Patents Issued in May 27, 2021
-
Publication number: 20210158815Abstract: Disclosed are a method and apparatus for remotely controlling an imaging apparatus. A method of controlling a remote control apparatus includes converting a spoken utterance of a user into an utterance text or receiving the utterance text, applying a generative model-based first learning model to the utterance text and generating an image having attributes corresponding to a context of the utterance text, and externally transmitting the image and the utterance text. In addition, a method of controlling an imaging apparatus includes receiving a first input including text or speech data and a second input including a first image, capturing at least one second image based on the first input, comparing the first image and the second image, and transmitting the second image in response to a comparison result of the first image and the second image.Type: ApplicationFiled: March 2, 2020Publication date: May 27, 2021Applicant: LG ELECTRONICS INC.Inventor: Kwangyong LEE
-
Publication number: 20210158816Abstract: A method, apparatus, device, and storage medium for voice interaction. A specific embodiment of the method includes: extracting an acoustic feature from received voice data, the acoustic feature indicating a short-term amplitude spectrum characteristic of the voice data; applying the acoustic feature to a type recognition model to determine an intention type of the voice data, the intention type being one of an interaction intention type and a non-interaction intention type, and the type recognition model being constructed based on the acoustic feature of training voice data; and performing an interaction operation indicated by the voice data, based on determining that the intention type is the interaction intention type.Type: ApplicationFiled: June 8, 2020Publication date: May 27, 2021Inventors: Xiaokong Ma, Ce Zhang, Jinfeng Bai, Lei Jia
-
Publication number: 20210158817Abstract: A dynamic speech recognition method includes performing a first stage: detecting sound data by using a digital microphone and storing the sound data in a first memory, generating a human voice detection signal in response to detecting a human voice from the sound data, and determining to selectively perform a second stage or a third stage according to a total effective data volume, a transmission bit rate of the digital microphone and a recognition interval time. In the second stage, the first processing circuit outputs a first command to a second processing circuit, and the second processing circuit instructs a memory access circuit to operate. In the third stage, the first processing circuit outputs a second command to the second processing circuit, and the second processing circuit instructs the memory access circuit to operate, and the second processing circuit determines whether the speech data matches a predetermined speech command.Type: ApplicationFiled: July 29, 2020Publication date: May 27, 2021Applicant: REALTEK SEMICONDUCTOR CORP.Inventors: Mei-Hua Wang, Ching-Lung Chen
-
Publication number: 20210158818Abstract: The present disclosure relates to methods, computer programs, and computer-readable media for processing a voice audio signal. A method includes receiving, at an electronic device, a voice audio signal, identifying spoken phrases within the voice audio signal based on the detection of voice activity or inactivity, dividing the voice audio signal into a plurality of segments based on the identified spoken phrases, and in accordance with a determination that a selected segment of the plurality of segments has a duration, Tseg, longer than a threshold duration, Tthresh, identifying a most likely location of a breath in the audio associated with the selected segment and dividing the selected segment into sub-segments based on the identified most likely location of a breath.Type: ApplicationFiled: April 16, 2020Publication date: May 27, 2021Applicant: Sonocent LimitedInventor: Roger Tucker
-
Publication number: 20210158819Abstract: Disclosed is an electronic device performing voice recognition on user utterance based on first voice assistance. The electronic device may receive information on recognition characteristic of second voice assistance for user utterance from an external device and adjust recognition characteristic of the first voice assistance based on the information on the recognition characteristic of the second voice assistance.Type: ApplicationFiled: November 24, 2020Publication date: May 27, 2021Applicant: Samsung Electronics Co., Ltd.Inventor: Dongwan KIM
-
Publication number: 20210158820Abstract: Systems and methods for providing an online to offline service in response to a voice request from a user terminal are provided. A method includes: receiving a voice request from a user terminal; in response to the voice request, updating a customized recognition model trained using data of a plurality of points of interest associated with the user terminal; obtaining a general recognition model trained using data from general public; determining a literal destination associated with the voice request based at least on the voice request, the customized recognition model and the general recognition model.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Applicant: BEIJING DIDI INFINITY TECHNOLOGY AND DEVELOPMENT CO., LTD.Inventor: Chen HUANG
-
Publication number: 20210158821Abstract: Provided are an image display apparatus and a method of controlling the same. The image display apparatus enabling voice recognition includes: a first voice inputter which receives a user-side audio signal; an audio outputter which outputs an audio signal processed by the image display apparatus; a first voice recognizer which recognizes the user-side audio signal received through the first voice inputter; and a controller which decreases a volume of the audio signal output through the audio outputter to a predetermined level if a voice recognition start command is received.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae Gyu BAE, Tae Hwan CHA, Ho Jeong YOU
-
Publication number: 20210158822Abstract: Methods and systems are provided for customizing an action. In some implementations, voice input is received from a user and a context is determined from the voice input. Potential contextual data is identified based on the context and the voice input. A level of confidence is determined for an association of the potential contextual data and the context. An action is performed based on the voice input, the potential contextual data, and the level of confidence. The potential contextual data is used to customize the action.Type: ApplicationFiled: February 8, 2021Publication date: May 27, 2021Applicant: Google LLCInventors: Zoltan Stekkelpak, Gyula Simonyi
-
Publication number: 20210158823Abstract: According to embodiments of the disclosure, a method and an apparatus for processing a speech signal, and a computer-readable storage medium are provided. The method includes obtaining a set of speech feature representations of a speech signal received. The method also includes generating a set of source text feature representations based on a text recognized from the speech signal, each source text feature representation corresponding to an element in the text. The method also includes generating a set of target text feature representations based on the set of speech feature representations and the set of source text feature representations. The method also includes determining a match degree between the set of target text feature representations and a set of reference text feature representations predefined for the text, the match degree indicating an accuracy of recognizing of the text.Type: ApplicationFiled: June 22, 2020Publication date: May 27, 2021Inventors: Chuanlei ZHAI, Xu CHEN, Jinfeng BAI, Lei JIA
-
Publication number: 20210158824Abstract: Disclosed is an electronic device capable of improving voice recognition. The electronic device includes a sound receiver, and a processor configured to: acquire a sound signal received by the sound receiver, separate the acquired sound signal into a plurality of sound source signals, detect signal characteristics of each of the plurality of separated sound source signals, and identify a sound source signal corresponding to a user utterance voice among the plurality of sound source signals based on predefined information on a correlation between the detected signal characteristics and the user utterance voice.Type: ApplicationFiled: November 24, 2020Publication date: May 27, 2021Applicant: Samsung Electronics Co., Ltd.Inventor: Eunheui JO
-
Publication number: 20210158825Abstract: A method, system, and computer program to encode and decode a channel coherence parameter applied on a frequency band basis, where the coherence parameters of each frequency band form a coherence vector. The coherence vector is encoded and decoded using a predictive scheme followed by a variable bit rate entropy coding.Type: ApplicationFiled: April 5, 2019Publication date: May 27, 2021Applicant: Telefonaktiebolaget LM Ericsson (publ)Inventors: Erik NORVELL, Fredrik JANSSON
-
Publication number: 20210158826Abstract: Systems and methods are disclosed for detecting and removing traceable identifying audio content from electronic media content. One method includes: receiving, over a network, media content to be broadcast or distributed, the media content including audio data; determining whether the audio data of the media content includes traceable identifying audio content defined by an audio identifier; generating new audio data based on the audio data of the media content when an audio identifier is determined to be include in the audio data; removing audio data from the media content when the audio identifier is determined to be include in the audio data; adding the new audio data to the media content when the audio data is removed from the media content; and broadcasting or distributing the media content having the new audio data to one or more user devices.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Inventors: Seth Mitchell DEMSEY, Jay CRYSTAL
-
Publication number: 20210158827Abstract: The present document relates to time-alignment of encoded data of an audio encoder with associated metadata, such as spectral band replication (SBR) metadata. An audio decoder configured to determine a reconstructed frame of an audio signal from an access unit of a received data stream is described. The access unit comprises waveform data and metadata, wherein the waveform data and the metadata are associated with the same reconstructed frame of the audio signal. The audio decoder comprises a waveform processing path configured to generate a plurality of waveform subband signals from the waveform data, and a metadata processing path configured to generate decoded metadata from the metadata.Type: ApplicationFiled: October 2, 2020Publication date: May 27, 2021Applicant: DOLBY INTERNATIONAL ABInventors: Kristofer KJOERLING, Heiko PURNHAGEN, Jens POPP
-
Publication number: 20210158828Abstract: An audio privacy processing device includes a microphone array device that acquires audio from a person in a designated audio pick-up area, and a signal processor that receives the acquired audio over a network and determines when an audio position of the person is within a privacy protection area in the designated audio pick-up area. The audio privacy processing device also includes an audio analyzer that analyzes speech audio of the person in the privacy protection area and determines an emotion of the person based on the analyzed speech audio by accessing a privacy protection sound database that includes emotion value tables, and an output controller that outputs a designated substitute sound and designated frequency from a speaker in place of the speech audio of the person while the person is in the privacy protection area.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hisashi TSUJI, Ryota FUJII, Hisahiro TANAKA
-
Publication number: 20210158829Abstract: A method includes obtaining first audio data corresponding to speech occurring within a communication area. The first audio data is obtained from one or more interior locations inside the communication area. The method includes obtaining second audio data corresponding to the speech. The second audio data is obtained from one or more exterior locations outside of the communication area. The method includes calculating a first intelligibility based on the first audio data and calculating a second intelligibility based on the second audio data. The method includes comparing the first intelligibility to the second intelligibility, and determining, based on the comparing, that the second intelligibility exceeds a threshold. The method includes generating a set of countermeasures in response to the determining. The set of countermeasures includes at least one modification to a parameter of the speech. The method includes providing at least one countermeasure of the set of countermeasures.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Gianluca Gargaro, MATTEO ROGANTE, ANGELA GHIDONI, Sara Moggi
-
Publication number: 20210158830Abstract: A multichannel audio system with a plurality of multichannel speakers having microphones, where the system receives audio signals from multichannel speakers, an adaptive filter enhances the voice signal portion of the audio signal by canceling interference in the audio signals by eliminating the portion of the audio signal matching reference signals, and processing the voice signal into voice commands.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Applicant: Summit Wireless Technologies, Inc.Inventor: Kenneth A. Boehlke
-
Publication number: 20210158831Abstract: Methods and systems for determining periods of excessive noise for smart speaker voice commands. An electronic timeline of volume levels of currently playing content is made available to a smart speaker. From this timeline, periods of high content volume are determined, and the smart speaker alerts users during periods of high volume, requesting that they wait until the high-volume period has passed before issuing voice commands. In this manner, the smart speaker helps prevent voice commands that may not be detected, or may be detected inaccurately, due to the noise of the content currently being played.Type: ApplicationFiled: February 3, 2021Publication date: May 27, 2021Inventors: Gyanveer Singh, Sukanya Agarwal, Vikram Makam Gupta
-
Publication number: 20210158832Abstract: A method for evaluating performance of a speech enhancement algorithm includes: acquiring a first speech signal including noise and a second speech signal including noise, wherein the first speech signal is acquired from a near-end audio acquisition device close to a sound source, the second speech signal is acquired from a far-end audio acquisition device far from the sound source, and the near-end audio acquisition device is closer to the sound source than the far-end audio acquisition device; acquiring a pseudo-pure speech signal based on the first speech signal and the second speech signal, as a reference speech signal; enhancing the second speech signal by using a preset speech enhancement algorithm, to obtain a denoised speech signal to be tested; and acquiring a correlation coefficient between the reference speech signal and the speech signal to be tested, for evaluating the speech enhancement algorithm.Type: ApplicationFiled: May 13, 2020Publication date: May 27, 2021Inventors: Yuhong YANG, Linjun Cai, Fei Xiang, Shicong Li, Jiaqian Feng, Weiping Tu, Haojun Al
-
Publication number: 20210158833Abstract: A computer device (100) for processing audio signals is described. The computer device (100) includes at least a processor and a memory. The computer device (100) is configured to receive a bitstream comprising a combined audio signal, the combined audio signal comprising a first audio signal including speech and a second audio signal. The computer device (100) is configured to compress the combined audio signal to provide a compressed audio signal. The computer device (100) is configured to control a dynamic range of the compressed audio signal to provide an output audio signal. In this way, a quality of the speech included in the output audio signal is improved.Type: ApplicationFiled: October 19, 2018Publication date: May 27, 2021Inventor: Michael Cooke
-
Publication number: 20210158834Abstract: There are provided herein, a method and system for creating a speech/language pathologies classifier, the method comprising: producing a pathological speech repository of pathological speech samples of multiple impairments; computing speech qualities/pathologies, based on data receive from the pathological speech repository; producing a text repository, the text repository comprises multiple known text passages; converting each one of a selection of the text passages from the multiple known text passages, to a speech segment, while introducing to the speech segment one or more of the computed speech pathologies, thereby creating multiple synthetic impaired speech segments; and training a classifier with the multiple synthetic impaired speech segments thereby creating a speech/language pathologies classifier.Type: ApplicationFiled: April 17, 2019Publication date: May 27, 2021Inventors: Yoav MEDAN, Shai SHAPIRA
-
Publication number: 20210158835Abstract: A network validation system is described which may perform operations such as generating, analyzing, verifying, correcting, recommending, and deploying language, symbols, etc., such as domain specific language, configured to allow users to express their intent on the configuration and operation of a network, such as a cloud-based network. The network validation system may provide domain specific language that includes rules, statements, symbols, data, etc., configured to convey the intent of users on the configuration and operation of networks for purposes such as configuring and/or validating communication paths, testing or setting associated network object configurations, and may be employed to report violations in such configurations relative to user intent of the one or more users. The network validation system may also be employed to monitor such domain specific language and generate telemetry signaling, for example, that a rule has or has not been violated, actions a user may take, etc.Type: ApplicationFiled: November 21, 2019Publication date: May 27, 2021Applicant: Oracle International CorporationInventors: Peter J. Hill, Jagwinder Brar, Yogesh Sreenivasan
-
Publication number: 20210158836Abstract: Provided is an information processing device including an output control unit that controls presentation of content to a user, and when a non-viewing/listening period is detected in a viewing and listening behavior of the user corresponding to the content, causes a summary of the content to be output. The output control unit determines an amount of information in the summary of the content, based on the length of the non-viewing/listening period. Moreover, provided is an information processing method including: by a processor, controlling presentation of content to a user; and when a non-viewing/listening period is detected in a viewing and listening behavior of the user corresponding to the content, causing a summary of the content to be output. The causing the summary of the content to be output further includes determining an amount of information in the summary of the content, based on the length of the non-viewing/listening period.Type: ApplicationFiled: April 24, 2018Publication date: May 27, 2021Applicant: Sony CorporationInventors: Hiro IWASE, Shinichi KAWANO, Mari SAITO, Yuhei TAKI
-
Publication number: 20210158837Abstract: A device includes a processor configured to receive audio data samples and provide the audio data samples to a first neural network to generate a first output corresponding to a first set of sound classes. The processor is further configured to provide the audio data samples to a second neural network to generate a second output corresponding to a second set of sound classes. A second count of classes of the second set of sound classes is greater than a first count of classes of the first set of sound classes. The processor is also configured to provide the first output to a neural adapter to generate a third output corresponding to the second set of sound classes. The processor is further configured to provide the second output and the third output to a merger adapter to generate sound event identification data based on the audio data samples.Type: ApplicationFiled: November 24, 2020Publication date: May 27, 2021Inventors: Fatemeh SAKI, Yinyi GUO, Erik VISSER, Eunjeong KOH
-
Publication number: 20210158838Abstract: A head shell enabling easy and accurate regulation of overhang is provided. A head shell is attachable to and detachable from a connector of a tone arm of a record player, and holds a pickup cartridge. The head shell includes a cylinder attachable to and detachable from the connector, a head shell main body held to the cylinder, and a fixing screw capable of fixing the head shell main body to the cylinder. The cylinder includes a cylindrical cylinder external circumferential surface and a groove disposed on the cylinder external circumferential surface along an axial direction of the cylinder. A space is defined between the fixing screw and the groove in a circumferential direction of the cylinder.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Inventor: Aya MASHIMO
-
Publication number: 20210158839Abstract: The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The magnetic recording head comprises a first write head, a second write head, at least one read head, and a thermal fly height control element. The first write head is a wide writing write head comprising a first main pole and a first trailing shield. The second write head a narrow writing write head comprising a second main pole, a trailing gap, a second trailing shield, and one or more side shields. The first main pole has a shorter height and a greater width than the second main pole. The second main pole has a curved or U-shaped surface disposed adjacent to the trailing gap. The thermal fly height control element and the at least one read head are aligned with a center axis of the second main pole of the second write head.Type: ApplicationFiled: August 24, 2020Publication date: May 27, 2021Inventors: Thao A. NGUYEN, Michael Kuok San HO, Zhigang BAI, Zhanjie LI, Quang LE
-
Publication number: 20210158840Abstract: An approach to forming a tape head with a first soft bias pinning layer in a tape head structure. The tape head structure includes an antiferromagnetic material forming the first soft bias pinning layer over a sensor and stitching into a soft bias layer surrounding the sensor where the antiferromagnetic material of the first soft bias pinning layer has a lower magnetic reluctance than a material forming a freelayer in the sensor. Furthermore, the tape head structure includes a first spacer separated from the first soft bias pinning layer by the sensor in the tape head structure and a second spacer layer over the first soft bias pinning layer where a thickness of the first spacer and the second spacer is determined by an optimum shield to shield distance in the tape head structure.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: David Seagle, Robert Biskeborn, Robert Fontana, Icko E. T. Iben
-
Publication number: 20210158841Abstract: A storage array includes a plurality of hard disks, each of the hard disks is divided into a plurality of chunks, and a plurality of chunks of different hard disks form a chunk group by using a redundancy algorithm. The storage array obtains fault information of a faulty area in a first hard disk, and determines a faulty chunk storing the lost data according to the fault information. The storage array recovers the data in the faulty chunk by using another chunk in a chunk group to which the faulty chunk belongs and stores the recovered data in a recovered chunk. The recovered chunk is located in a second hard disk which is not a hard disk for forming the chunk group.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Guoxia Liu, Liming Wu
-
Publication number: 20210158842Abstract: An information processing device functioning as a video editing device editing a video to be projected by a projector includes a display control unit, an acquisition unit, and a decision unit. The display control unit causes a display device of a touch panel to display an editing screen including a video display area where a video to be projected by a projector is displayed. The acquisition unit acquires, from the projector, information representing an aspect ratio of a projected video projected by the projector. The decision snit decides the video display area according to the aspect ratio represented by the information acquired by the acquisition unit.Type: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Inventor: Kentaro IDE
-
Publication number: 20210158843Abstract: A future thinking mobile application, which may allow one or more users to interact with their loved ones as if it is happening in real time is presented. The application may allow or enable a user to record one or more circular images or videos. The application may further facilitate to have a series of prerecorded video or audio questions that can be loaded into the application. This can be used by the user to conduct own personal interviews. The application may further ensure a delivery of multiple digital content to respective recipients when the user is inactive in the application for a defined time duration. The application may further facilitate a circular media player which layouts media content in an orbital fashion. The application may further enable or allow the user to add voice or audio components to a static image.Type: ApplicationFiled: February 2, 2021Publication date: May 27, 2021Inventors: Shabazz Lalumba Graham, Olawale Oluwadamilere Omotayo Dada
-
Publication number: 20210158844Abstract: An enhanced video book and a system and method for creating an enhanced video book are described. Artwork and text corresponding to a storyline can be converted into a format that can be animated. A timing is established at which the converted artwork can be displayed, at a pace corresponding to the timing at which the converted text can be read. The converted artwork and/or the converted text are animating, and voice-over narration corresponding to the converted text is generated. The display of the converted artwork or the converted text is adjusted and synchronized with the voice-over narration based on the timing at which the converted artwork can be displayed. Audio is added and synchronized to the converted artwork. The converted artwork, the converted text, the animated or converted artwork, the animated converted text, the voice-over narration, and the audio are combined into an enhanced video book.Type: ApplicationFiled: November 20, 2020Publication date: May 27, 2021Inventors: Russell Powell Hirtzel, Marshall Bex, IV
-
Publication number: 20210158845Abstract: In some examples, a server retrieves a video and performs an audio analysis of an audio portion of the video and a video analysis of a video portion of the video. The video may provide information on modifying a hardware configuration and/or a software configuration of a computing device. The audio analysis performs natural language processing to the audio portion to determine a set of words indicative of a start and/or end of a segment. The video analysis uses a convolutional neural network to analyze the video portion to determine frames in the video portion indicative of a start and/or end of a segment. Machine learning segments the video by adding chapter markers based on the video analysis and the audio analysis. The video is indexed, hyperlinks are associated with each segment, and each hyperlink named to enable a user to select and stream a particular segment.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Parminder Singh Sethi, Sathish Kumar Bikumala
-
Publication number: 20210158846Abstract: A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.Type: ApplicationFiled: June 19, 2018Publication date: May 27, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tatsuya ONUKI, Shuhei NAGATSUKA
-
Publication number: 20210158847Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.Type: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-shin YOO, Min-su KIM, Hyun-chul HWANG
-
Publication number: 20210158848Abstract: A semiconductor memory device operated under control of a controller. The semiconductor memory device including a control logic and a data input/output circuit. The control logic configured to store logic data and generate a plurality of pieces of circular data based on the logic data in response to an output command of the logic data that is received from the controller. The data input/output circuit configured to select circular data corresponding to a set warm-up cycle among the plurality of pieces of circular data and output the selected circular data to the controller.Type: ApplicationFiled: May 11, 2020Publication date: May 27, 2021Applicant: SK hynix Inc.Inventors: Ja Yoon GOO, Sung Hwa OK
-
Publication number: 20210158849Abstract: Provided are a magnetoresistive element, a magnetic memory device, and a writing and reading method for a magnetic memory device, in which an aspect ratio of a junction portion can be decreased. A magnetoresistive element 1 of the invention, includes: a heavy metal layer 2 that is an epitaxial layer; and a junction portion 3 including a recording layer 31 that is provided on the heavy metal layer 2 and includes a ferromagnetic layer of an epitaxial layer magnetized in an in-plane direction, which is an epitaxial layer, a barrier layer 32 that is provided on the recording layer 31 and includes an insulating body, and a reference layer 33 that is provided on the barrier layer 32 and has magnetization fixed in the in-plane direction, in which the recording layer 31 is subjected to magnetization reversal by applying a write current to the heavy metal layer 2.Type: ApplicationFiled: April 11, 2019Publication date: May 27, 2021Inventors: Yoshiaki Saito, Shoji Ikeda, Hideo Sato, Tetsuo Endoh
-
Publication number: 20210158850Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Alexander Reznicek, Eric Raymond Evarts, Virat Vasav Mehta, Bahman Hekmatshoartabari
-
Publication number: 20210158851Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.Type: ApplicationFiled: February 8, 2021Publication date: May 27, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
-
Publication number: 20210158852Abstract: An arithmetic device includes an auto-command/address generation circuit, a first data storage circuit, and a second data storage circuit. The auto-command/address generation circuit generates an auto-load selection signal that activates an auto-load operation based on a level of a power source voltage. In addition, the auto-command/address generation circuit generates an auto-load command for the auto-load operation. The first data storage circuit outputs look-up table data, to which an activation function is applied, based on the auto-load command. The second data storage circuit stores the look-up table data, output from the first data storage circuit, based on the auto-load command.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Applicant: SK hynix Inc.Inventor: Choung Ki SONG
-
Publication number: 20210158853Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.Type: ApplicationFiled: July 1, 2020Publication date: May 27, 2021Inventors: Ming-Hung Wang, Chun-Peng Wu
-
Publication number: 20210158854Abstract: A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.Type: ApplicationFiled: September 28, 2020Publication date: May 27, 2021Inventor: Mahmut Sinangil
-
Publication number: 20210158855Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Arijit Banerjee, Russell Schreiber, Kyle Whittle
-
Publication number: 20210158856Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.Type: ApplicationFiled: June 17, 2020Publication date: May 27, 2021Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
-
Publication number: 20210158857Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.Type: ApplicationFiled: October 22, 2020Publication date: May 27, 2021Applicant: MACRONIX International Co., Ltd.Inventors: Ming-Liang Wei, Po-Kai Hsu, Hang-Ting Lue, Teng-Hao Yeh
-
Publication number: 20210158858Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.Type: ApplicationFiled: December 24, 2020Publication date: May 27, 2021Inventors: Xinyu Wu, Dong Pan
-
Publication number: 20210158859Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.Type: ApplicationFiled: November 18, 2020Publication date: May 27, 2021Inventors: Mohit Gupta, Manu Komalan Perumkunnil
-
Publication number: 20210158860Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Jun Wu, Liang Li, Yu Zhang, Dong Pan
-
Publication number: 20210158861Abstract: The present disclosure relates to a semiconductor memory device. The semiconductor memory device includes memory cell array, error correction code (ECC) engine, refresh control circuit and control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine such that the ECC engine generates an error generation signal by performing ECC decoding on sub-pages in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value and provides the refresh control circuit with a first address of the first memory cell row as an error address based on the comparison. The refresh control circuit increases a number of refresh operations performed in the first memory cell row during a refresh period.Type: ApplicationFiled: June 15, 2020Publication date: May 27, 2021Inventors: YUNKYEONG JEONG, CHULHWAN CHOO
-
Publication number: 20210158862Abstract: A refresh tracking circuit and associated methods are disclosed herein. The tracking circuit may be configured to track a primary count value and a secondary count value based on addresses associated with received commands. The primary and secondary count values may be configured to control corresponding refresh operations respectively associated with a primary address and a secondary address.Type: ApplicationFiled: February 4, 2021Publication date: May 27, 2021Inventor: Sadayuki Okuma
-
Publication number: 20210158863Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory row and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Dale H. Hiscock, Debra M. Bell, Michael Kaminski, Joshua E. Alzheimer, Anthony D. Veches, James S. Rehmeyer
-
Publication number: 20210158864Abstract: An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line (BL); and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's (WX and WY). The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Hidehiro Fujiwara, Yen-Huei Chen, Yi-Hsin Nien