Abstract: A ferroelectric capacitor of a memory cell may be in electronic communication with a sense capacitor through a digit line. The digit line may be virtually grounded during memory cell sensing, limiting or avoiding voltage drop across the digit line, and allowing all or substantially all of the stored charge of the ferroelectric capacitor to be extracted and transferred to the sense capacitor. Virtually grounding the digit line may be achieved by activating a switching component (e.g., a p-type field-effect transistor) that is electronic communication with the digit line. The charge of the ferroelectric capacitor may be transferred through the switching component. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.

Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.

Abstract: Provided is a semiconductor storage element including a first transistor having a gate insulation film that includes a ferroelectric material at least partially and being a transistor to which information is written, and a second transistor that is coupled to, at one of a source and a drain, a source or drain of the first transistor. The first transistor has a threshold voltage smaller than 0 V when writing information and a threshold voltage smaller than 0 V when erasing information.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.

Abstract: A memory module includes a plurality of memory devices each including a memory cell array, and a register clock driver connected to the memory devices. The register clock driver detects a row hammer address among row addresses corresponding to word lines of the memory cell array, converts a refresh command, among a plurality of refresh commands received from a memory controller for refreshing the memory cell array, to a row hammer refresh command, and transmits the row hammer refresh command and the row hammer address to each of the memory devices.

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

Abstract: Technologies for a multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.

Abstract: A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation.

Abstract: A semiconductor memory device includes a bitline driver configured to drive a global bitline; a memory cell array including a first memory cell that is coupled between a cell wordline and a cell bitline; a bitline decoder including a bitline switch that couples the global bitline and the cell bitline; a wordline decoder including a wordline switch that couples a global wordline and the cell wordline; a sense amplifier configured to output a sensing signal corresponding to a state of the first memory cell based on a voltage of the global bitline; and a control circuit configured to control the bitline driver, the bitline decoder, the wordline decoder and the sense amplifier during a first read operation for the first memory cell.

Abstract: Provided is a method including acquiring reading and writing information of logical chunks of a storage apparatus in a number of historical periods before a current time, and predicting reading and writing information of the logical chunks in a next period according to reading and writing information of the logical chunks in a number of historical periods before the current time and a data prediction model. The data prediction model indicates a relationship between reading and writing information of the logical chunks in a next period and reading and writing information of the logical chunks in a number of historical periods before the current time.

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: In writing and reading data at a semiconductor storage device, control is carried out such that, at a time of a burst mode, in a case in which a value of a block address which is, from addresses assigned to a region of an internal address, an address for selecting a sense amplifier block from plural sense amplifier blocks, is a largest value, a first sense amplifier block and a second sense amplifier block are made to access different banks, and, in case in which the value of the block address is not the largest value, the first sense amplifier block and the second sense amplifier block are made to access a same bank of plural banks.

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.

Abstract: Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.

Abstract: Latch circuitry configured to latch data for use in the memory device. The latch circuitry includes latch cells each configured to store a bit of the data. The latch circuitry also includes a data line coupled to a first side of the latch cells and a data false line coupled to a second side of the latch cells. The latch circuitry also includes a write driver that includes an input configured to receive the data to be stored in the latch cells and a pair of inverters coupled to the input and configured to output a data signal to a first side of the latch cells. The latch circuitry also includes an inverter coupled to the input and configured to generate a data false signal to a second side of the latch cells. The data used to generate the data false signal is not passed through the pair of inverters.

Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

Abstract: A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.

Abstract: A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n?1)-th stepped voltage level of the post-write pulse.

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Abstract: The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. There are more FRAM cells than SRAM cells. The first memory array and the second memory array share the same bus.

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region. The memory cell region includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

Abstract: A memory system includes a memory device including memory sets and a controller including a decoder. The decoder receives multiple codewords from the memory sets and decodes the multiple codewords. The decoder determines an inter-set delay for a codeword of a select memory set. When the inter-set delay is greater than a maximum inter-set delay, the decoder determines a total decoding time based on an effective inter-set delay and an effective decoding time. The decoder outputs the decoded codeword at the end of the total decoding time.

Abstract: In one example, a nonvolatile memory device, such as a NAND flash memory device, includes an array of non-volatile memory cells. Program operations performed by the memory may be suspended (e.g., in order to service a high priority read request). The memory device includes a timer to track a duration of time the program operation is suspended. Upon program resume, the controller applies a program voltage after resume that is adjusted based on the duration of time the program operation is suspended.

Abstract: A data arranging method, a memory control circuit unit and a memory storage device for flash memory are provided. The method can be applied to a flash memory with a three-dimensional (3D) structure, an embedded memory device, or a solid-state hard disk. The method includes: writing at least one piece of data to at least one second physical erasing unit of at least one first physical erasing unit, and obtaining a distribution state of valid data in a plurality of physical erasing units; adjusting a specific threshold value according to the distribution state; and when the number of the at least one first physical erasing unit is less than the specific threshold value, performing a valid data merging operation.

Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.

Abstract: Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.

Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.

Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.

Abstract: A memory device includes a plurality of memory blocks and each memory block includes a plurality of columns of memory cells. Each column of memory cells is coupled to a corresponding bit line. Upon completion of a power-up sequence, detect if a current leakage of corresponding columns in a group of memory blocks is greater than a predetermined level. If the current leakage of the corresponding columns in the group of memory blocks is greater than the predetermined level, perform an over-erasure correction on the corresponding columns.

Abstract: A high current fast read scheme can enable improved read disturb without negatively impacting read performance. In one example, a fast read scheme involves applying a higher current as soon as the cell thresholds. In one example, circuitry detects the threshold event and turns on a bypass control transistor to bypass the circuitry applying the read voltage to enable a higher voltage and therefore higher current as soon as possible. The read time can thus be decreased (or at least not increased) and read disturb improved.

Abstract: A shift register unit, a gate drive circuit, a display device and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit and an anti-crosstalk circuit. The first input circuit is configured to input a first input signal to a first node; the second input circuit is configured to input a second input signal to the first node in a situation where the second node is at a first level and to stop inputting the second input signal to the first node in a situation where the second node is at a second level; the output circuit is configured to output or not output an output signal; the anti-crosstalk circuit is configured to prevent a level of the second node from becoming the first level in a situation where the second node is at the second level.

Abstract: A memory system includes: a memory device including a plurality of memory blocks; a memory; a data classifier suitable for classifying check-pointing information stored in the memory as selective information and mandatory information; and a check-pointing component suitable for performing a control to periodically perform a check-pointing operation of programming the selective information and the mandatory information in a memory block, wherein the check-pointing component performs the check-pointing operation by performing a control to program the mandatory information after programming the selective information.

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.

Abstract: Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

Abstract: In pattern discovery visual analytics, a patient data table (14) is generated that tabulates, for each patient, attribute values for a set of attributes. A positive or negative prediction is generated for each patient for a target value of a target attribute using a prediction pattern (20) of attribute values for w attributes (22). The prediction is positive if at least a threshold fraction (26) of the w attributes of the patient match the prediction pattern, is negative otherwise. Patients are grouped into a selected proportion of a confusion matrix (30) in accord with the positive or negative predictions and actual values of the target attribute T in the patient data table. A display component (4) displays a representation (42) of patient statistics for the selected proportion of the confusion matrix on a per-attribute basis for attributes of the w attributes. A patient cohort (44) is identified using the representation.

Abstract: A computer implemented method of generating new chemical compounds is provided. The method includes preparing a data-driven substructure feature vector for each of a plurality of chemical compounds for which a chemical or physical property is known. The method further includes preparing a predefined component feature vector, creating a regression model to predict a target value for the chemical or physical property, and performing a search algorithm to identify substructure features that affect the target value for the chemical or physical property. The method further includes generating a candidate structure having the target value for the chemical or physical property, and synthesizing the candidate structure.

Abstract: Systems, methods, and apparatus providing automated clinical case creation and routing are disclosed and described. An example cloud-based medical image and document exchange infrastructure apparatus includes an instruction processor to execute an instruction to process data according to one or more defined rules, wherein the instruction is associated with a state, the state including at least active and inactive. The example apparatus also includes a gateway to at least: receive incoming data related to an imaging study; monitor the incoming data to compare the incoming data to one or more active instructions; and, when an active instruction applies to the incoming data, execute the active instruction with respect to the corresponding imaging study.

Abstract: A system to remotely perform medication reconciliation for a patient in a health care facility using medication records for the patient stored in a client computing device is provided. The system can include the client computing device, servers to securely transfer medication records between the client computing device and a health care facility computer system. The servers, client computing device and a health care facility computer system communicatively coupled via the Internet.

Abstract: A system for assigning concepts to a medical image includes a visual feature module and a tagging module. The visual feature module is configured to obtain an image feature vector from the medical image. The tagging module is configured to apply a machine-learned algorithm to the image feature vector to assign a set of concepts to the image. The system may also include a text report generator that is configured to generate a written report describing the medical image based on the set of concepts assigned to the medical image.

Abstract: Systems, methods, and computer-readable mediums for modifying, by an artificial intelligence engine, a treatment plan for optimizing patient outcome and pain levels during treatment sessions. The system includes, in one implementation, a treatment apparatus, a patient interface, and a computing device. The treatment apparatus is configured to be manipulated by a patient while the patient performs the treatment sessions. The computing device is configured to receive the treatment plan for the patient and treatment data pertaining to the patient. The computing device is also configured to receive patient input from the patient interface correlating with the pain levels of the patient. The computing device is further configured to use the treatment plan, the treatment data, and the patient input to generate at least one threshold. Responsive to an occurrence of exceeding the at least one threshold, the computing device is configured to modify the treatment plan.