Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

Abstract: A photovoltaic cell device and a manufacturing method of a template thereof are provided. The manufacturing method of the template of the photovoltaic cell device includes the steps of providing a substrate and a target disposed opposite to each other in a chamber, applying an unbalanced magnetic field, and generating a plasma in the chamber to form a sputtered layer on the substrate. The plasma extends to an area proximate to the substrate due to the unbalanced magnetic field to assist the crystallization of the sputtered layer, so that the sputtered layer has a single crystalline or a single crystalline-like structure.

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

Abstract: There is provided a method of forming a layer, comprising depositing a seed layer on the substrate and depositing a bulk layer on the seed layer. Depositing the seed layer comprises supplying a first precursor comprising metal and halogen atoms to the substrate; and supplying a first reactant to the substrate. Depositing the bulk layer comprises supplying a second precursor comprising metal and halogen atoms to the seed layer and supplying a second reactant to the seed layer.

Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.

Abstract: A substrate processing method performed in a substrate processing apparatus includes providing a substrate which has a first film composed of silicon only and a second film including silicon; and etching the first film by plasma formed from a mixed gas including a halogen-containing gas and a silicon-containing gas but not including an oxygen-containing gas.

Abstract: A method for etching a surface including obtaining a substrate comprising a material; reacting a surface of a substrate with a reactant, comprising a gas or a plasma, to form a reactive layer on the substrate, the reactive layer comprising a chemical compound including the reactant and the material; and wet etching or dissolving the reactive layer with a liquid wet etchant of solvent that selectively etches or dissolves the reactive layer but not the substrate.

Abstract: There is provided a structure manufacturing method, including: preparing an etching target with at least one surface comprising group III nitride; then in a state where the etching target is immersed in an etching solution containing peroxodisulfate ions, irradiating the surface of the etching target with light through the etching solution, and generating sulfate ion radicals from the peroxodisulfate ions and generating holes in the group III nitride, thereby etching the group III nitride, wherein in the etching of the group III nitride, the etching solution remains acidic during a period for etching the group III nitride by making the etching solution acidic at a start of etching the group III nitride, and the etching is performed, with a resist mask formed on the surface.

Abstract: A treatment method is provided that includes an embedding step of embedding an organic film in an undercoat film in which a depression is formed; and an etching step of performing etching, after the embedding step, until at least a portion of a top of the undercoat film is exposed.

Abstract: The present invention relates to sensors comprising pattern illumination-based annealed coated substrate and one or more functional molecules and process of using same. Such process yields components that can have one or more electronic and/or optical functionalities that are integrated on the same substrate or film and to which one or more functional molecules can be attached to yield a sensor. In addition, such process does not require large-scale clean rooms and is easily configurable. Thus, rapid device prototyping, design change and evolution in the lab and on the production side is realized. The resulting sensors provide a sensing capability that is as good as or better than current sensors and can be tailored to sense specific biomaterials and/or chemicals.

Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

Abstract: An alkaline etchant containing a quaternary ammonium hydroxide, water, and an inhibitory substance for inhibiting contact between hydroxide ions generated from the quaternary ammonium hydroxide and objects P1 to P3 to be etched is prepared. The prepared etchant is supplied to a substrate in which the polysilicon-containing objects P1 to P3 to be etched and objects O1 to O3 not to be etched, which are different from the objects P1 to P3 to be etched, are exposed, thereby etching the objects P1 to P3 to be etched while preventing the objects O1 to O3 not to be etched from being etched.

Abstract: In accordance with an embodiment, a method of plasma processing includes etching a refractory metal by flowing oxygen into a plasma processing chamber, intermittently flowing a passivation gas into the plasma processing chamber, and supplying power to sustain a plasma in the plasma processing chamber.

Abstract: In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then, oxygen is introduced (added) to the oxide semiconductor layer through the oxide insulating layer, and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, so that the oxide semiconductor layer is highly purified.

Abstract: A method for manufacturing a semiconductor device includes forming first and second interconnect layers on first and second substrates, respectively; adhering the first and second substrates so that the back surfaces thereof face each other; bonding first and second semiconductor chips on the first and second interconnect layers, respectively; forming first and second molded bodies on the first and second substrates, respectively, while the first and second substrates are adhered; and detaching the first and second molded bodies from the first and second substrates. The first molded body includes the first interconnect layer, the first semiconductor chip and a first resin layer covering the first semiconductor chip on the first interconnect layer. The second molded body includes the second interconnect layer, the second semiconductor chip and a second resin layer covering the second semiconductor chip on the second interconnect layer. The first and second resin layers are formed simultaneously.

Abstract: A method for forming a chip package structure is provided. The method includes providing a wiring substrate including a substrate, a pad, and a polymer layer. The polymer layer is over the substrate and the pad, and the polymer layer has a first opening exposing the pad. The method includes forming a conductive adhesive layer over the polymer layer and the pad. The conductive adhesive layer is in direct contact with and conformally covers the polymer layer and the pad. The method includes forming a nickel layer over the conductive adhesive layer. The nickel layer is thicker than the conductive adhesive layer, and the nickel layer and the conductive adhesive layer are made of different materials. The method includes bonding a chip to the wiring substrate through a conductive bump. The conductive bump is between the nickel layer and the chip.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: An electroplating method that is a conventional method has had a problem that it is difficult to manufacture fine pillars without being affected by an undercut. Furthermore, an electroless plating method has had a problem that it is difficult to manufacture pillars having the same shape without any void. The inventors have performed intensive investigations to solve the above problems and, as a result, have found that fine conductive pillars with a high aspect ratio can be readily manufactured on a substrate having an electrode section in such a manner that after a conductive paste containing metal micro-particles is applied in a reduced pressure state, the conductive paste is exposed to standard pressure. The present invention has a particular effect on the manufacture of a metal pillar that is a terminal for flip-chip mounting.

Abstract: An upper flow passage 181 is connected to a buffer space 182. The upper flow passage 181 has a constant cross-sectional shape and a processing fluid flows as a laminar flow in the upper flow passage 181. On the other hand, the buffer space 182 has a larger flow passage cross-sectional area than the upper flow passage 181. Thus, the processing fluid flowing in the upper flow passage 181 is released at once into the wide buffer space 182, whereby the pressure of the processing fluid decreases. A backflow of the processing fluid from the buffer space 182 to the upper flow passage 181 is prevented due to this pressure difference and the magnitude of a flow passage resistance of the upper flow passage 181 viewed from the buffer space 182.

Abstract: A processing fluid flows into a processing space SP by way of a flow passage and discharge openings 174, 178 having substantially the same cross-sectional shape as that of a gap space formed in a clearance between a wall surface of the processing space SP and a substrate holder 15. On the other hand, the processing fluid having passed through the processing space SP is discharged to an outside via discharge flow passages 183, 187 after flowing into the buffer space 182, 186 having substantially the same width as the gap space. From these, the processing fluid can be caused to flow into the buffer space 182, 186 while the laminar flow state is maintained in the gap space. Thus, the generation of a turbulence in the processing space SP can be suppressed.

Abstract: The present disclosure relates to an apparatus for wafer cleaning. The apparatus includes an enclosure made of a noncombustible material, a wafer holder, a cleaning nozzle, at least one sensor, and an exhaust unit. The wafer holder can hold and heat a wafer. The cleaning nozzle can supply a flow of a cleaning fluid onto a surface of the wafer. The at least one sensor can detect attributes of the wafer. The exhaust unit can expel a vapor generated by the cleaning fluid in the enclosure. The exhaust unit can include a rinse nozzle to rinse the vapor passing through the exhaust unit with a mist.

Abstract: An upper member is disposed at an upper portion within a processing chamber. A ceiling member forms a ceiling of the processing chamber, and is provided with a through hole at a facing surface thereof which faces the upper member. A supporting member supports the upper member with a first end thereof located inside the processing chamber by being inserted through the through hole and slid within the through hole. An accommodation member accommodates therein a second end of the supporting member located outside the processing chamber, and is partitioned into a first space at a first end side and a second space at a second end side in a moving direction with respect to the second end. A pressure controller generates a pressure difference between the first space and the second space. The pressure difference allows the supporting member to be moved.

Abstract: A substrate support for use in a substrate processing apparatus includes: a base having an internal space; an electronic circuit board disposed in the internal space; a substrate supporting plate disposed on the base; and at least one temperature adjusting element disposed in the internal space, the at least one temperature adjusting element being configured to adjust a temperature of the electronic circuit board.

Abstract: A deadlock determination method includes constructing a new WRG and determining a deadlock. At least a process step that includes a plurality of resources is selected from process steps in a WRG that supports transporting a single piece of material. The plurality of resources corresponding to the selected process step are combined. A total capacity of each of the process steps is changed according to a combination result to construct the new WRG that supports transporting a plurality of pieces of material. The plurality of resources include apparatuses for performing the process steps. The total capacity is a sum of a number of workstations of resources corresponding to each process step. Determining a deadlock includes determining whether a piece of material scheduling deadlock occurs based on the new WRG. The plurality of resources include apparatuses for performing the process steps.

Abstract: Disclosed is a wafer processing system, a dual gate system, and methods for operating these systems. The dual gate system may have a first gate, a second gate, a gate connector coupled to the first gate and to the second gate, and actuator coupled to the gate connector. The actuator is configured to seal the first gate against a first slot or open the first slot via vertical motion. The actuator is also configured to seal the second gate against a second slot or open the second slot via a combination of vertical motion and horizontal motion.

Abstract: According to one aspect of the technique, there is provided a configuration including: a furnace body covering a reaction chamber; a heating element divided into zones and provided in the furnace body; first temperature sensors provided for the zones such that its temperature measuring point is arranged near the heating element; second temperature sensors provided such that its temperature measuring point is provided close to a temperature measuring point of a first temperature sensor; and temperature meters provided at the zones to hold the temperature measuring points of the first and the second temperature sensors to be close to each other in a protection pipe. Each temperature meter penetrates an outer periphery of the furnace body perpendicular to a central axis of the reaction chamber such that a front end of the protection pipe is located outside the reaction tube and on a tube axis thereof.

Abstract: The invention relates to an inspection unit intended for use in devices for transferring electronic components from a first substrate to a second substrate and/or for applying adhesive from a reservoir to the second substrate, comprising an image capturing unit, which is assigned an illumination unit, wherein the illumination unit is designed to direct light of different wavelengths onto a second holder, which in turn is designed to support an object located on the second substrate, which is to be captured by the image capturing unit, wherein a sixteenth, seventeenth, eighteenth and/or nineteenth conveying unit is designed to convey the respective image capturing unit and/or its associated optics, including focusing optics, a beam deflector and/or an illumination unit, along the second holder.

Abstract: A wafer image capturing apparatus, including a loud/unload system, at least one imaging station and a conveying device, are provided. The loud/unload system contains a plurality of wafers. The at least one imaging includes a platform and an image capturing device. The conveying device includes a movable component for moving the wafer to a platform of at least one imaging station. An image capturing device is configured to capture an image of the wafer. A method for image capturing is also provided, including: operating a conveying device to pick a wafer from a load/unload system and move the wafer to at least one imaging station; and operating at least one image capturing device to capture an image from above or below the imaging station. Thus, the flexibility and efficiency of wafer image capturing can be improved.

Abstract: A cutting apparatus includes a table including a support plate transparent in a visible region, a cutting unit, a first feeding mechanism that includes a first moving section for supporting the table and a first motor, a second feeding mechanism that includes a second moving section for supporting the cutting unit and a second motor, a first camera disposed on the side of a first surface of the support plate, a second camera disposed on the side of a second surface opposite to the first surface of the support plate, and a storage section that stores positional deviation amounts in the X-axis direction and the Y-axis direction between an imaging region at a reference position of the first camera and an imaging region at a reference position of the second camera.

Abstract: A substrate processing method according to an embodiment of the present disclosure includes a step of holding a substrate by a substrate holding unit (31) which is rotatable, a step of arranging a top plate portion (41) above the substrate, a step of supplying a processing liquid to the substrate, and a step of supplying a rinsing liquid (Lr) between the substrate and the top plate portion (41) to wash the substrate and the top plate portion (41) with the rinsing liquid (Lr).

Abstract: A load port includes a first pin projecting on a dock plate and provided on the dock plate so as to be pushed down, and a first detection unit provided on the base portion and configured to detect that the dock plate is located at a first position. The first detection unit includes a movable member capable of displacing in a moving direction of the dock plate, and a first sensor configured to detect the displacement of the movable member. The movable member is arranged at a position to abut against the first pin that is in a pushed down state in a process in which the dock plate moves from a second position to the first position.

Abstract: This chip mounting system simultaneously images an alignment mark disposed on a substrate (WT) and an alignment mark disposed on a chip (CP), with the alignment marks disposed on the substrate (WT) and the chip (CP) being separated by a first distance at which the alignment marks fall within a depth-of-field range of imaging devices (35a, 35b). The chip mounting system calculates a relative positional deviation amount between the substrate (WT) and the chip (CP) from the imaged images of the alignment marks imaged by the imaging devices (35a, 35b) and, based on the calculated positional deviation amount, relatively moves the chip (CP) with respect to the substrate (WT) in a direction in which the positional deviation amount therebetween decreases.

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

Abstract: A method and apparatus for biasing regions of a substrate in a plasma-assisted processing chamber are provided. Biasing of the substrate, or regions thereof, increases the potential difference between the substrate and a plasma formed in the processing chamber thereby accelerating ions from the plasma towards the active surfaces of the substrate regions. A plurality of bias electrodes herein are spatially arranged across the substrate support in a pattern that is advantageous for managing uniformity of processing results across the substrate.

Abstract: According to the present invention, a stack comprises, between a carrier substrate and a flexible substrate layer, a peeling power adjustment layer comprising polyimide, which has a refractive index higher than that of the flexible substrate layer, so that a flexible substrate can be more easily peeled from a carrier substrate layer, and thus a flexible element can be manufactured without damage to the element through a simpler process.

Abstract: A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool for contacting the die during a transfer from the die supply source to the substrate; a first motion system for moving the bond head along a first axis; and a second motion system, independent of the first motion system, for moving the bond tool along the first axis.

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

Abstract: In certain embodiments, a method includes forming a first etch stop layer on a first metallization layer of a semiconductor substrate. The method further includes forming, prior to forming a second metallization layer over the first metallization layer, an opening in the first etch stop layer according to a supervia mask. The method further includes forming the second metallization layer over the first metallization layer and forming a second etch stop layer on the second metallization layer. The method further includes forming, prior to forming a third metallization layer over the second metallization layer, an opening in the second etch stop layer according to the supervia mask. The method further includes forming the third metallization layer over the second metallization layer and etching a supervia opening from the third metallization layer to the first metallization layer according to the supervia mask.

Abstract: The present disclosure provides a semiconductor structure, including a transistor. The transistor includes a semiconductive substrate, a gate structure, a pair of highly doped regions and a dielectric element. The semiconductive substrate has a top surface. The gate structure is over the top surface. The pair of highly doped regions is separated by the gate structure. The dielectric element is embedded in the semiconductive substrate. The dielectric element is laterally and vertically misaligned with the pair of highly doped regions.

Abstract: A semiconductor device may include a substrate, a first transistor disposed on the substrate, and a second transistor disposed on the substrate. The first transistor includes a first gate structure. The first gate structure of the first transistor may include a first high-k layer, a first work function layer, an overlying work function layer, and a first capping layer sequentially disposed on the substrate. The second transistor includes a second gate structure. The second gate structure comprises a second gate structure, the second gate structure comprising a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate. The first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer and the overlying work function layer.

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.

Abstract: Methods and architectures for forming metal line plugs that define separations between two metal line ends, and for forming vias that interconnect the metal lines to an underlying contact. The line plugs are present in-plane with the metal lines while vias connecting the lines are in an underlying plane. One lithographic plate or reticle that prints lines at a given pitch (P) may be employed multiple times, for example each time with a pitch halving (P/2), or pitch quartering (P/4) patterning technique, to define both metal line ends and metal line vias. A one-dimensional (1D) grating mask may be employed in conjunction with cross-grating (orthogonal) masking structures that are likewise amenable to pitch splitting techniques.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

Abstract: Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: Integrated chips and methods of forming the same include forming a conductive layer over a lower conductive line. The conductive layer is etched to form a via on the lower conductive line. A first insulating layer is formed around the via. The first insulating layer is etched back to a height below a height of the via. An upper conductive line is formed on the via, making contact with at least a top surface and a side surface of the via.

Abstract: The present disclosure relates to a method of forming an interconnect structure. The method can include providing a semiconductor substrate; depositing a photoresist and a BARC layer on the semiconductor substrate; forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate; depositing a conductive material to fill the opening; and planarizing the conductive material and the semiconductor substrate.

Abstract: A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.