Abstract: An apparatus (2) comprises processing circuitry (4) for performing data processing in response to instructions. The processing circuitry (4) supports a cache maintenance instruction (50) specifying a virtual page address (52) identifying a virtual page of a virtual address space. In response to the cache maintenance instruction, the processing circuitry (4) triggers at least one cache (18, 20, 22) to perform a cache maintenance operation on one or more cache lines for which a physical address of the data stored by the cache line is within a physical page that corresponds to the virtual page identified by the virtual page address provided by the cache maintenance instruction.

Abstract: An approach is provided in which a system includes a GPU cluster. The GPU cluster includes multiple GPU nodes, that each includes a GPU core and a corresponding local cache. The GPU cluster also includes a shared memory and an internal bus that maintains cache coherency between the shared memory and the local caches included in the GPU nodes.

Abstract: A data storage device may include a controller configured to generate an ID based on a name and a version of an application transmitted from a host device together with a logic address, and generate an L2P map list for each application based on the ID; and a nonvolatile memory apparatus including a plurality of map blocks configured to store map data for each ID.

Abstract: An apparatus comprises at least one processing device configured, in conjunction with processing of an input-output (IO) operation by a first storage node of a distributed storage system, where processing of the IO operation requires access to at least one persistent storage device remote from the first storage node but local to a second storage node of the distributed storage system, to send a request from the first storage node to the second storage node identifying data associated with the operation. The processing device determines a buffer of the second storage node that is allocated for use by the second storage node for temporary storage of the data, and utilizes the buffer to provide the data to the second storage node to allow the second storage node to write the data, and/or to obtain the data from the second storage node after the second storage node has read the data.

Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.

Abstract: A method for an in-memory distributed cache includes receiving a write request from a client device to write a block of client data in random access memory (RAM) of a memory host and determining whether to allow the write request by determining whether the client device has permission to write the block of client data at the memory host, determining whether the block of client data is currently saved at the memory host, and determining whether a free block of RAM is available. When the client device has permission to write the block of client data at the memory host, the block of client data is not currently saved at the memory host, and a free block of RAM is available, the write request is allowed and the client is allowed to write the block of client data to the free block of RAM.

Abstract: Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.

Abstract: In a data access method, after an interface card receives a first data write instruction or a first data read instruction, the interface card generates a second data write instruction or a second data read instruction, and writes the second data write instruction or the second data read instruction into a cache. No resource of a processor of a storage device is used. After the interface card writes the second data write instruction or the second data read instruction into the cache, a cache control unit sends the second data write instruction or the second data read instruction to a storage subsystem. No resource of the processor of the storage device is used. Alternatively, the cache control unit may instruct the storage subsystem to execute the second data write instruction or the second data read instruction.

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Abstract: A system may include a processor and a memory, the processor having at least one cache. The cache may include a plurality of sets, each set having a plurality of cache lines. Each cache line may include several bits for storing information, including at least a “shared” bit to indicate whether the cache line is shared between different processes being executed by the processor. The example cache may also include shared cache line detection and eviction logic. During normal operation, the cache logic may monitor for a context switch (i.e., determine if the processor is switching from executing instructions for a first process to executing instructions for a second process). Upon a context switch, the cache logic may evict the shared cache lines (e.g., the cache lines with a shared bit of 1). This eviction of shared cache lines may prevent attackers utilizing such attacks from gleaning meaningful information.

Abstract: Distributed computing system functionality is enhanced. Transmission of data changes may be incremental, thus reducing bandwidth usage and latency. Data changes may be propagated over geographic distances in an outward-only manner from a central data store to one or more servers or other remote nodes, using proactive updates as opposed to making cache updates only in reaction to cache misses. Cache expiration and eviction may be reduced or avoided as mechanisms for determining when cached data is modified. A central computing environment may proactively push incremental data entity changes to place them in remote data stores. Remote nodes proactively check their remote data store, find changes, pull respective selected changes into their remote node caches, and provide current data in response to service requests. Data may be owned by particular tenants. Data pulls may be limited to data in selected categories, data of recently active tenants, or both.

Abstract: Method for managing a cache memory comprising: the transformation of a received set address in order to find a word in the cache memory, into a transformed set address by means of a bijective transformation function, the selection of one or more line tags stored in the cache memory at the transformed set address. in which: the transformation function is parameterized by a parameter q such that the transformed set address obtained depends both on the received set address and on the value of this parameter q, and for all the non-zero values of the parameter q, the transformation function permutes at least 50% of the set addresses, and during the same execution of the process, a new value of the parameter q is repeatedly generated for modifying the transformation function.

Abstract: Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

Abstract: A computational device receives an indication that specifies a maximum retention time in cache for a first plurality of tracks, wherein no maximum retention time is specified for a second plurality of tracks. A plurality of insertions points are generated in a least recently used (LRU) list, wherein different insertion points in the LRU list correspond to different amounts of time that a track of the first plurality of tracks is expected to be retained in the cache, wherein the LRU list is configured to demote both tracks of the first plurality of tracks and the second plurality of tracks from the cache.

Abstract: A computer program product, system, and method for managing adding of accessed tracks in cache to a most recently used end of a cache list. A cache list for the cache has a least recently used (LRU) end and a most recently used (MRU) end. Tracks in the cache are indicated in the cache list. A track in the cache indicated on the cache list is accessed. A determination is made as to whether a track cache residency time since the accessed track was last accessed while in the cache list is within a region of lowest track cache residency times. A flag is set for the accessed track indicating to indicate the track at the MRU end in response to determining that the track cache residency time of the accessed track is within the region of lowest track cache residency times. The accessed track remains at a current position in the cache list before being accessed after setting the flag.

Abstract: An apparatus includes a cache controller circuit and a multi-ported cache memory including a plurality of cache ways. The cache controller circuit is configured to maintain rank values and a threshold value usable to classify the rank values. A given rank value corresponds to a least recently used one of the plurality of cache ways. The cache controller circuit is further configured to receive, in a common access cycle, first and second memory access requests for the cache memory, and, in response to a determination that the first and second memory access requests correspond to respective first and a second cache ways, compare the corresponding rank values for the first and second cache ways to the threshold value. The cache controller circuit is further configured to, based on the comparison, modify the rank value of a selected one of the first and second cache ways.

Abstract: The disclosure relates to a method for processing an application, an electronic device, and a computer-readable storage medium. The method is carried in an electronic device and includes that a plurality of reclaimable memory pages occupied by an application to be processed are determined; data stored in the plurality of reclaimable memory pages is written into an external storage medium; an operation of the application to be processed is paused; and the data written into the external storage medium is written into a memory when the operation of the application to be processed is unpaused.

Abstract: An operation method of a memory system includes: searching for a valid physical address in memory map segments stored in the memory system, based on a read request from a host, a logical address corresponding to the read requests, and a physical address corresponding to the logical address and performing a read operation corresponding to the read request; caching some of the memory map segments in the host as host map segments based on a read count threshold indicating the number of receptions of the read request for the logical address; and adjusting the read count threshold based on a miss count indicating the number of receptions of the read request with no physical address, and a provision count indicating the number of times the memory map segment is cached in the host.

Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

Abstract: Disclosed herein is a technique for managing I/O requests transmitted between a computing device and a storage device. According to some embodiments, the technique can be implemented by the computing device, and include providing at least one I/O request to a submission queue configured to store a plurality of I/O requests. In conjunction with providing the at least one I/O request, the computing device can identify that at least one condition associated with the submission queue—and/or a completion queue—is satisfied, where efficiency gains can be achieved. In turn, the computing device can (1) update an operating mode of the storage device to cause the storage device to cease interrupt issuances to the computing device when I/O requests are completed by the storage device, and (2) update an operating mode of the computing device to cause the computing device to periodically check the completion queue for completed I/O requests.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

Abstract: A method and electronic device for communicating audio signals with an audio input/output device is provided. The electronic device includes a USB type connection port, an audio processor configured to support conversion between a digital signal and an analog signal, and at least one processor configured to detect a connection of a peripheral device via the connection port, identify a type of the peripheral device, establish a first signal path for communicating the digital signal with the peripheral device through a first pin and/or a second pin included in the connection port based on whether the peripheral device supports a first mode, or establish a second signal path for communicating the analog signal with the peripheral device through the first pin and/or the second pin included in the connection port based on whether the peripheral device supports a second mode and whether a predetermined condition is satisfied.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.

Abstract: A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.

Abstract: A computer system includes a first baseboard management controller (BMC) and a first host of the first BMC. The first host operates a first storage service at the first host. The first host is a first storage device connected to one or more storage drives. The first storage service managing a first Remote Direct Memory Access (RDMA) controller for accessing user data stored on the one or more storage drives through a storage network. The first BMC receives state information of the one or more storage drives. The first BMC sends notifications to a client of the first BMC, in response to receiving the state information.

Abstract: A method for arbitrating data transfer requests from a plurality of nodes includes specifying one or more nodes among the plurality of nodes, the one or more nodes satisfying a predetermined condition, and selecting, if two or more nodes are specified among the plurality of nodes, one node from the two or more nodes using priority information, the priority information indicating correspondence between the plurality of nodes and a plurality of priorities each assigned to one of the plurality of nodes, the correspondence changing so that the plurality of priorities are assigned equally to each of the plurality of nodes and high and low relations appear equally between pairs of priorities each assigned to a pair of nodes of the plurality of nodes.

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.

Abstract: An interface control circuit includes an interface wrapper, a logic circuit, a multiplexer and a command decoder. The interface wrapper transceives a plurality of first signals in a first interface, converts the first signals to a plurality of second signals in a second interface, and generates at least one first command signal according to the first signals. The logic circuit receives the second signals, and generates a second command signal according to the second signals. The multiplexer receives the first command signal and the second command signal, and generates a third command signal according to the first command signal and the second command signal. The command decoder receives the third command signal and generates the decoded command according to the third command signal.

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Abstract: Composite interface circuit including bidirectional single-conductor bus, first switching circuit, and second switching circuit. Bidirectional single-conductor bus is coupled by first pull-up resistor (R1) with first direct current (“DC”) input current source having first voltage (V1). First switching circuit includes first transistor (T1) being coupled with first pull-up resistor (R1) and with bidirectional single-conductor bus. Second switching circuit includes second transistor (T2) being coupled by second pull-up resistor (R2) with second DC input current source having second voltage (V2). Second switching circuit further includes voltage divider coupling second transistor (T2) with bidirectional single-conductor bus. First and second switching circuits are respectfully configured for being coupled with first transmitter conductor (Tx1) and first receiver conductor (Rx1) of full duplex universal asynchronous data communication interface.

Abstract: A method is provided for remote control. Peripheral component interconnect express (PCI-E) is used for controlling with universal serial bus (USB) type-C (USB-C). A controlling terminal inputs a control signal of switching through a user interface. The controlling terminal transfers the control signal to a PCI-E connector of an image capture unit through a first port. After being handled and transformed by a processing device, the control signal is transferred with a USB-C connector of the image capture unit to at least one controlled terminal through a second port. Thus, the image capture unit is expanded in function to obtain keyboard-video-mouse switch (KVM Switch) among the category of image capturing cards. In summary, with a remote connection, a controlling terminal remotely controls a controlled terminal while simple flow, enhanced speed, and effective cost-down are achieved.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: A device that may configure itself is disclosed. The device may include an interface that may be used for communications with a chassis. The interface may support a plurality of transport protocols. The device may include a Vital Product Data (VPD) reading logic to read a VPD from the chassis and a built-in self-configuration logic to configure the interface to use one of the transport protocols and to disable alternative transport protocols, responsive to the VPD.

Abstract: A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of ALUs in a data path is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first selecting a first available instruction node from the dependency graph; first assigning the selected first available instruction node to the instruction word; second selecting any available dependent instruction nodes that are dependent upon a result of the selected first available instruction node and do not violate any predetermined rule; second assigning to the instruction word the selected any available dependent instruction nodes; and updating the dependency graph to remove any instruction nodes assigned during the first and second assigning from further consideration for assignment.

Abstract: Techniques are provided for managing objects within an object store. An object is maintained within an object store. The object comprises a plurality of slots. Each slot is used to store a unit of data accessible to applications hosted by remote computing devices. The object comprises an object header used to store metadata for each slot. A determination is made that the object is a fragmented object comprising an in-use slot of in-use data and a freed slot from which data was freed. The object is compacted to retain in-use data and exclude freed data as a rewritten object.

Abstract: A system and method logs update queries by epoch, including at checkpoints performed at various times.

Abstract: The embodiments relate to assigning data to processors of a file system. Metadata associated with respective blocks of data, and an initial batch of the blocks is assigned to nodes of a file system based on the metadata. Unassigned blocks are selectively assigned to one or more of the nodes. The selective assignment includes constructing a linear regression model based on node data, and determining a value for each node based on the linear regression model. Each value is associated with a predicted load corresponding to a new assignment of one or more unassigned blocks.

Abstract: Files can be located using a durable and universal file identifier. A content URI includes a file protocol URI specifying a path to a file. The file protocol URI includes a query string specifying properties of the file that can be utilized to locate the file, such as an object ID property specifying a GUID for the file and a volume ID property specifying a GUID for a storage volume storing the file. The content URI can be utilized to locate the file using the file protocol URI and its associated query string even if the file has been moved, renamed, or is accessed on a different computing device. Operations can then be performed using the file, such as resuming a previously performed activity that used the file.

Abstract: Techniques are provided for an object file system for an object store. Data, maintained by a computing device, is stored into slots of an object. The data within the slots of the object is represented as a data structure comprising a plurality of nodes comprising cloud block numbers used to identify the object and particular slots of the object. A mapping metafile is maintained to map block numbers used to store the data by the computing device to cloud block numbers of nodes representing portion of the data stored within slots of the object. The object is stored into the object store, and the mapping metafile and the data structure are used to provide access through the object file system to portions of data within the object.

Abstract: Techniques are provided for an object file system for an object store. Data, maintained by a computing device, is stored into slots of an object. The data within the slots of the object is represented as a data structure comprising a plurality of nodes comprising cloud block numbers used to identify the object and particular slots of the object. A mapping metafile is maintained to map block numbers used to store the data by the computing device to cloud block numbers of nodes representing portion of the data stored within slots of the object. The object is stored into the object store, and the mapping metafile and the data structure are used to provide access through the object file system to portions of data within the object.

Abstract: Techniques to eliminate redundant file system operations are disclosed. In various embodiments, an indication is received to send locally-stored file system operations to a remote file system metadata server. A set of related locally-stored file system operations is determined. Operations in the set are determined to satisfy a merger criteria and are merged into a single merged file system operation. The merged file system operation is sent to the remote file system metadata server.

Abstract: Methods, systems, and computer storage media for providing reduced-latency data operations in a file system. In operation, a request to perform a data operation associated with a B+ table storage of a file system is received. The file system supports the B+ table storage that is accessible using a B+ tree lookup logic for accessing B+ table data and supports a cache storage that is accessible using a cache table lookup logic for accessing cache data in the cache storage. A number of references to the location in the B+ table storage is determined. The location in the B+ table storage is associated with the request to perform the data operation. Based on determining the number of references to the location, a cache storage location to perform the data operation is accessed. The cache storage location is mapped (using the cache table) to the location in the B+ table storage.

Abstract: Techniques are provided for compression of log data using field types. An exemplary method comprises: obtaining at least one log message, wherein the at least one log message comprises a message template and at least one message variable, wherein the message template comprises at least one field corresponding to the at least one message variable; obtaining a compression index that maps a plurality of message templates to a corresponding message signature; identifying a predefined field type of the at least one field; selecting a compression technique to apply to the at least one message variable based on the predefined field type to obtain a compressed message variable; and writing the compressed message variable and a message signature corresponding to the message template of the at least one log message to a log file. The at least one log message can be a historical log message or part of a real-time stream of log messages.

Abstract: Techniques for balancing data compression and read performance of data chunks of a storage system are described herein. According to one embodiment, similar data chunks are identified based on sketches of a plurality of data chunks stored in the storage system. A first portion of the similar data chunks as a first group is associated with a first storage area. The first storage area is associated with one or more data chunks that are dissimilar to the first group but are likely accessed together. The first group of the similar data chunks and its associated dissimilar data chunks are compressed and stored in the first storage area.