Abstract: An etching protection layer structure of a metal semiconductor junction includes a semiconductor substrate and a metal etching protection layer. The semiconductor substrate has a metal semiconductor contact layer. The metal etching protection layer is disposed on the metal semiconductor contact layer, and serves as an etching mask for the ridge structure of laser device during the inductively coupled plasma reactive ion etching (ICP-RIE) process. The disclosure is not necessary to remove the metal etching protection layer after completing the etching process.

Abstract: A process for manufacturing a silicon carbide semiconductor device includes providing a silicon carbide wafer, having a substrate. An epitaxial growth for formation of an epitaxial layer, having a top surface, is carried out on the substrate. Following upon the step of carrying out an epitaxial growth, the process includes the step of removing a surface portion of the epitaxial layer starting from the top surface so as to remove surface damages present at the top surface as a result of propagation of dislocations from the substrate during the previous epitaxial growth and so as to define a resulting top surface substantially free of defects.

Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

Abstract: A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer. Each of the first and second superlattices may include stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The second superlattice may have a greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate toward the at least one non-semiconductor monolayer of the second superlattice.

Abstract: A dry-state non-contact method for patterning of nanostructured conducting materials is disclosed. Short self-generated electron-emission pulses in air at atmospheric pressure can enable an electron-emission-based (field enhancement) interaction between a sharp tungsten tip and elements of the nanostructured materials to cause largely non-oxidative sequential decomposition of the nanostructured elements. Embodiments can employ a substrate/tip gap of 10 to 20 nm, discharge voltages of 25-30 V, and patterning speeds as fast as 10 cm/s to provide precisely patterned nanostructures (<200 nm) that are largely free of foreign contaminants, thermal impact and sub-surface structural changes.

Abstract: A method comprises producing a base plate, wherein producing the base plate comprises forming a layer of a metallic material, and forming at least one first area in the layer of metallic material, wherein forming the at least one first area either comprises locally deforming the layer of metallic material, or locally inducing stress into the layer of metallic material, or both such that a deflection or a local stress or both in the at least one first area differs from a deflection or a local stress or both of those areas of the metallic layer surrounding the at least one first area.

Abstract: A controller of a substrate processing apparatus causes execution of: a cleaning process of cleaning at least a bottom surface of a cover by a cleaning liquid that fills a space between a top surface of a substrate and the bottom surface of the cover by supplying, in a state in which a vertical distance between the top surface of a substrate (a cleaning substrate) held by a substrate holder and the bottom surface of the cover is set to a first distance, the cleaning liquid to the top surface of the substrate while rotating the substrate; and after the cleaning process, a drying process of drying at least the bottom surface of the cover by stopping, in a state in which the vertical distance is set to a second distance greater than the first distance, the supply of the cleaning liquid while rotating the substrate.

Abstract: A wafer cleaning apparatus for cleaning a circumferential edge of a wafer includes a cleaning unit that jets high-pressure water toward the circumferential edge of the wafer from an outer side than the circumferential edge of the wafer held by a holding surface of a holding table, to clean the circumferential edge of the wafer. The cleaning unit includes a first nozzle that jets the high-pressure water to the circumferential edge of the wafer from an outer side than the circumferential edge of the wafer in a direction parallel to the holding surface, a second nozzle that jets the high-pressure water to the circumferential edge of the wafer in a direction of 45 degrees downward relative to the holding surface, and a third nozzle that jets the high-pressure water to the circumferential edge of the wafer in a direction of 45 degrees upward relative to the holding surface.

Abstract: A system for fabricating a semiconductor device structure includes a tool comprising a chamber and a platform within the chamber configured to receive a semiconductor device structure thereon. The tool further includes a heating and cooling system in operable communication with the platform and configured to control a temperature of the platform.

Abstract: Described herein is a technique capable of preventing a constituent contained in an aluminum alloy from being vaporized and scattered when the aluminum alloy is used in a process vessel which is heated to a high temperature.

Abstract: A method includes receiving a plurality of sets of sensor data associated with a processing chamber of a substrate processing system. Each of the plurality of sets of sensor data comprises a corresponding sensor value of the processing chamber mapped to a corresponding spacing value of the processing chamber. The method further includes providing the plurality of sets of sensor data as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of a health of the processing chamber. The method further includes causing, based on the one or more outputs, performance of one or more corrective actions associated with the processing chamber.

Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.

Abstract: Provided are a diffraction-based metrology apparatus having high measurement sensitivity, a diffraction-based metrology method capable of accurately performing measurement on a semiconductor device, and a method of manufacturing a semiconductor device using the metrology method. The diffraction-based metrology apparatus includes a light source that outputs a light beam, a stage on which an object is placed, a reflective optical element that irradiates the light beam onto the object through reflection, such that the light beam is incident on the object at an inclination angle, the inclination angle being an acute angle, a detector that detects a diffracted light beam that is based on the light beam reflected and diffracted by the object and a processor that measures a 3D pupil matrix for the diffracted light beam and analyze the object based on the 3D pupil matrix.

Abstract: To provide an automated apparatus for conveying a rectangular substrate. According to one embodiment, there is provided a substrate conveying apparatus for conveying the rectangular substrate. The substrate conveying apparatus includes a plurality of conveyance rollers, a plurality of roller shafts, a motor, and a pusher. The plurality of conveyance rollers are configured to support a lower surface of the substrate. To the plurality of roller shafts, the plurality of conveyance rollers are mounted. The motor is configured to rotate the plurality of roller shafts. The pusher is for lifting the substrate on the plurality of conveyance rollers such that the substrate is separated away from the plurality of conveyance rollers. The pusher includes a stage configured to pass through a clearance between the plurality of roller shafts.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate retainer in a reaction chamber, wherein the substrate retainer is provided with a plurality of slots capable of accommodating a plurality of substrates in a multistage manner; (b) repeatedly performing a set including: (b-1) moving the substrate retainer so as to locate one or more of the slots outside the reaction chamber; and (b-2) charging one or more of the substrates into the one or more of the slots; and (c) moving the substrate retainer such that the plurality of substrates charged in the plurality of slots are accommodated in the reaction chamber.

Abstract: The present disclosure is directed to a wafer container including: a housing configured for transporting a plurality of wafers, wherein the plurality of wafers are stacked on a base of the housing in a first direction; a plurality of wafer separator rings; each of the wafer separator rings configured to encircle a wafer of the plurality of wafers in a second direction that is substantially perpendicular to the first direction, each of the wafer separator rings including a top surface and a bottom surface, defining a thickness there between extending in the first direction, which is about 0.3 mm-1.4 mm; and each of the wafer separator rings including an inner side wall and an outer side wall defined by an inner diameter and an outer diameter, respectively, in the second direction, wherein the inner diameter of the wafer separator ring is greater than 300 mm and configured to be spaced apart from the wafer it is encircling.

Abstract: An apparatus for aligning dipoles is provided. The apparatus includes: an electric field forming unit including a stage and a probe unit, the probe unit being configured to form an electric field on the stage; an inkjet printing device including an inkjet head, the inkjet head being configured to spray ink including a solvent and dipoles dispersed in the solvent onto the stage; a light irradiation device configured to irradiate light onto the stage; and a temperature control device including a temperature control unit, the temperature control unit being configured to control a temperature of the solvent sprayed on the stage.

Abstract: The present invention comprises an arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a first or a second donor chuck respectively; monitoring the solder ball and chip arrangement by a computer-controlled camera; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, the monitored by a second computer controlled camera; flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate, monitored and positionally controlled by a third computer-controlled camera; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-contro

Abstract: A method of aligning a wafer includes defining a reference direction for aligning the wafer; capturing an image of the wafer held on a chuck; using an identifying module to analyze a straight line on the image of the wafer; calculating an offset angle between the straight line and the reference direction; and calibrating the offset angle to align the straight line with the reference direction by way rotating the chuck.

Abstract: A heater for a semiconductor manufacturing apparatus, the heater includes an AlN ceramic substrate and a heating element embedded inside the AlN ceramic substrate. The AlN ceramic substrate contains O, C, Ti, Ca, and Y as impurity elements, includes an yttrium aluminate phase as a crystal phase, and has a Ti/Ca mass ratio of 0.13 or more, and a TiN phase is not detected in an XRD profile measured with Cu K-? radiation.

Abstract: Embodiments of the disclosure provide electrostatic chucks for securing substrates during processing. Some embodiments of this disclosure provide methods and apparatus for increased temperature control across the radial profile of the substrate. Some embodiments of the disclosure provide methods and apparatus for providing control of hydrogen concentration in processed films during a high-density plasma (HDP) process.

Abstract: A method for taping a wafer is disclosed. A wafer taping device comprising a wafer stage is provided. A wafer is mounted and secured on the wafer stage. A tape is delivered along a first direction over the wafer. The tape is forced into adhesion with a surface of the wafer in a non-contact manner. The tape is cut along a perimeter of the wafer.

Abstract: A processing apparatus includes a chuck table mechanism including a chuck table configured to hold the wafer and a table base configured to support the chuck table in a detachable manner. The chuck table includes a porous plate having a suction surface that sucks the wafer, a frame body surrounding surfaces of the porous plate other than the suction surface of the porous plate, a wafer suction hole formed in the frame body and configured to transmit a suction force to the suction surface of the porous plate, and a bolt hole formed in the frame body and configured to fix the frame body to the table base.

Abstract: Electronic device manufacturing systems, robot apparatus and associated methods are described. The robot apparatus includes an arm having an inboard end and an outboard end, the inboard end is configured to rotate about a shoulder axis; a first forearm is configured for independent rotation relative to the arm about an elbow axis at the outboard end of the arm; a first wrist member is configured for independent rotation relative the first forearm about a first wrist axis at a distal end of the first forearm opposite the elbow axis, wherein the first wrist member includes a first end effector and a second end effector. The robot apparatus further includes a second forearm configured for independent rotation relative to the arm about the elbow axis; a second wrist member configured for independent rotation relative the second forearm about a second wrist axis, wherein the second wrist member comprises a third end effector and a fourth end effector.

Abstract: A temperature control device includes: a top plate that supports a substrate; a base plate connected to the top plate so as to form an internal space with the top plate; a thermoelectric module plate arranged in the internal space; a heat exchange plate that is arranged in the internal space and exchanges heat with the thermoelectric module plate; and a sealing member that comes into contact with each of the top plate and the base plate.

Abstract: Disclosed are a wafer susceptor and a chemical vapor deposition apparatus, which solve a problem of a decrease in yield due to uneven wavelength of deposited epitaxial material caused by uneven heating during a wafer manufacturing process. The wafer susceptor includes: a wafer carrying groove; and two convex structures disposed at the bottom of the wafer carrying groove.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Abstract: A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: Embodiments of the invention include semiconductor devices having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The devices further include a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.

Abstract: A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate.

Abstract: An inspecting device includes a stage configured to support a wafer in which a plurality of rows of modified regions are formed in a semiconductor substrate, a light source configured to output light, an objective lens configured to pass light propagated through the semiconductor substrate, a light detection part configured to detect light passing through the objective lens, and an inspection part configured to inspect whether or not there is a tip of a fracture in an inspection region between a front surface and the modified region closest to the front surface of the semiconductor substrate. The objective lens positions a virtual focus symmetrical with a focus with respect to the front surface in the inspection region. The light detection part detects light propagating from the back surface side of the semiconductor substrate to the back surface side via the front surface.

Abstract: According to one aspect of the present disclosure, there is provided a technique that includes: a substrate retainer; a reaction tube; a heater configured to heat an inside of the reaction tube; a gas supplier configured to supply a process gas to substrates accommodated in the reaction tube; an exhauster configured to exhaust the process gas from the inside of the reaction tube; a temperature detector configured to measure an inner temperature of the reaction tube; a reflectance detector configured to measure a reflectance of a film formed by supplying the process gas through the gas supplier; and a controller configured to be capable of performing a feedback control of film-forming conditions on the substrates accommodated in the reaction tube by using temperature information measured by the temperature detector and reflectance information measured by the reflectance detector.

Abstract: A method of controlling plasma includes providing a plasma processing apparatus that includes N microwave introducing radiators disposed in a circumferential direction of a ceiling plate of a processing container so as to introduce microwaves for generating plasma into the processing container, wherein N?2; and M sensors and configured to monitor at least one of electron density Ne and electron temperature Te of the plasma generated in the processing container, wherein M equals to N or a multiple of N. The method further includes controlling at least one of a power and a phase of the microwaves introduced from the microwave introducing radiators based on at least one of electron density Ne and electron temperature Te of the plasma monitored by the M sensors.

Abstract: A substrate processing system includes a processing chamber, a substrate support, a heat source, a gas delivery system and a controller. The substrate support is disposed in the processing chamber and supports a substrate. The heat source heats the substrate. The gas delivery system supplies a process gas to the processing chamber. The controller controls the gas delivery system and the heat source to iteratively perform an isotropic atomic layer etch process including: during an iteration of the isotropic atomic layer etch process, performing pretreatment, atomistic adsorption, and pulsed thermal annealing; during the atomistic adsorption, exposing a surface of the substrate to the process gas including a halogen species that is selectively adsorbed onto an exposed material of the substrate to form a modified material; and during the pulsed thermal annealing, pulsing the heat source multiple times within a predetermined period to expose and remove the modified material.

Abstract: A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body.

Abstract: A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Abstract: A semiconductor module includes a first heat sink member, a semiconductor device, a second heat sink member, a lead frame, a second sealing member. The semiconductor device includes a semiconductor element, a first sealing member for covering the semiconductor element, a first wiring and a second wiring electrically connected to the semiconductor element, and a rewiring layer on the semiconductor element and the sealing member. The second heat sink member is disposed on the semiconductor device. The lead frame is electrically connected to the semiconductor device through a bonding member. The second sealing member covers a portion of the first heat sink member, the semiconductor and a portion of the second heat sink member. A surface of the second heat sink member faces the semiconductor device. The semiconductor device has a portion protruded from an outline of the second surface sink member.

Abstract: A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.

Abstract: An element module includes an element, a plurality of conductive members, and a spacer member. The plurality of conductive members are connected to the element and arranged in a predetermined direction. The spacer member is disposed between two conductive members of the plurality of conductive members adjacent to each other in the predetermined direction and is in contact with parts of the two conductive members.

Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.

Abstract: A method for manufacturing a semiconductor device includes a process of providing two source electrodes on a substrate, a process of providing a gate electrode on one surface of the substrate between the two source electrodes, a process of providing an insulating film on the gate electrode, the substrate, and side surfaces of the two source electrodes, a process of providing an airbridge foundation resist on the insulating film, providing an airbridge on the two source electrodes and the airbridge foundation resist, and a process of removing the airbridge foundation resist, in which surfaces of the two source electrodes at sides opposite to the substrate and a front surface of the airbridge foundation resist provided in the subsequent process are substantially coplanar.

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Abstract: In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator.