Abstract: A method of manufacturing a device chip includes applying, from a front surface of a wafer formed with devices in a plurality of regions partitioned by a plurality of crossing division lines, a laser beam of such a wavelength as to be absorbed in the wafer along the division lines, to form V-shaped laser processed grooves along the division lines, the laser processed grooves becoming shallower toward outer sides in a width direction; adhering an adhesive tape to the front surface of the wafer formed with the laser processed grooves; and grinding the wafer held by a chuck table, with the adhesive tape interposed therebetween, from a back surface, to divide the wafer while thinning the wafer to a finished thickness, thereby forming a plurality of device chips having inclined surfaces at outside surfaces thereof.

Abstract: A method of batch massively parallel die release of a die from a substrate enabling low cost mass production of with passive, system in package (SiP) or system-in-a-package, or systems-on-chip (SoC), filters and/or other devices from a glass substrate.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The semiconductor device includes a plurality of fin-shaped active regions spaced apart from each other in the device region and extending in a first direction. The semiconductor device includes a protruding pattern extending along a bottom surface of the trench. Moreover, an interval between the protruding pattern and the plurality of fin-shaped active regions is greater than an interval between two adjacent ones of the plurality of fin-shaped active regions.

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.

Abstract: A method for forming fins of Fin FETs is provided. A patterning process on the second sidewalls forms a type-one second sidewalls and a type-two second sidewalls, the type-one second sidewalls are arranged next to each other and sandwiched between a pair of type-two second sidewalls on one side and another pair of type-two second sidewalls on another side, followed by an etching to remove the pairs of the type-two second sidewalls from both sides of the type-one second sidewall. The type-two second sidewalls adjacent to the two sides of the type-one second sidewalls are not pattern-transferred to a to-be-patterned layer, after the fin patterns on the to-be-patterned layer are formed, patterns corresponding to the type-two second sidewalls are etched away through a rough removal process.

Abstract: A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer.

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

Abstract: A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. First gate insulator material is formed along opposing sidewalls of the channel region in the vertical cross-section. One of (a) or (b) is formed over opposing sidewalls of the first gate insulator material in the vertical cross-section, where (a): conductive gate lines that are horizontally elongated through the vertical cross-section; and (b): sacrificial placeholder gate lines that are horizontally elongated through the vertical cross-section. The one of the (a) or the (b) laterally overlaps the upper source/drain region and the lower source/drain region.

Abstract: A TMR element includes a magnetic tunnel junction, a side wall portion that covers a side surface of the magnetic tunnel junction, and a minute particle region that is disposed in the side wall portion. The side wall portion includes an insulation material. The minute particle region includes the insulation material and a plurality of minute magnetic metal particles that are dispersed in the insulation material. The minute particle region is electrically connected in parallel with the magnetic tunnel junction.

Abstract: A method includes preparing an electronic component that includes an element plate including an element region provided with a functional element and a peripheral region disposed around the element region, a counter plate facing the element region and the peripheral region, a first resin member disposed between at least one of the element region and the peripheral region and the counter plate, and a second resin member disposed between the peripheral region and the counter plate, applying light to the element plate through the counter plate and the second resin member, and measuring a gap between the counter plate and the element plate based on light reflected between the element plate and the second resin member and light reflected between the counter plate and the second resin member.

Abstract: A sensor device includes: a first sensor element; a second sensor element; and a processing chip that includes a semiconductor substrate, a first processor that receives a first detection signal and processes the first detection signal, a second processor that receives the second detection signal and processes the second detection signal, and an isolation portion that electrically isolates the first processor the second processor. The first processor includes a first diagnosis unit that self-diagnoses a presence or absence of a failure. The second processor includes a second diagnosis unit that self-diagnoses a presence or absence of a failure. The processing chip identifiably outputs a first output of the first processor and a second output of the second processor.

Abstract: A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Abstract: A semiconductor package includes a semiconductor chip having chip pads on a first surface and having first and second side surfaces opposite to each other and third and fourth side surfaces opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings.

Abstract: The present disclosure provides thermal interface materials that are useful in transferring heat from heat generating electronic devices, such as computer chips, to heat dissipating structures, such as heat spreaders and heat sinks. The thermal interface material is soft and has elastic properties post-curing along with high thermally conductive filler loading. The thermal interface material includes at least one long chain alkyl silicone oil; at least one long chain, vinyl terminated alkyl silicone oil; at least one long chain, single end hydroxyl terminated silicone oil; at least one thermally conductive filler, at least one coupling agent, at least one catalyst, at least one crosslinker, and at least one addition inhibitor.

Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.

Abstract: A heat sink including a metal-formed body having a base board part and two or more fin parts standing on a surface of the base board part and arranged in a parallel manner to each other, and one or more filled bodies consisting of a plurality of coiled metal-wire materials filled in one or more groove parts formed between the fin parts of the metal-formed body; the heat sink in which the coiled metal-wire materials have a first outer diameter at one end part and a second outer diameter at the other end part which is different from the first outer diameter; and the coiled metal-wire materials are metallurgically joined at partially to at least one of an inner surface of the groove parts of the metal-formed body and the other coiled metal-wire materials.

Abstract: Disclosed is a power module capable of maximizing heat dissipation performance through application of a thick lead frame and a ceramic coating layer to upper and lower sides of a semiconductor device.

Abstract: A silver-indium transient liquid phase method of bonding a semiconductor device and a heat-spreading mount, and a semiconductor structure having a silver-indium transient liquid phase bonding joint are provided. With the ultra-thin silver-indium transient liquid phase bonding joint formed between the semiconductor device and the heat-spreading mount, its thermal resistance can be minimized to achieve a high thermal conductivity. Therefore, the heat spreading capability of the heat-spreading mount can be fully realized, leading to an optimal performance of the high power electronics and photonics devices.

Abstract: The load force bolster assembly includes a metallic stiffener. A carrier associated with a CPU (Central Processing Unit) is located upon the load force bolster assembly and positioned upon the electrical connector. A heat sink is located upon both the carrier and the load force bolster assembly wherein a torsioned wire of the bolster assembly provides a downward force upon an up-and-down movable stud which is secured to a screw of the heat sink so as to downwardly push the heat sink, thus enhancing the normal forces among the heat sink, the CPU and the contacts of the electrical connector. To efficiently hold the torsioned wire in position around a bottom corner of the stiffener, a retention groove is formed around the top portion of the restricting pole, and a pressing ring is downwardly snapped into the retention groove so as to restrain the torsioned wire in position.

Abstract: A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.

Abstract: A power assembly that has at least two power modules that each have at least one component to be cooled, for example, an electronic chip mounted on a base from which cooling elements extend. Each power module also has a hollow body with a channel for flow of a coolant fluid Each power module is mounted on each respective body so that the cooling elements extend at least partially into said channel through an opening of the body. At least one deflector is mounted in the channel between the cooling elements of the two modules so as to force the coolant fluid to flow in the zone of the channel comprising the cooling elements.

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

Abstract: The disclosure describes a lid allowing for a liquid thermal interface material (TIM) in a lidded flip chip package. The lid includes a reservoir structure so that a liquid system can be formed in the lidded flip chip package, allowing for a liquid TIM in the gap between the lid and the flip chip. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a tunnel for taking in a liquid material and releasing it again from and to the gap according to the change of the gap volume. The lid further includes an injection hole and a plug for filling and removing liquid into or from the gap and reservoir. The lid further includes a plurality of pins, which extrude downwards from the bottom surface of the lid so as to strongly bond with the substrate of the flip chip package through an adhesive.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

Abstract: Provided is a Pd coated Cu bonding wire for a semiconductor device capable of sufficiently obtaining bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases. The bonding wire for a semiconductor device comprises a Cu alloy core material; and a Pd coating layer formed on a surface of the Cu alloy core material; and contains 0.03 to 2% by mass in total of one or more elements selected from Ni, Rh, Ir and Pd in the bonding wire and further 0.002 to 3% by mass in total of one or more elements selected from Li, Sb, Fe, Cr, Co, Zn, Ca, Mg, Pt, Sc and Y. The bonding wire can be sufficiently obtained bonding reliability of a ball bonded portion in a high temperature environment of 175° C. or more, even when the content of sulfur in the mold resin used in the semiconductor device package increases by being used.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has amounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

Abstract: A flat no-leads package, the flat no-leads package includes a leadframe for electrically connecting an integrated circuit (IC) chip which in a mounted configuration is arranged in a center portion of the flat no-leads package. The leadframe has at least one RF lead pin; and an isolating encapsulation which is at least partially encapsulating the leadframe such that contact surfaces of the leadframe are electrically contactable at least from a bottom side of the flat no-leads package; wherein at least one of the RF lead pin has a first and second contact surfaces. A cross-section of the RF lead pin increases from the first contact surface to the second contact surface both in a horizontal direction and in a direction vertical thereto. Further, a printed circuit board having a flat no-leads package and a measurement device having a flat no-leads package are provided.

Abstract: A semiconductor device according to an embodiment comprises a semiconductor element, a first terminal, a plurality of second terminals, and an encloser. The semiconductor element is rectangular. The first terminal has an upper surface to which a back surface of the semiconductor element is bonded. The second terminals are arranged around the first terminal. The second terminals are arranged at four corners of the encloser to be exposed from the bottom surface, and sides of the semiconductor element are opposed to the first side, the second side, the third side, and the fourth side, respectively. The first terminal is apart from the first side surface and the third side surface, a lower surface of the first terminal is exposed from the bottom surface, and the first terminal is partly exposed from the second side surface and the fourth side surface.

Abstract: A structure of a substrate is provided for application in an electric power module. The substrate includes element regions, on which a plurality of semiconductor elements are arranged, a center region that defines a space among the element regions, an input terminal region, on which an input terminal for applying an electric current to the substrate is disposed, and one or more slit insulation portions that are defined to face toward sides, respectively, of the element regions adjacent to the input terminal region, which are among the element regions. The slit insulation portions extend toward the center region in such a manner that an electric current applied through the input terminal region flows into the center region.

Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

Abstract: A semiconductor device includes a semiconductor chip, first and second source terminals and a Kelvin terminal, wherein the semiconductor chip includes a first source electrode coupled to the first source terminal through a first connecting portion, a second source electrode coupled to the second source terminal through a second connecting portion, a Kelvin pad coupled to the Kelvin terminal and formed independently of the first source electrode, a power MOSFET that has a source coupled to the first source electrode, a sense MOSFET that has a source coupled to the second source electrode, a source pad formed on a portion of the first source electrode and coupled to the first connecting portion, a plurality of source potential extraction ports formed around a connection point between the first connecting portion and the source pad and a plurality of wires coupled between the source potential extraction ports and the Kelvin pad.

Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Abstract: A flip-chip film includes a substrate and a plurality of flip-chip film units. The plurality of flip-chip film units are disposed on the substrate, and each of the flip-chip film units includes a plurality of first metal traces arranged at intervals. A punch cut is defined between the first metal traces of two adjacent flip-chip film units.

Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

Abstract: An electronic device includes a substrate, a first conductive pad and a chip. The first conductive pad is disposed on the substrate. The chip includes a second conductive pad electrically connected to the first conductive pad, and the first conductive pad is disposed between the substrate and the second conductive pad. The first conductive pad has a first groove.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first portion includes forming a first patterned conductive pad with a first through hole on a first interconnect structure over a first semiconductor substrate; patterning a dielectric material over the first interconnect structure to form a first patterned dielectric layer with a first opening that passes through a portion of the dielectric material formed inside the first through hole to accessibly expose the first interconnect structure; and forming a conductive material inside the first opening and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer. A singulation process is performed to cut off the first patterned dielectric layer, the first interconnect structure, and the first semiconductor substrate to form a continuous sidewall of a semiconductor structure.

Abstract: A semiconductor package includes a redistribution layer, a semiconductor chip on the redistribution layer, and a molding layer covering a sidewall of the semiconductor chip and a top surface and a sidewall of the redistribution layer. The sidewall of the redistribution layer is inclined with respect to a bottom surface of the redistribution layer, and a sidewall of the molding layer is spaced apart from the sidewall of the redistribution layer.

Abstract: A semiconductor package includes a core substrate having a through hole, a first molding member at least partially filling the through hole and covering an upper surface of the core substrate, the first molding member having a cavity within the through hole, a first semiconductor chip on the first molding member on the upper surface of the core substrate, a second semiconductor chip arranged within the cavity, a second molding member on the first molding member and covering the first semiconductor chip, a third molding member filling the cavity and covering the lower surface of the core substrate; first redistribution wirings on the second molding member and electrically connecting first chip pads of the first semiconductor chip and core connection wirings of the core substrate; and second redistribution wirings on the third molding member and electrically connecting second chip pads of the second semiconductor chip and the core connection wirings.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.