Abstract: A method for providing analysis data of a dynamic website is a method for providing analysis data, the method including the steps of: receiving visitor behavior analysis data of a dynamic webpage; identifying, from the dynamic webpage, an effective area corresponding to an effective element; acquiring, from the analysis data, event counter data corresponding to the effective area; on the basis of the event counter data, generating a heatmap representing analysis results of user behavior on the dynamic webpage; and synchronizing the generated heatmap onto the dynamic webpage, and outputting same.

Abstract: Example embodiments describe a method performed by one or more processors. The method may comprise sending over a network, to a software component installed at a remote data source, a request to download data stored at, or in association with, the remote data source, the software component being configured to access performance data at said remote data source. In response to sending the request, the method may comprise receiving from the software component at least an indication of the performance data accessed by said software component, determining whether to proceed with the data download request or to modify the data download request based on the received performance data.

Abstract: Techniques described herein relate to a method for deploying workflows. The method may include receiving, by a global orchestrator of a device ecosystem, a request to execute a workflow; decomposing, by the global orchestrator, the workflow into a plurality of workflow portions; executing, by the global orchestrator, a metaheuristic algorithm to generate a result comprising a plurality of domains of the device ecosystem in which to execute the plurality of workflow portions; and providing, by the global orchestrator, the plurality of workflow portions to respective local orchestrators of the plurality of domains based on the result of executing the metaheuristic algorithm.

Abstract: An apparatus comprises a processing device configured to initiate, in response to a designated event, monitoring of memory allocation and de-allocation operations associated with a given application, to maintain a memory allocation operation data structure comprising entries each corresponding to a memory allocation operation not having an associated memory de-allocation operation, and to determine whether memory usage of the given application corresponds to any of a set of anomalous memory usage pattern rules based on the memory allocation operation data structure. The processing device is also configured to identify the given application as being a cause of a memory leak responsive to determining that the memory usage of the given application corresponds to one or more of the anomalous memory usage pattern rules, and to perform remedial action for preventing or resolving the memory leak responsive to identifying the given application as being the cause of the memory leak.

Abstract: Request flow log retrieval can include extracting one or more keywords from a natural language description of an action, the action being a system response to a user request submitted to a resource-provisioning system during a user session. Request flow log retrieval can also include determining a classification of the action based on a correlation value generated by a classifier model trained using machine learning to classify actions performed by the resource-provisioning system, the classification based on the one or more keywords. Additionally, request flow log retrieval can include automatically identifying a request flow associated with the action based on the classification of the action and returning at least one system log entry corresponding to the request flow.

Abstract: A method including receiving, from a user device, a user request to access data associated with a web page; generating, by a processor, a first transaction identification; collecting transaction information, the transaction information comprising server-side metrics; integrating, by the processor, the first transaction identification with the transaction information; transmitting, by the processor, the first transaction identification to the user device; receiving, from the user device, client-side data associated with a second transaction identification; integrating, by the processor, the server-side metrics and the client-side data; and analyzing, by the processor, the integrated server-side metrics and the client-side data.

Abstract: Various implementations of the invention develop executable code for an embedded system, including a microcontroller and a device. Some implementations of the invention comprise a microcontroller development tool configured to operate on a general purpose computer.

Abstract: A method for testing software applications in a system under test (SUT) includes building a reference model of the SUT that defines a computer-based neural network. The method includes training the reference model using input data and corresponding output data generated by the SUT, selecting an output value within a domain of possible output values of the SUT representing an output that is not represented in the output data used to train the reference model, applying the selected output value to the reference model, and tracing the selected output through the reference model to identify test input values that when input to the reference model, produce the selected output value. The method can further include using the identified test input values to test the system under test.

Abstract: Diffing subject and comparison traces. A first call tree representing function calls made by a first executable entity is created based on subject trace, and a second call tree representing function calls made by a second executable entity is created based on a comparison trace. A differencing tree is created from the call trees, with differencing tree nodes indicate a differencing status between the first and second call trees. A differencing cost is assigned to each differencing tree node, based at least on the nodes' differencing status. A differencing tree node is identified based on following nodes that most contribute to differences between the first and second call trees, and it is used to provide an indicia of a difference between the first and second function calls.

Abstract: Described are a system, method, and computer program product for operating dynamic shadow testing environments for machine-learning models. The method includes storing a testing policy including an identifier of a machine-learning model and an identifier of a transaction service. The method includes generating a shadow testing environment operating the transaction service using the machine-learning model. The method also includes receiving, at a transaction service provider system, a transaction authorization request including transaction data of a transaction associated with a payment device. The method further includes identifying the machine-learning model associated with the transaction based on a parameter of the transaction data. The method further includes determining, based on the identifier of the machine-learning model, the testing policy and the shadow testing environment.

Abstract: The present disclosure is directed to systems, media, and methods of generating test authorization for financial transactions. One or more computing devices generate an initial data set corresponding to a financial transaction. Alterations to one or more fields of information included in the initial data set are made responsive to instructions received via a user interface. Responsive to the alterations, the one or more computing devices: convert the test data set into a binary file, deserialize the binary file, and generate a transaction file for the financial transaction based on the deserialized test data set.

Abstract: A method and apparatus for testing a map service are provided. The method may include: determining a to-be-screened service request based on a service request of an electronic map recorded in advance at a preset sampling frequency; screening the to-be-screened service request by using a static rule, to obtain a first valid service request set; screening the to-be-screened service request by using a dynamic test step, to obtain a second valid service request set; and testing a service of the electronic map based on the first valid service request set and the second valid service request set.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for testing open source software are disclosed. In one aspect, a method includes the actions of receiving, from a user device and by a presubmit check server system that is configured to perform presubmit checks on system software code updates, a system software code update and a request to perform a presubmit check on the system software code update. The actions further include requesting, from a system software code server system that is configured to store system software code, presubmit check code. The actions further include receiving, from the system software code server system, a presubmit check code module. The actions further include executing the presubmit check code module against the system software code update. The actions further include providing a report that indicates results of the presubmit check code module execution against the software code update.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.

Abstract: The subject matter described herein provides systems and techniques to counter a high write amplification in physical memory, to ensure the longevity of the physical memory, and to ensure that the physical memory wears in a more uniform manner. In this regard, aspects of this disclosure include the design of a Flash Translation Layer (FTL), which may manage logical to physical mapping of data within the physical memory. In particular, the FTL may be designed with a mapping algorithm, which uses reinforcement learning (RL) to optimize data mapping within the physical memory. The RL technique may use a Bellman equation with q-learning that may rely on a table being updated with entries that take into account at least one of a state, an action, a reward, or a policy. The RL technique may also make use a deep neural network to predict particular values of the table.

Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data. An SSD controller may manage reading and writing data to the flash memory. The SSD may include an automatic stream detection logic to select a stream identifier responsive to attributes of data. A garbage collection logic may select an erase block and program valid data in the erase block into a second block responsive to a stream ID determined the automatic stream detection logic. The stream ID may be determined after the garbage collection logic has selected the erase block for garbage collection.

Abstract: A flash memory controller includes a read only memory (ROM) and a microprocessor. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control access of a flash memory module. When executing the program code, the microprocessor is arranged to perform operations of: monitoring data retention state of one or more blocks in the flash memory module by reading a last page of the one or more blocks to obtain time information regarding the one or more blocks, which is generated by the flash memory controller; and arranging a specific block to a garbage collection process if time information obtained from the last page of the specific block exceeds a threshold.

Abstract: A memory controller includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is configured to control access of a flash memory device. The microprocessor is configured to obtain a number of spare blocks of the flash memory device corresponding to a first operation period, determine a write speed compensation value, determine a target write speed according to the write speed compensation value and a balance speed, and determine a target garbage collection speed according to the target write speed. The microprocessor is further configured to perform one or more write operations in response to one or more write commands received from a host device in the first operation period according to the target write speed and perform at least one garbage collection operation according to the target garbage collection speed.

Abstract: Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.

Abstract: An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

Abstract: A storage control system receives a first write request and a second write request following the first write request. The first and second write requests comprise respective first and second data items for storage to a primary storage. First and second cache write operations are performed in parallel to write the first and second data items a persistent write cache. The first cache write operation comprises a split write operation which comprises writing a parsing header for the first data item to the write cache, and writing a payload of the first data item to the write cache. The second cache write operation comprises storing the second data item and associated metadata in the write cache, and waiting for an acknowledgment that the parsing header for the first data item has been successfully stored in the write cache before returning an acknowledgment indicating successful storage of the second data item.

Abstract: Techniques are disclosed for preventing overwriting of shared line segments. The techniques include sending a data unit from a first processor to second processor using an augmented hardware cache coherency protocol, the augmented hardware cache coherency protocol being augmented to maintain dirty bits information during an exchange of the data unit within a cache coherency domain. A size of the data unit is a fraction of a size of any shared line of a shared memory, and writing the data unit to a segment of a shared line of a shared memory includes using another protocol, without overwriting another segment of the shared line. The writing is based at least in part on the dirty bits information, and the other protocol does not support hardware coherency and maintains the dirty bits information.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing rolling updates of distributed systems with a shared cache. An embodiment operates by receiving a platform update request to update data item information associated with a first version of a data item cached in a shared cache memory. The embodiment may further operate by transmitting a cache update request to update the data item information of the first version of the data item cached in the shared cache memory, and isolating the first version of the data item cached in the shared cache memory based on a collection of version specific identifiers and a version agnostic identifier associated with the data item.

Abstract: Aspects of the present disclosure include methods and system for fast allocation of memory from fragmented memory. In one example, at a processor receives a request for an address to a buffer stored in a magazine associated with the processor. Upon determining that the magazine associated with the processor is empty, a request is made to a depot layer for additional memory. Upon determining that the depot layer cannot satisfy the request for the additional memory, executing a call to a slab layer for the additional memory. The slab layer identifies one or more partially-allocated slabs and generates a new magazine. A set of addresses correspond to buffers may be stored in the new magazine. A reference to the new magazine may be transferred from the slab layer to the depot layer. The reference to the new magazine may then be transferred from the depot layer to the processor.

Abstract: A virtual disk is provided to a computing environment. The virtual disk includes identity information to enable identification of a virtual machine within the computing environment. A size of the virtual disk is increased within the computing environment to enable the virtual disk to act as a storage for the identity information and as a cache of other system data to operate the virtual machine. The virtual machine is booted within the computing environment. The virtual machine is configured to at least access the virtual disk that includes both identity information and caches other system data to operate the virtual machine. Related apparatus, systems, techniques and articles are also described.

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: A flash memory controller includes a processor and a cache. When the processor receives a specific write command and specific data a host, the processor stores the specific data into a region of the cache, and the processor generates host-based cache information or flash-memory-based cache information to build or update/optimize a binary tree with fewer number of nodes to improve the searching speed of the binary tree, reducing computation overhead of multiple cores in the flash memory controller, and minimizing the number of accessing the cache to reduce the total latency wherein the host-based cache information may indicate dynamic data length and flash-memory-based cache information indicates the data length of one writing unit such as one page in flash memory chip.

Abstract: Methods, systems, and devices for cache metadata management in a memory subsystem are described. The memory subsystem may include an interface controller coupled with a non-volatile memory and a volatile memory. The interface controller may use metadata, such as validity information and dirty information, to operate the volatile memory as cache. The interface controller may store the dirty information in the volatile memory and may store the validity information in an array in the interface controller.

Abstract: Disclosed is a method of managing memory of a virtual machine (VM), including receiving, at a physical input-output memory management unit (IOMMU) of a processing device operating the VM, a request from a VM IOMMU for VM memory address translation for a VM peripheral component interconnect (PCI) device created on the VM; determining, by the physical IOMMU, a corresponding VM memory address translation result based on the request as received and a memory translation table; and transmitting, by the physical IOMMU to the VM IOMMU, the corresponding VM memory address translation result for servicing the request for VM memory address translation of the VM PCI device.

Abstract: Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources available at a target system are discovered over a network. A configuration is determined of virtual target storage resources mapping to the target storage resources for a host node. The configuration is registered with a virtual target. The configuration maps the virtual target storage resources to the target storage resources at the target system and an access control list of the host node allowed to access the virtual target storage resources. A query is received from the host node for the target storage resources the host node is permitted to access according to the access control list. Host discovery information is returned to the requesting host node indicating the virtual target storage resources the requesting host node is provisioned to access from the virtual target.

Abstract: An integrated circuit, comprising: a volatile memory module configured to store a cryptographic key; a capacitor array for providing power to the volatile memory module; and a power switching logic arranged to connect and disconnect the memory module from the capacitor array, the power switching logic being configured to operate in at least one of a first operating mode and a second operating mode, wherein, when the power switching logic operates in the first operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting a change of state of a break line, and, when the power switching logic operates in the second operating mode, the power switching logic is configured to disconnect the capacitor array from the volatile memory module in response to detecting that a voltage at a connection terminal of the integrated circuit exceeds a threshold.

Abstract: The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.

Abstract: A memory device such as a page mode NAND flash including a page buffer, and an input/output interface for I/O data units having an I/O width less than the page width supports continuous page read with non-sequential addresses. A controller controls a continuous page read operation to output a stream of pages at the I/O interface. The continuous read operation includes responding to a series of commands to output a continuous stream of pages. The series of commands including a first command and a plurality of intra-stream commands received before completing output of a preceding page in the stream. The first command includes an address to initiate the continuous page read operation, and at least one intra-stream command in the plurality of intra-stream commands includes a non-sequential address to provide the non-sequential page in the stream of pages.

Abstract: A bus system is provided. A memory device is electrically connected to a master device via a serial peripheral interface (SPI) bus. A plurality of slave devices are electrically connected to the master device via an enhanced SPI (eSPI) bus. Each of the slave devices has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. The first slave device is electrically connected to the memory device via the SPI bus. After obtaining a program code from the memory device, the first slave device verifies the program code using a security code and controls the alert-handshake control line to unlock all the slave devices except for the first slave device via the alert handshake pin in response to the program code being verified. The unlocked slave devices communicate with the master device via the eSPI bus.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Abstract: An integrated circuit is provided, which includes: a processor, a general interrupt controller, and a bus master. The bus master includes: a bus-control circuit and a polling circuit, which is configured to detect whether an interrupt signal of the sensing device is asserted. In response to the polling circuit detecting that the interrupt signal is asserted, the bus-control circuits fetches each task stored in a task queue of a memory in sequence, and performs one or more data-transfer operations corresponding to each task to obtain sensor data from the sensing device. In response to a task-completion signal of the tasks generated by the bus-control circuit, the general interrupt controller generates an interrupt request signal. In response to the interrupt request signal, the processor reports a sensor event using the sensor data obtained by the data-transfer operations corresponding to each task.

Abstract: A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.

Abstract: A control device including a USB port of a first interface capable of transmitting an image signal serving as a basis of an image to be displayed by the control device and capable of receiving power, and a port of a second interface capable of receiving power, is provided. The control device is accommodated in a housing, the USB port is disposed at a bottom surface which, given a surface of the housing where the touch panel is disposed as a front surface, is a side surface positioned in a longitudinal direction of the front surface, and the port is disposed at a rear surface opposite the front surface.

Abstract: Various embodiments for managing assets in a data center device rack include: establishing a data connection between a cabinet level controller and at least one primary power distribution unit (PDU); using a first electrical outlet on the primary PDU to establish an electrical connection between the primary PDU an electrical asset in a data center equipment rack; using a first asset interface connector on the cabinet level controller to establish a data connection between the cabinet level controller and the electrical asset in the data center equipment rack, the first electrical outlet and the first asset interface connector being in horizontal alignment; using a router integrated into the cabinet level controller to connect the cabinet level controller to a wide area Internet Protocol (IP) network; and using the router to establish a single IP address corresponding to a plurality of electrical assets in the data center equipment rack.

Abstract: Disclosed is an RS-485 circuit, which includes an RS-485 interface chip, a start detector, a control module and a counter. The RS-485 interface chip includes a data input terminal and an enable terminal, wherein the data input terminal is configured to receive a data signal, the enable terminal is configured to receive a start signal or a switching signal to make the RS-485 interface chip in a data transmitting state or a data receiving state. The start detector is configured to detect a first signal edge of the data signal to generate the start signal to the enable terminal. After detecting the first signal edge of the data signal, the control module outputs first counting information. The counter is configured to count based on the first counting information, and output the switching signal to the enable terminal when the counter expires.

Abstract: A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

Abstract: A hybrid electrical and optic system-on-chip (SOC) device configured for both electrical and optic communication includes a substrate, an electrical device configured for electrical communication arranged on the substrate, a photonics device configured for optic communication arranged on the substrate, and a self-test module arranged on the substrate. The self-test module is configured to receive a loop-back signal indicative of an optical signal output from the photonics device and calibrate the photonics device based on the loop-back signal.

Abstract: In one embodiment of the present invention, a programmable vision accelerator enables applications to collapse multi-dimensional loops into one dimensional loops. In general, configurable components included in the programmable vision accelerator work together to facilitate such loop collapsing. The configurable elements include multi-dimensional address generators, vector units, and load/store units. Each multi-dimensional address generator generates a different address pattern. Each address pattern represents an overall addressing sequence associated with an object accessed within the collapsed loop. The vector units and the load store units provide execution functionality typically associated with multi-dimensional loops based on the address pattern. Advantageously, collapsing multi-dimensional loops in a flexible manner dramatically reduces the overhead associated with implementing a wide range of computer vision algorithms.

Abstract: Systems and methods permit gloveless filling containers with a product. A filling arm is disposed within the chamber. An optical sensor is configured to locate and target openings of the containers within the chamber. Locations of the openings are used to guide the filling arm to fill the containers with a product.