Abstract: One or more processors examine source code of one or more software packages that produce output messages and identify, in the source code, one or more call expressions that each represent a logging call. The one or more processors generate a number of search patterns for parsing output messages produced by the one or more software packages, wherein each of the search patterns is based on one or more arguments of a corresponding call expression of the one or more call expressions. The one or more processors further reduce the number of search patterns to be applied to the output messages produced by the one or more software packages to identify log entries among the output messages.

Abstract: System and method are provided for facilitating performance testing.

Abstract: A system may execute a pipelined multiple-tier test stack to support migration of computing resources via a migratory data stream. Via the pipelined multiple-tier test stack, the system may perform extract, transform, and load operations on the migratory data stream. The extract, transform, and load operations may be used to identify applications that may undergo testing. At a generation tier of the pipelined multiple-tier test stack, the system may generate test scripts, which may be used to test the application. The tests may be validated by the system via a validation tier of the pipelined multiple-tier test stack. To govern the operations, the pipelined multiple-tier test stack may rely on a multi-point reference data model.

Abstract: A system and a method for automatically testing software builds. The system includes testing a first software build using a test package. The test package includes at least a test strategy, a test case, a test model, an automation test script, a crowdsource script, and a manual test script. Further, baseline data is generated based upon a successful execution of the test package on the first software build. Further, a second software build is tested using the test package. Subsequently, the target data is generated based upon an execution of the test package on the second software build. The system then identifies a change in the second software build by comparing the target data with the baseline data. Further, a modification is recommended to the test package for the second software build using Artificial Intelligence (AI) techniques and Natural Language Processing (NLP).

Abstract: Systems and methods for generating a dataset of synthesized data items from a dataset of original data items are disclosed herein. Some embodiments include (i) selecting an original data item from the dataset of original data items, where each original data item (a) comprises a combination of first-type codes and second-type codes, and (b) is associated with a topic in a topic model; and (ii) generating a synthesized data item based on the original data item and the topic associated with the original data item, where the synthesized data item comprises a combination of first-type codes and second-type codes that differs from the combination of first-type codes and second-type codes in the original data item by one first-type code or one second-type code.

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

Abstract: A storage apparatus includes: a memory that stores data and main management information, the main management information identifying a physical address of the data; and processing circuitry configured to generate preliminary management information that includes information of the same content as the main management information, and select, as use management information, any one of the main management information and the preliminary management information upon start of the storage apparatus. Access to the data stored in the memory is performed using the selected use management information.

Abstract: Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: A method of managing a garbage collection (GC) operation includes: comprising: selecting a source block and at least one candidate source block from the flash memory; calculating an overall valid page percentage according to a number of valid pages in the source block and the at least one candidate source block; determining a GC-to-host base ratio according to the overall valid page percentage; and performing the GC operation on the source block according to at least the GC-to-host base ratio.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: A data processing apparatus includes a requester, a completer and a cache. Data is transferred between the requester and the cache and between the cache and the completer. The cache implements a cache eviction policy. The completer determines an eviction cost associated with evicting the data from the cache and notifies the cache of the eviction cost. The cache eviction policy implemented by the cache is based, at least in part, on the cost of evicting the data from the cache. The eviction cost may be determined, for example, based on properties or usage of a memory system of the completer.

Abstract: A computer implemented system and method of memory management for an in-memory database. The system implements a paged data vector using non-uniform compression of its chunks. In this manner, the system achieves greater compression than systems that use uniform compression.

Abstract: A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

Abstract: Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.

Abstract: Described herein is a memory architecture that is configured to dynamically determine an address encoding to use to encode multi-dimensional data such as multi-coordinate data in a manner that provides a coordinate bias corresponding to a current memory access pattern. The address encoding may be dynamically generated in response to receiving a memory access request or may be selected from a set of preconfigured address encodings. The dynamically generated or selected address encoding may apply an interleaving technique to bit representations of coordinate values to obtain an encoded memory address. The interleaving technique may interleave a greater number of bits from the bit representation corresponding to the coordinate direction in which a coordinate bias is desired than from bit representations corresponding to other coordinate directions.

Abstract: A pre-read data caching method and apparatus, a device, and a storage medium, the method including: receiving a read command for a target file; if determining that there is target pre-read data of the target file in a pre-read queue, then moving the pre-read data from the pre-read queue into a secondary cache queue; reading the target pre-read data in the secondary cache queue; and, after reading is complete, moving the target pre-read data from the secondary cache queue into a reset queue, the invalidation priority level of the pre-read queue being the lowest.

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

Abstract: Examples described herein can be used to allocate replacement receive buffers for use by a network interface, switch, or accelerator. Multiple refill queues can be used to receive identifications of available receive buffers. A refill processor can select one or more identifications from a refill queue and allocate the identifications to a buffer queue. None of the refill queues is locked from receiving identifications of available receive buffers but merely one of the refill buffers is accessed at a time to provide identifications of available receive buffers. Identifications of available receive buffers from the buffer queue are provide to the network interface, switch, or accelerator to store content of received packets.

Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.

Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.

Abstract: A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

Abstract: A device for processing commands to manage non-volatile memory includes a controller configured to obtain address information from a command, read, based on the address information, an entry of a metadata table, and determine, based on the entry of the metadata table, whether a metadata page corresponding to the address information is being processed by the controller. In response to determining that the metadata page corresponding to the address information is being processed, the controller determines a processing status of the metadata page, among a plurality of processing statuses, based on the entry of the metadata table and processes the command according to the processing status of the first metadata page. In response to determining that the metadata page corresponding to first address information is not being processed, the controller reads the metadata page from the non-volatile memory based on the entry of the metadata table.

Abstract: Data base performance is improved using write-behind optimization of covering cache. Non-volatile memory data cache includes a full copy of stored data file(s). Data cache and storage writes, checkpoints, and recovery may be decoupled (e.g., with separate writes, checkpoints and recoveries). A covering data cache supports improved performance by supporting database operation during storage delays or outages and/or by supporting reduced I/O operations using aggregate writes of contiguous data pages (e.g., clean and dirty pages) to stored data file(s). Aggregate writes reduce data file fragmentation and reduce the cost of snapshots. Performing write-behind operations in a background process with optimistic concurrency control may support improved database performance, for example, by not interfering with write operations to data cache. Data cache may store (e.g., in metadata) data cache checkpoint information and storage checkpoint information. A stored data file may store storage checkpoint information (e.g.

Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Abstract: A memory system may include a memory device suitable for storing data and a controller suitable for generating and managing map data comprising a logical address of an external device and a physical address of the memory device corresponding to the logical address. The controller uploads at least some of the map data to the external device and uploading a latest version of the uploaded map data to the external device again based on dirty information or access information. The dirty information indicates whether a physical address corresponding to a logical address included in the uploaded map data has been changed. The access information indicates whether an access request for the logical address included in the uploaded map data from the external device has been made.

Abstract: Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

Abstract: A computing device includes a non-volatile memory (NVM) interface and a processor. The NVM interface is configured to communicate with an NVM. The processor is configured to store in the NVM Type-Length-Value (TLV) records, each TLV record including one or more encrypted fields and one or more non-encrypted fields, the non-encrypted fields including at least respective validity indicators of the TLV records, to read the TLV records that include the encrypted fields and the non-encrypted fields from the NVM, and to invalidate selected TLV records by modifying the respective validity indicators of the selected TLV records that are stored in the non-encrypted fields.

Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.

Abstract: A memory controller for controlling a non-volatile memory device includes a key management unit configured to control an access right to a secure key based on a biometric authentication message and a unique value, which are received from an external device; and a data processing unit configured to encrypt data received from a host and decrypt data stored in the non-volatile memory device based on the secure key.

Abstract: A method of synchronizing time between a host device and a storage device is provided. The method includes: identifying, by the storage device, a time synchronization interval; notifying the time synchronization interval from the storage device to the host device; providing host time information from the host device to the storage device during the time synchronization interval; and synchronizing, by the storage device, time information of the storage device with the host time information.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: Enabling multi-channel communications between controllers in a storage array, including: creating a plurality of logical communications channels between two or more storage array controllers; inserting, into a buffer utilized by a direct memory access (‘DMA’) engine of a first storage array controller, a data transfer descriptor describing data stored in memory of the first storage array controller and a location to write the data to memory of a second storage array controller; retrieving, in dependence upon the data transfer descriptor, the data stored in memory of the first storage array controller; and writing, via a predetermined logical communications channel, the data into the memory of the second storage array controller in dependence upon the data transfer descriptor.

Abstract: A method for execution by a low voltage drive circuit (LVDC) operably coupled to a bus includes, when activated, setting data reception for a control channel of a plurality of channels on the bus, where the control channel is a sinusoidal signal having a known frequency. The method further includes receiving the control channel and capturing a cycle of the control channel when the control channel is void of a data communication. The method further includes comparing the cycle of the control channel with a cycle of a first receive clock signal of the LVDC and when the cycle of a first receive clock signal compares unfavorably to the cycle of the control channel, adjusting phase and/or frequency of the cycle of the first receive clock signal to substantially match phase and/or frequency of the cycle of the control channel to produce an adjusted first receive clock signal.

Abstract: A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.

Abstract: A method to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without USB On the Go (OTG) controllers or additional vehicle wiring or inhibiting the functionality of any consumer devices connected to the same USB Hub. Preferably, the method is configured to provide that no additional cabling or hardware changes to accommodate this capability. The method can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port. When the consumer device is acting as a USB Host, signals between the consumer device and the vehicle's embedded USB Host are processed through a USB bridge, thereby rendering the consumer device compatible with the vehicle's embedded USB Host.

Abstract: Designs for enabling safe insertion and removal of computing components from a live motherboard are presented herein. In one example, a method includes maintaining a slot power connection and an auxiliary power connection for a peripheral card slot in a powered-off state, and sensing insertion of a peripheral card into the peripheral card slot and responsively detecting whether the auxiliary power connection is employed by the peripheral card. Based on detecting the auxiliary power connection is employed by the peripheral card, the method further includes applying current limits selected for the peripheral card to the slot power connection and the auxiliary power connection and concurrently enabling the slot power connection and the auxiliary power connection for the peripheral card.

Abstract: A reconfigurable data processor includes a plurality of configurable units, and a configuration controller. The configuration controller is configured to start execution of a first application graph in a first set of configurable units. Then, concurrently with the execution of the first application graph in the first set of configurable units, the configuration controllers receive a command to load a configuration file into a second set of configurable units and obtain the configuration file. The configuration file contains information to configure the second set of configurable units to execute a second application graph. The configuration file is then loaded into the second set of configurable units and execution of the second application graph is started in the second set of configurable units.

Abstract: A server rack has server sleds, each including a motherboard upon which is mounted: a memory module, a cache, at least one CPU connected to the cache, a memory controller connected to the cache and the memory module, an I/O hub, and a fabric interface (FIC) having a memory bridge and optical transceivers, where this memory bridge is connected to the I/O hub through this motherboard. The rack also has a memory sled disaggregated from the server sleds and that includes: a motherboard upon which is mounted: memory modules and a FIC having a memory bridge, a memory controller and optical transceivers, wherein this memory controller is connected to these memory modules through this motherboard, and wherein this memory bridge connects the memory controller to the optical transceivers. The rack has a photonic cross-connect switch interconnected by optical fiber cables to the optical transceivers of the server and memory sleds.

Abstract: An electronic apparatus and a hot-swappable storage device thereof are provided. The hot-swappable storage device includes a carrier, a connector, a controller, and a wireless communication interface. The carrier is configured to carry a plurality of storage components. The connector is configured to be electronically connected to a host end for performing a data transfer operation. The controller detects a connection status between the connector and the host end. The wireless communication interface decides whether to perform the data transfer operation according to the connection status.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A microprocessor system comprises a computational array and a hardware data formatter. The computational array includes a plurality of computation units that each operates on a corresponding value addressed from memory. The values operated by the computation units are synchronously provided together to the computational array as a group of values to be processed in parallel. The hardware data formatter is configured to gather the group of values, wherein the group of values includes a first subset of values located consecutively in memory and a second subset of values located consecutively in memory. The first subset of values is not required to be located consecutively in the memory from the second subset of values.

Abstract: The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured fine-grain parallel computations. The execution engine includes a memory for storing data and a domain flow program, a controller for requesting the domain flow program from the memory, and further for translating the program into programming information, a processor fabric for processing the domain flow programming information and a crossbar for sending tokens and the programming information to the processor fabric.

Abstract: Systems and methods of the present disclosure may read source data corresponding to a source variable and apply a transformation to the source variable to generate an output variable. Accordingly, one such method comprises receiving a request to generate an output variable by applying one or more data transformations to a source variable; before applying an actual data transformation to the source variable, checking a database of prior data transformations that have been applied to source variables to generate existing output variables for a match with the requested one or more data transformations to the source variable; determining that a match exists in the database, wherein the match is associated with an existing output variable; and/or responding to the request by providing the existing output variable associated with the match that exists in the database of prior data transformations.

Abstract: Embodiments of the present disclosure provide methods, electronic devices and computer program products for accessing data. A method comprises receiving, at a first device, a file system operation request for accessing target data, the target data being stored at a second device after being pre-processed, and the first device providing a file system interface for data stored at the second device; forwarding the file system operation request to the second device, such that the target data is restored at the second device; receiving the restored target data from the second device; and providing the target data as a response to the file system operation request. Embodiments of the present disclosure allow users to access backup data stored after being pre-processed through normal file system operations and can achieve high data access performance.

Abstract: Systems and methods facilitating namespace representation and enhanced browsability for replicated file systems are described herein. A method as described herein can include computing, by a device operatively coupled to a processor, a first length of a first object key for a first data object, wherein the first object key comprises a directory path associated with the first data object; in response to determining that the first length is larger than a threshold, creating, by the device, a second data object having a second object key that comprises a representation of the directory path associated with the first data object; and altering, by the device, the first object key in response to the creating the second data object, resulting in an altered first object key that comprises a reference to the second data object instead of the directory path associated with the first data object.

Abstract: A method that includes receiving a request to select one or more files for a user; in response to receiving the request, identifying file request context information associated with the request, wherein the file request context information is based at least in part on a current state of a user device; identifying one or more candidate files based on the file request context information; identifying a relevance measure for the one or more candidate files based on the file request context information; identifying one or more candidate user contacts based on the file request context information, each of the one or more candidate user contacts having sent communications to or received communications from the user, wherein the communications include at least one of the one or more candidate files; and providing, for display to the user, a display portion of a user interface for selection pertaining to the one or more files and the one or more candidate user contacts, the display portion including a representation

Abstract: Embodiments of the present disclosure provide a method and an apparatus for opening a file, and an electronic device. Embodiments of the present disclosure receive the file opening request, obtain the format information of the file to be opened indicated by the file opening request, search for application information of the target application for opening the file to be opened according to the format information, provide the application entry of the target application in the current interface according to the application information, obtain the configuration file corresponding to the target application when the application entry is triggered, and generate the native interface of the target application according to the configuration file and open the file to be opened in the native interface.