Abstract: Distributed gain equalization circuits for use with radio frequency (RF) devices are provided. The distributed gain equalization circuits include a substrate layer, multiple transverse electromagnetic (TEM) line circuits disposed on the substrate layer and multiple traces disposed on the substrate layer, each trace connected to one or more of the TEM line circuits. The traces and TEM line circuits are configured to provide resistances, inductances and capacitances to eliminate the need for lumped or packaged resistors, inductors and capacitors. The distributed gain equalization circuit operates at millimeter wave frequencies and provides a compensating gain slope to counteract a negative gain slope of the RF device. Methods of manufacturing distributed gain equalization circuits are also provided.

Abstract: Systems and methods for limiting volume in an audio playback device using a feedback controller are disclosed herein. In one example, a gain stage modulates gain of an audio signal based in part on feedback from a downstream limiter. The gain stage receives a first audio signal as well as a feedback signal from the feedback controller. Based at least in part on the feedback signal from the feedback controller, the gain stage modulates a gain of the first audio signal to provide a second audio signal. The second audio signal is delivered to the limiter, which limits the second audio signal to produce an output signal. The output signal is played back via a transducer. The feedback controller receives a gain reduction value from the limiter and determines a feedback signal to provide to the gain stage upstream of the limiter.

Abstract: A thin-film filter may include a monolithic substrate and a patterned conductive layer formed over the monolithic substrate. The patterned conductive layer may include at least one thin-film inductor. The thin-film filter may have a power capacity that is greater than about 25 W. In some embodiments, the thin-film inductor(s) may be connected between the input port and the output port. A heat sink terminal may be exposed along the bottom surface of thin-film filter. In some embodiments, the heat sink terminal may have an exposed heat sink area, and the bottom surface of the thin-film filter has an area that is less than 20 times larger than the exposed heat sink area.

Abstract: Circuits and methods that provide wider bandwidth and smaller IM inductances for phase change material (PCM) based RF switch networks. The present invention recognizes that it is beneficial to consider the total high parasitic capacitance to ground of the various PCM switches in an RF switch network as constituting two or more separate capacitive contributions. This leads to several “split capacitance” concepts, including signal-path splitting, switch-block splitting, stacked-switch splitting, and splitting parasitic capacitances due to layout discontinuities, in which compensating impedance matching inductances are inserted between additive capacitances.

Abstract: A low radio frequency electro-mechanical load pull impedance tuner uses four rotary, remotely controlled variable shunt capacitors and three fixed series transmission lines to create up to 108 independently controllable impedance states at each frequency covering the entire Smith chart in the frequency range between 1 and 10 MHz; the capacitors and control motors and gear are immersed in high epsilon dielectric fluid inside individual sealed containers. Appropriate Error Function-based optimization algorithms, allow fast impedance tuning at the fundamental frequency at the output of DUT's operated in high gain compression. Stepper motors, drivers and control software are used to remotely control the variable shunt capacitors of the tuner and allow it to be automated, pre-calibrated and used in an automated load pull measuring setup.

Abstract: A device includes a die and an interdigital transducer on the die. The interdigital transducer includes a first bus bar, a second bus bar, and a number of electrode fingers. The first bus bar is parallel to the second bus bar. The electrode fingers are divided into a first set of electrode fingers and a second set of electrode fingers. The first set of electrode fingers extend obliquely from the first bus bar towards the second bus bar. The second set of electrode fingers extend obliquely from the second bus bar towards the first bus bar, and are parallel to and interleaved with the first set of electrode fingers. By providing the electrode fingers oblique to the bus bars, spurious transverse modes may be suppressed while maintaining the quality factor, electromechanical coupling coefficient, and capacitance of the device.

Abstract: Acoustic sensor devices and sensor systems are disclosed. An acoustic sensor device includes a piezoelectric plate having a front surface and a back surface. A floating back-side conductor pattern is formed on the back surface. A first and second front-side conductor patterns are formed on a portion of the front surface opposite the back-side conductor pattern. A sensing layer is formed over all or a portion of the floating back-side conductor pattern.

Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.

Abstract: Examples of contactor controllers, systems and methods time-modulate levels of high-side (HS) and low-side (LS) clamp voltages in a contactor controller to switch a path through which current flows during quick-turn-off (QTO) of the contactor controller. One of the clamp voltages is at a high level and the other is at a low level. The output voltage of the contactor controller is held at the low level. The path switching may be a function of one or more parameters. In a configuration, the level of a supply voltage of the contactor controller is monitored and used to control the path switching. In a configuration, temperatures of HS and LS transistors of the contactor controller are monitored and used to control the path switching. Control of the path switching may be performed to dissipate power in a larger area to increase thermal performance of the contactor controller. Both clamps may remain active throughout the QTO process, providing redundancy and safety.

Abstract: A chip with pad tracking having an input/output buffer (I/O buffer), a pad, and a bias circuit. The I/O buffer is powered by a first power and is coupled to the pad. The pad is coupled to the system power. The bias circuit generates a bias signal to be transferred to the I/O buffer to block a leakage path within the I/O buffer when the system power is on and the first power is off. The bias circuit is a voltage divider which generates a divided voltage as the bias signal. In an example, the bias circuit is powered by a second power that is independent from the first power and is not drawn from the pad. In another example, a power terminal of the bias circuit is coupled to an electrostatic discharging bus, and the pad is coupled to the electrostatic discharging bus through a diode.

Abstract: A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.

Abstract: A buffer circuit, a frequency dividing circuit, and a communications device are disclosed. The buffer circuit includes a buffer, a first control circuit, and a second control circuit. The buffer is coupled to a frequency divider, and the buffer is configured to receive a first signal output by the frequency divider, and output a fourth signal by using an output terminal of the buffer circuit when driven by the first signal, where the first signal is obtained by the frequency divider by performing frequency division on a group of differential signals, and the differential signals include a second signal and a third signal. The first control circuit is configured to perform delay control on a rising edge of the fourth signal based on the second signal. The second control circuit is configured to perform delay control on a falling edge of the fourth signal based on the third signal.

Abstract: Circuits and methods for performing a hash algorithm are disclosed. A circuit includes: an input module receiving data; and an operation module calculating a hash value based on the received data. The operation module includes multiple operation stages (0th operation stage, 1st operation stage, up to P-th operation stage, P being a fixed positive integer greater than 1 and less than the number of operation stages in a pipeline structure) arranged in the pipeline structure. Each of the 1st operation stage to P-th operation stage includes: cache registers storing intermediate values of a current operation stage and operating at a first frequency, and extension registers storing extension data of the current operation stage and the extension registers comprising a first set of extension registers operating at the first frequency and a second set of extension registers operating at a second frequency which is 1/N times the first frequency.

Abstract: A switch control circuit includes a power switch, a first protection unit, and a second protection unit. The power switch has a first terminal coupled to a first voltage terminal for receiving a first voltage, a second terminal coupled to a second voltage terminal for receiving a second voltage, and a control terminal receives a control voltage. In a first mode, the control voltage is greater than the first voltage. In a second mode, when a voltage of the second voltage terminal is smaller than a first reference voltage, the first protection unit pulls down the control voltage to reduce a current flowing through the power switch. When the voltage of the second voltage terminal is smaller than the second reference voltage, the second protection unit pulls down the control voltage to a ground voltage.

Abstract: In one example, an apparatus comprises: a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal; a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to: determine a state of a transistor based on the first voltage; and generate a driver signal at the control circuit output based on the state; and a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal.

Abstract: A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.

Abstract: A smart switch apparatus is coupled between a live wire of an indoor power and two output terminals of a SPDT (Single Pole Double Throw) switch. Two ends of a load are respectively connected to a neutral wire of the indoor power and an input terminal of the SPDT switch. The smart switch apparatus includes an on-off status detector, a switch position detector, a controller, an on-off controller and a power circuit. The on-off status detector is coupled to the live wire of the indoor power for generating an on-off status signal. The switch position detector is coupled to the two output terminals of the SPDT switch for generating a switch position signal. The controller is coupled to the on-off status detector and the switch position detector for receiving the on-off status signal and the switch position signal.

Abstract: The present disclosure provides a controller for controlling a GaN-based semiconductor device. The controller is configured to receive a current sensing signal VCS which is indicative of a drain-to-source current of the GaN-based semiconductor device and generate a control driving signal VDRV to the GaN-based semiconductor device such that a gate-to-source voltage VGS applied to the GaN-based semiconductor device for switching on the GaN-based semiconductor device is stabilized to a voltage value equal to a reference voltage Vref over an on-time duration. Impact of the change in the voltage drop across the current sensing resistor to the operation of the GaN-based semiconductor device is eliminated.

Abstract: A capacitive touch sensor is disclosed for use with input signal. The capacitive touch sensor includes a number n of input/output lines. Each of the number n of input/output lines is electrically disconnected from every other of the number n of input/output lines. Each of the number n of input/output lines is arranged to cross every other of the number n of input/output lines. Each of a number ? of positions includes one of the number n of input/output lines crossing another of the number n of input/output lines.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.

Abstract: Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.

Abstract: Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.

Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Abstract: A delta sigma modulator includes a summation circuit, at least one integrator, a multi-bit quantizer and a negative feedback circuit. The summation circuit is configured to produce a difference signal between a unipolar or bipolar analog input signal and an analog feedback signal. The integrator is operatively coupled to the summation circuit to integrate the difference signal. The multi-bit quantizer is operatively coupled to the integrator to digitize the integrated signal to generate an N-bit digital output signal, N being an integer greater than 1. The negative feedback circuit operatively couples the multi-bit quantizer to the summation circuit. The negative feedback circuit includes a digital-to-analog converter arrangement for receiving the N-bit digital output signal and providing the analog feedback signal such that digital values of the N-bit digital output signal and values of the analog feedback encoded by the digital values have a non-linear relationship to one another.

Abstract: A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.

Abstract: Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

Abstract: A data compressor a zero-value remover, a zero bit mask generator, a non-zero values packer, and a row-pointer generator. The zero-value remover receives 2N bit streams of values and outputs 2N non-zero-value bit streams having zero values removed from each respective bit stream. The zero bit mask generator receives the 2N bit streams of values and generates a zero bit mask for a predetermined number of values of each bit stream in which each zero bit mask indicates a location of a zero value in the predetermined number of values corresponding to the zero bit mask. The non-zero values packer receives the 2N non-zero-value bit streams and forms a group of packed non-zero values. The row-pointer generator that generates a row-pointer for each group of packed non-zero values.

Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Abstract: Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

Abstract: A radio frequency module and a communication device capable of reducing a mounting substrate size. The radio frequency module includes a mounting substrate, a first filter, and a second filter. The mounting substrate has a first main surface and a second main surface that are on opposite sides of the mounting substrate. The first filter is provided on the first main surface and allows a first receiving signal in a first frequency band to pass through. The second filter is stacked on the first filter and allows a second receiving signal in a second frequency band different from the first frequency band to pass through.

Abstract: A switching circuit comprises a first filter, a second filter and a plurality of switches. The first filter is configured to filter a first frequency band, a second frequency band that is adjacent to the first frequency band and a gap band between the first frequency band and the second frequency band. The second filter is configured to filter the second frequency band. The plurality of switches is configured to route signals from an antenna through one of the first filter and second filter.

Abstract: One example discloses a multi-radio device, including: a controller configured to be coupled to a first radio that is configured to transmit a first signal, and a second radio that is configured to transmit a second signal; wherein the controller includes a detection element configured to detect a third signal generated in response to simultaneous transmission of the first and second signals; wherein the controller includes a decision element configured to modulate one or more information packets in the first and second signals in response to the third signal.

Abstract: An energy-efficient implementation of a WiFi transceiver is proposed in this disclosure. The WiFi transceiver comprises a receive chain comprising a variable receive (Rx) filter circuit and a variable Rx analog-to-digital converter (ADC) circuit. The receive chain is configured to receive a receive signal during a receive mode of operation, having a receive bandwidth associated therewith and receive a transmit signal associated with a transmit chain of the transceiver during a transmit mode of operation, having a transmit bandwidth associated therewith. The WiFi transceiver further comprises a control circuit configured to dynamically adapt a bandwidth of the variable Rx filter and the variable Rx ADC in the receive chain to the receive bandwidth or to the transmit bandwidth, based on the mode of operation.

Abstract: A radio-frequency module includes a module substrate; a power amplifier; a first switch connected to an input terminal of the power amplifier; a second switch connected to an output terminal of the power amplifier; and a switch control circuit that controls the first switch and the second switch. The first switch, the second switch, and the switch control circuit are included in a semiconductor IC being integrated into a single chip. The power amplifier and the semiconductor IC are mounted on or above the module substrate. When the module substrate is viewed in a plan view, in the semiconductor IC, the switch control circuit is disposed between the first switch and the second switch.

Abstract: Systems, methods, and apparatuses for wireless communication are described. Input data for in-phase branch/quadrature branch (I/Q) imbalance or mismatch may be compensated for or non-linear power amplifier noise may be used to generate compensated input data. In some examples, a transmitter may be configured to transmit communications signaling via a first antenna, the transmitter including a filter configured for digital mismatch correction; a receiver may be configured to receive communications signaling via a second antenna; and a switch may be configured to selectively activate a first switch path to couple the transmitter and the first antenna and a second switch path to couple the receiver and the transmitter to provide communications signaling received via the transmitter as feedback for the filter through the receiver.

Abstract: A radio frequency switch has an antenna end, a first signal end for transmitting a first radio frequency signal, a second signal end for transmitting a second radio frequency signal, a third signal end for transmitting a third radio frequency signal, a first series path having a first switch, a second series path having a second switch, a third series path having a third switch, a first shunt path coupled between the first signal end and a node, a second shunt path coupled between the second signal end and the node, a common path coupled between the node and a first reference voltage end, and a third shunt path coupled between the third signal end and a second reference voltage end. The first series path and the second series path are connected to a common ground pad via the common path.

Abstract: A multipath suppression method based on a steepest descent method includes stripping, according to carrier Doppler shift information fed back by a phase-locked loop, a carrier from an intermediate-frequency signal input into a tracking loop; constructing, on the basis of the autocorrelation characteristics of a ranging code, a quadratic cost function related to a measurement deviation of the ranging code, the cost function being not affected by a multipath signal; and finally, designing a new tracking loop of the ranging code according to the quadratic cost function and the principle of the steepest descent method, such that the loop has a multipath suppression function without increasing the computational burden. Compared with a narrow-distance correlation method, the current method reduces computing resources by ?, the design and adjustment of parameters are simple and feasible, a multipath suppression effect is superior, and a high engineering application value is obtained.

Abstract: Circuits with filters and acoustic resonators. In some embodiments, a radio-frequency circuit can include a plurality of nodes and a common node. The radio-frequency circuit can further include a signal path implemented between each of the plurality of nodes and the common node. Each corresponding signal path can include a filter having a first Q-factor value and a respective resonator having a second Q-factor value higher than the first Q-factor value.

Abstract: On-chip Multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided, The multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and/or selecting the tapped out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

Abstract: A network communication device includes a first output port, a second output port, and a converting circuit. The first output port may be in communication with an input port and may be configured to receive a first reduced-power version of the signal received at an input port. The converting circuit may be configured to receive a second reduced-power version of the signal, down-convert a high-frequency portion thereof, and produce a down-converted signal. The first and the second reduced-power versions of the signals are in the same frequency band. The second output port receives at least a portion of the down-converted signal such that the high frequency portion of the second reduced power version of the signal is attenuated before the signal is transmitted to a subscriber device.

Abstract: Technologies for provided for a radio frequency input/output (RFIO) combiner/splitter. An example combiner/splitter can include an RFIO circuit including a receive path including first and second low noise amplifiers (LNAs), first switches, resistors, and capacitors, each of the first switches being in series with a respective one of the first capacitors and first resistors; a transmit path including a first power amplifier (PA) including second switches coupled to second resistors and third switches coupled to third resistors, and a second PA including fourth switches coupled to fourth resistors and fifth switches coupled to fifth resistors, each of the second switches, the third switches, the fourth switches, and the fifth switches being in series with one or more respective ones of the second resistors, the third resistors, the fourth resistors, and the fifth resistors; and a balun that couples the Rx and Tx path to an RFIO terminal.

Abstract: A system includes a housing operably coupled with a vehicle system, and a vehicle monitoring system disposed within the housing comprising a wireless communication device including an antenna configured to wirelessly communication data signals. One or more ground radials are electrically coupled with the wireless communication device and conduct the data signals from the wireless communication device. The one or more ground radials form a ground plane of the antenna while the vehicle system is moving and the antenna is wirelessly communicating the data signals.

Abstract: An apparatus is disclosed with an absorptive filter. In an example aspect, an apparatus has a filter including a first filter port and a second filter port. The filter also includes a hybrid coupler, a signal combiner, a first filter unit, and a second filter unit. The hybrid coupler includes a first hybrid port, a second hybrid port, and a third hybrid port, with the first hybrid port coupled to the first filter port. The signal combiner is coupled to the second filter port. The first filter unit is coupled between the second hybrid port and the signal combiner. The second filter unit is coupled between the third hybrid port and the signal combiner.

Abstract: Wireless communication devices, systems, and methods related to mechanisms for transmitting and receiving reference signals in a high-speed train (HST) single frequency network (SFN). A base station (BS) determines a first frequency pre-compensation value for a reference signal transmitted via a first transmission and reception point (TRP) and a second frequency pre-compensation value for a reference signal via a second TRP. The BS notifies a user equipment (UE) of the first and second pre-compensation values through at least one of the TRPs. The BS applies the first pre-compensation value to the reference signal via the first TRP and the second pre-compensation value to the reference signal via the second TRP. The UE adjusts its tracking loop for the reference signal based on the pre-compensation values, reducing estimation and/or search overhead at the UE.