Abstract: A method performed by one or more processors comprises displaying code, receiving user selection of a portion of code, determining one or more settable data items, generating a template, displaying the template, receiving a user input value for the settable data items by the template, and executing the code with each of the settable data items set to the received user input value. A data processing pipeline is configured to pass a data item to a first transformer to provide first transformed data, store the first transformed data in a temporary memory, write the first transformed data to the data storage system, and pass the transformed data from the temporary memory to a second transformer.

Abstract: Systems and methods may generate code, for a model, with one or more service access points generated and at locations in the code based on an analysis of model constraints and deployment specifications (e.g., RTE specifications or OS specifications). The systems and methods may analyze the model and identify a functionality that needs an RTE service. The system and methods may receive deployment specifications. The systems and methods may generate code for the model, where an analysis of model constraints and the deployment specifications determine which service access points are generated and where in the code the service access points are located. In an embodiment, the code may be executed by different RTEs. In an embodiment, the systems and methods may determine, based on the analysis of the model constraints and the deployment specification, one or more admissible implementations for an RTE service that may be implemented in different ways.

Abstract: According to certain embodiments, a software development system comprises memory and a processor operably coupled to the memory. The memory is operable to store a plurality of code templates, each coded according to syntax of a respective programming language. The processor is configured to receive a user instruction in natural language and perform processing of the user instruction to yield a structured user instruction. The processor is further configured to determine a pre-defined structure that maps to the structured user instruction, select a code template associated with the pre-defined structure that maps to the structured user instruction, and use the selected code template to generate software code that implements functionality of the structured user instruction according to the syntax of the respective programming language of the selected code template.

Abstract: Disclosed herein is a software technology for facilitating an interactive conversational session between a user and a digital conversational character. For instance, in one aspect, the disclosed process may involve two primary phases: (1) an authoring phase that involves a first user accessing a content authoring tool to create a given type of visual conversation application that facilitates interactions between a second user and a digital conversational character in an interactive conversational session, and (2) a rendering phase that involves the second user accessing the created visual conversation application to interact with the digital conversational character in an interactive conversational session. In one implementation, accessing the created visual conversation application may involve detecting an object and identifying information associated with the detected object.

Abstract: Systems and methods for compiling functions into a single entity are disclosed. An execution graph representing dependencies between a plurality of functions is analyzed to identify portions of the graph that include two or more of the plurality of functions used as a combined entity and have a single entry point. The plurality of functions corresponds to a decomposed application. The processing device combines the functions of each of the identified one or more portions of the graph into a composition. For each portion of the graph that includes two or more of the plurality of functions used as a combined entity and has multiple entry points, the processing device determines whether to combine each function providing a subsequent entry point to the portion into a composition with other functions of the portion based at least in part on a network latency and a scale efficiency of the application.

Abstract: Deterministic memory allocation for real-time applications. In an embodiment, bitcode is scanned to detect calls by a memory allocation function to a dummy function. Each call uses parameters comprising an identifier of a memory pool and a size of a data type to be stored in the memory pool. For each detected call, an allocation record, comprising the parameters, is generated. Then, a header file is generated based on the allocation records. The header file may comprise a definition of bucket(s) and a definition of memory pools. Each definition of a memory pool may identify at least one bucket.

Abstract: There is provided methods and apparatus to improve runtime by computer programs at compilation time. A compiler analyzes code to be translated into machine executable instructions to identify overloaded functional units of the target processor, and replaces instructions scheduled on the overloaded functional unit to an idle unit using functionally equivalent operations on the idle unit. The replacement instructions may be taken from an instruction replacement library comprising function calls that implement functionality of a functional unit of the target processor on another functional unit of the target processor.

Abstract: A compiler optimization for structure peeling an array of structures (AOS) into a structure of arrays (SOA) by which a pointer to an array in the original program, is transformed into a tagged index that includes both an array index, and a memory identifier tagging the array index. Once processed by the compiler, each array index is identified by a respective memory identifier, hence if the program instructions call for redefining an array during run time, its array element can still be retrieved by referring to the memory identifier it is tagged with.

Abstract: This disclosure relates generally to creating and managing cloud infrastructure, and more specifically, integrating one or more cloud infrastructure tools for building cloud infrastructures. An example method includes, receiving a request to deploy a cloud infrastructure on a cloud service provider based on a cloud template of the cloud management platform; transmitting configuration instructions associated with a cloud infrastructure tool to a container orchestration platform for execution on one or more containers running on the container orchestration platform to deploy the cloud infrastructure; receiving a deployment state of the cloud infrastructure on the cloud service provider from the container orchestration platform following execution of the configuration instructions; and reporting a status of the cloud infrastructure based on the deployment state.

Abstract: Provided is an optimally deploying an application on a node of a network. An application deployment apparatus 10 is an apparatus that deploys an application in a node N in a network 4, the network 4 including a plurality of the nodes N communicably connected by links L, and includes a deployment determination unit 14 configured to determine, as a deployment destination of the application, a node of the nodes N having a minimum cost including a computation cost of the node N and a communication cost of a links of the links L, and a deployment execution unit 15 configured to distribute the application to the determined node N.

Abstract: One embodiment of the present invention sets forth a technique for managing playback of digital content on two or more different playback devices. A playback device designated as a controller is associated with a playback device designated as a playback target. Association is implemented via a local network discovery protocol. The controller issues commands to the target, which then streams digital content directly from a content server. The controller is able to separately stream related digital content for independent, but synchronized playback. Server mediated operations, such as device activation and application installation, are advantageously enabled by explicit association between the controller and the target.

Abstract: A device includes a memory and a processor. The processor is configured to download a plurality of installation files for different application programs provided on a website at a predetermined download timing, store the plurality of installation files in the memory, recommend, to a user, a function added by installing an application program based on the plurality of installation files stored in the first storage unit at a predetermined recommendation timing that is a different timing from the download timing, and install a respective application program using a respective installation file selected from among the plurality of installation files stored in the first storage unit in response to an instruction from the user based on the recommendation.

Abstract: A computer-implemented method includes: registering, by a computer device, a device to a network; collecting, by the computer device, device data from the device through the network; compiling, by the computer device, training data from the collected device data; training, by the computer device, a machine learning model using the training data; predicting, by the computer device and using the machine learning model, a time when the device will be in an inactive system state; and automatically scheduling, by the computer device and based on the predicting, an application of an update for the time when the device is in the inactive system state.

Abstract: Embodiments of the invention are directed to a system, method, or computer program product for an integrated entity resource distribution device set-up and deliver platform for distribution of devices to an entity for resource acceptance. An entity must be activated and on-boarded to accept resource acceptance and processing. The invention creates a platform for identification of entity needs with respect to resource acceptance devices. With this information the platform generates configured resource acceptance devices for the entity with correct components and sub-components. Furthermore, the system integrate software and firmware in an appropriate sequence onto resource acceptance devices components and sub-components.

Abstract: A storage circuit includes a first storage region, a second storage region, a third storage region, and a fourth storage region. The first storage region stores first firmware data. The second storage region stores second firmware data. The third storage region stores first state data corresponding to the first firmware data. The fourth storage region stores second state data corresponding to the second firmware data. One of the first firmware data and the second firmware data is executed based on the first state data and the second state data. In a situation that the first firmware data is executed, the second firmware data is updated if a firmware updating event occurs.

Abstract: A software update device is configured to control software update of an electronic control unit mounted on a vehicle. The software update device includes: one or more storage devices configured to store first software and second software for downloading update data of the electronic control unit from a server, the first software and the second software being different from each other; and one or more processors configured to download the update data from the server by executing any of the first software and the second software.

Abstract: Embodiments of the present disclosure relate to systems and methods for creating logical groups of packages by tagging individual packages with a tag associated with metadata corresponding to packages that are part of the group. A group of packages may be defined from a plurality of packages that make up an application ecosystem using the tag. A command to perform a first operation of a set of operations performed by the package manager on the group of packages may be provided to a package manager, wherein the command may reference the tag and wherein the package manager is modified to perform each of the set of operations on one or more of the plurality of packages simultaneously. The first operation may be performed by the package manager on the group of packages simultaneously using the metadata to identify each package that is part of the group.

Abstract: Example embodiments facilitate prioritizing the recycling of computing resources, e.g., server-side computing systems and accompanying resources (e.g., non-volatile memory, accompanying firmware, data, etc.) leased by customers in a cloud-based computing environment, whereby computing resources (e.g., non-volatile memory) to be forensically analyzed/inspected, sanitized ,and/or updated are prioritized for recycling based on estimates of when the computing resources are most likely to require recycling, e.g., via background sanitizing and updating. Computing resources that are likely to be recycled first are given priority over computing resources that are more likely to be recycled later. By prioritizing the recycling of computing resources according to embodiments discussed herein, other cloud-based computing resources that are used to implement computing resource recycling can be efficiently allocated and preserved.

Abstract: A versioned schema of a data platform. A process of maintaining a call stack of executing objects of an application package having a versioned schema includes calling, by a first procedure executed by one or more processors, a second procedure of a versioned application instance, and determining, by the first procedure, a version of the second procedure based on a call context. In response to determining that the version of the second procedure is not in the call context, the first procedure determines a current version of the versioned application package adds the current version to the call context as the version of the second procedure.

Abstract: The subject disclosure relates to techniques for updating a bootloader on a embedded device. In some aspects, a process of the disclosed technology can include steps for calculating a digest for an existing bootloader stored on the bootloader memory, determining if the digest for the existing bootloader matches a digest for a target bootloader, and copying the target bootloader to the bootloader memory, if the digest for the existing bootloader does not match the digest for the target bootloader. Systems and computer-readable media are also provided.

Abstract: Systems and methods for implementing changes made to source code of a program at runtime are provided. In particular, a computing device may execute the source code in a runtime environment and detect changes made to the source code at runtime in the runtime environment. In response to detecting the changes, the computing device may determine if the changes were made to a type in the source code identified as reloadable. In response to determining that the changes were made to the type in the source code identified as reloadable, the computing device may create a new version of the type and perform implementation of the changes to the source code at runtime using the new version of the type.

Abstract: An example operation may include one or more of receiving a software update at a transport, performing a first validation of the software update in a first environment, wherein the first environment includes a least amount of potential interactions, and performing a further validation of the software update when the first validation is successful, in a further environment, wherein the further environment includes an amount of potential interactions greater than the first environment.

Abstract: A boot Read-Only Memory (ROM) update method and a boot-up method of an embedded system are provided. The boot Read-Only Memory (ROM) update method of an embedded system including a memory and a ROM. The memory includes a user data area and a boot ROM area that includes a first area and a second area. The ROM copies a first boot code from the boot ROM area during boot-up. The boot ROM update method includes writing a second boot code to the second area in response to a first ROM update command. The second boot code includes a second boot ROM image and a second signature for the second boot ROM image. The method also includes verifying validity of the second signature and, if the second signature is valid, swapping the first area and the second area. The first boot code is disposed in the first area and includes a first boot ROM image and a first signature for the first boot ROM image.

Abstract: Disclosed are systems, methods, and non-transitory computer-readable media for a customizable cloud-based software platform. A customizable cloud-based software platform provides functionality that enables a user (e.g., individual user, organization, etc., that has created an account with the customizable cloud-based software platform) to modify a base version of a cloud-based software application to the specific user's needs. For example, the customizable cloud-based software platform provides a base version of a cloud-based software application that includes a base set of functionalities, settings, user interfaces, etc., which a user may modify to meet the user's specific needs A user may therefore use a client device to interact with the customizable cloud-based software platform to access their customized instance of the cloud-based application.

Abstract: An extensible platform-as-a-service (PaaS) system for use during the software development lifecycle (SDLC) processes of a user application. The extensible PaaS system receives, from a user, values associated with a user application for features exposed in a presented application programming interface (API) to the user. The system displays a set of software modules for during the SDLC processes of the user application. The system receives a selection of software modules for custom configuration from the user. The system generates a set of custom configured software modules for the received selection of software modules. The system generates a set of automatically configured software modules for the remaining software modules. The system uses the custom configured software modules and the automatically configured software modules during the SDLC processes of the user application.

Abstract: Even when one refactoring operation cannot establish a target software structure, an appropriate refactoring operation establishes the target software structure. An improvement proposing device includes: a structure comparator to output, as an improvement object, a difference between a first software structure and a second software structure different in software structure from the first software structure; and an improvement plan examining unit to examine an improvement plan for each improvement portion in the improvement object, the improvement plan being a method for bringing the first software structure closer to the second software structure.

Abstract: A method includes collecting code development data associated with development of code files on a per user basis. A predicted code execution performance score is determined based on weighting one or more developer attributes captured in the code development data on the per user basis, the predicted code execution performance score indicative of a predicted likelihood of a code quality issue, where the one or more developer attributes are based at least in part on personnel data including a level of developer experience and a history of observed development activities of an associated developer from review data. One or more resources of one or more code execution servers associated with execution of selected files are predictively allocated based on the predicted code execution performance score. One or more code execution metrics are captured associated with executing selected files on the one or more code execution servers.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Abstract: A circuit includes a data input that is configured to receive a data word, the data word including at least one operand which is rotated by a number of bits given by a rotation parameter, a first control input that is configured to receive the rotation parameter, a second control input that is configured to receive an indication of an operation to be performed, a first subcircuit that is configured to generate an operation- and rotation-dependent bit mask from the rotation parameter and the indication of the operation to be performed, a second subcircuit which is configured to process the at least one operand as a function of the bit mask and the operation to be performed, wherein the operand and the operation result generated by the processing remain in the rotated state, and a data output which is configured to output the operation result.

Abstract: Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.

Abstract: An apparatus and method for multiplying packed real and imaginary components of complex numbers are described. A processor embodiment includes: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed real and imaginary data elements; a second source register to store a second plurality of packed real and imaginary data elements; and execution circuitry to execute the decoded instruction.

Abstract: A computer system, processor, programming instructions and/or method for managing operations of a gather buffer for a processor core load storage unit. The processor core includes a processing pipeline having one or more execution units for processing unaligned load instructions that executes in two phases to satisfy. A buffer storage element is provided having a plurality of entries for temporarily collecting partial writeback results retrieved from the memory that are associated with first phase accesses for each of a plurality of unaligned load instructions. An associated logic controller device tracks two parts of the unaligned load to be gathered at independent times, wherein said partial result stored at said buffer storage element comprises a first part of an unaligned load. The second phase load access for the same instruction is independently accessed and later merged with first part of the load data at byte granularity to satisfy the load.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: Delivering immediate values by using program counter (PC)-relative load instructions to fetch literal data in processor-based devices is disclosed. In this regard, a processing element (PE) of a processor-based device provides an execution pipeline circuit that comprises an instruction processing portion and a data access portion. Using a literal data access logic circuit, the PE detects a PC-relative load instruction within a fetch window that includes multiple fetched instructions. The PE determines that the PC-relative load instruction can be serviced using literal data that is available to the instruction processing portion of the execution pipeline circuit (e.g., located within the fetch window containing the PC-relative load instruction, or stored in a literal pool buffer), The PE then retrieves the literal data within the instruction processing portion of the execution pipeline circuit, and executes the PC-relative load instruction using the literal data.

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: Processors and methods related to tracking exact convergence to guide the recovery process in response to a mispredicted branch are provided. An example processor includes a pipeline having a frontend and a backend. The processor further includes a state table for maintaining information related to at least a subset of branches corresponding to instructions being processed by the processor. The processor further includes state logic configured to access the state table and track locations of any exact convergence points associated with branches corresponding to the instructions being processed by the processor. The state logic is further configured to identify a first recovery method for recovering from a misprediction associated with a branch if a location of an exact convergence point associated with the branch is determined to be in the frontend of the pipeline, else identify a second recovery method for recovering from the misprediction associated with the branch.

Abstract: A processor includes a processing pipeline, a plurality of result-storage elements, and writeback logic. The processing pipeline is configured to process program operations and to write, to a result storage, up to a predefined maximal number of results of the processed program operations per clock cycle. The result-storage elements are configured to store respective ones of the results. The writeback logic is configured to (i) detect a writeback conflict event in which the processing pipeline produces simultaneous results that exceed the predefined maximal number of results, for writing to the result storage, in a same clock cycle, (ii) in response to detecting the writeback conflict event, to temporarily store at least a given result, from among the simultaneous results, in a given result-storage element, and (iii) to subsequently write the temporarily-stored given result from the given result-storage element to the result storage.

Abstract: Systems and methods for performance benchmarking-based selection of processor for generating graphic primitives. An example method comprises: initializing, by a computer system comprising a plurality of processors of a plurality of processor types, a current value of a graphic primitive parameter; for each processor type of the plurality of processor types, computing a corresponding value of a performance metric by generating, using at least one processor of a currently selected processor type, a corresponding graphic primitive of a specified graphic primitive type, wherein the graphic primitive is characterized by the current value of the graphic primitive parameter; and estimating, based on the computed performance metric values, a threshold value of the graphic primitive parameter.

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

Abstract: Systems and methods are provided for supporting remote management of an IHS (Information Handling System). A first remote management command is received at an IHS. Managed hardware components of the IHS are identified that are configured by the first remote management command. While the first remote management command is pending, a mapping is maintained of the command and the managed hardware components configured by the command. A second remote management command is received that is related to a component of the IHS. Based on the maintained mapping, a determination is made whether the component of the second remote management command is configured by the pending first management command. When the component of the second remote management command is configured by the pending first management command, a notification of the pending first management command is appended to a response to the second management command.

Abstract: In an example, a computing device includes a non-volatile storage device to store a basic input/output system (BIOS) variable. Further, the computing device includes a BIOS. During a boot process of the computing devices, the BIOS may read the BIOS variable from the non-volatile storage device. Further, the BIOS may detect that an application is to be deployed in the computing device based on the BIOS variable. Furthermore, the BIOS may load an application package from the non-volatile storage device into a volatile storage device and build an advanced configuration and power interface (ACPI) data structure with the application package loaded in the volatile storage device. Further, the BIOS may deploy the application using the ACPI data structure.

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

Abstract: Techniques are disclosed for managing dependencies in an orchestration service. A computer-implemented method can include operations performed by a declarative infrastructure provisioner (DIP). In some embodiments, the DIP parses configuration data associated with a computing system and generates a directed acyclic graph (DAG) for booting a first resource. The DAG may specify a dependency of the first resource on a capability of a second resource. The DIP may traverse the DAG and determine, based at least in part on the traversal, that the dependency has been reached. The DIP may publish, to a scheduling process, an indication that the first resource is awaiting availability of the capability of the second resource. In some embodiments, the DIP receives a subsequent indication that the capability is available, regenerates the DAG, and recommences traversal of the DAG. Additional operations for booting the first resource may be performed in accordance with the recommenced traversal.

Abstract: A node that includes data processing unit (DPU) and a processor, where the processor is configured to perform a method for utilizing a data processing unit (DPU), that includes identifying, by the DPU, a processing entity operatively connected to the DPU, receiving processing entity properties from the processing entity, storing the processing entity properties in a processing entity catalog, generating a virtual combined memory space in the processing entity catalog, and providing access to the processing entity catalog to a BIOS.

Abstract: A cloud based network includes a plurality of nodes, each of which include at least one containerized microservice that enables intent-driven operation of the cloud based network. One or more resource controllers, each designated to manage a custom resource, communicate with a master controller of the node to manage operational and configuration states of the node and any microservices containerized within the node. The master enables a user to monitor and automate the management of microservices and the cloud based network as a whole. The containerized microservice architecture allows user customizable rendering of microservices, reconciliation of old and new versions of microservices, and facilitated management of a plurality of nodes.

Abstract: The techniques disclosed herein improve existing systems by providing a system that receives a settings profile associated with a first application. The settings profile is stored. When it is determined that a second application has unconfigured settings, the stored settings profile is accessed and based on the stored settings profile, the unconfigured settings are automatically configured.

Abstract: This application discloses a class loading method and apparatus. The method is applied to a computer device, the computer device includes a target binary file, the target binary file includes a correspondence between class names of a plurality of classes and full information of the plurality of classes, and the class names are in a one-to-one correspondence with the full information of the classes. The method includes: determining a class name of a to-be-loaded class required for running an application program in the computer device; obtaining full information corresponding to the class name of the to-be-loaded class based on the class name of the to-be-loaded class and the correspondence between the class names of the plurality of classes and the full information of the plurality of classes; and running the application program based on the full information corresponding to the class name of the to-be-loaded class.

Abstract: A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.

Abstract: Methods, apparatus and articles of manufacture to provide workflow subscription management in a cloud computing environment are disclosed. Examples disclosed herein cause a graphical user interface associated with a virtual appliance to present a template to create a first workflow subscription, the template including (1) a first input element to specify a workflow to be performed, and (2) a second input element to specify an event topic that is to trigger operation of the workflow, the second input element including a field to specify at least one of (i) whether other workflow subscriptions are to be blocked from an event notification associated with the event topic until the first workflow subscription has acted upon the event notification, or (ii) whether a reply notification is to be sent to a service associated with the event notification after the workflow has completed in response to being triggered based on the event notification.