Abstract: Approaches presented herein enable fault detection. More specifically, implementation code of one or more functions is identified from source code. The implementation code of the one or more functions is converted to corresponding Abstract Syntax Trees (ASTs). The implementation code of the one or more functions is represented as a first plurality of sets of AST paths over the ASTs. Classification results for the one or more functions are generated with a classifier based on the first plurality of sets of AST paths for the implementation code of the one or more functions. Each of the classification results indicates a probability of having at least one fault in a corresponding function of the one or more functions. Fault detection results of the source code are generated based on the classification results.

Abstract: A method of analyzing a performance of a microservices-based application comprises generating a plurality of traces from a plurality of spans associated with the microservices-based application. The method also comprises generating a plurality of data sets each associated with a respective analysis mode of a plurality of analysis modes using the plurality of traces, wherein each analysis mode extracts a different level of detail for analyzing the performance of the services in the application from the plurality of spans. Further, the method comprises selecting, based on a first user query, a first analysis mode from the plurality of analysis modes for generating a response to the first user query. The method also comprises accessing a data set of the plurality of data sets that is associated with the first analysis mode and generating the response to the first user query using the data set associated with the first analysis mode.

Abstract: A scalable test workflow service facilitates management, automated generation and execution of numerous test cases. Test definitions representing tasks to be executed to validate a capability, parameter providers that provide metadata options, and step executors that execute the individual steps of the tasks are all specified. In response to a request to perform a test, an iterative process builds, based on the test definitions and the corresponding parameters, test instances that are executed to obtain the test results. For example, a run tests workflow initiates a test initialization workflow for each test definition. The test initialization workflows call the parameter providers to obtain parameter combinations used to create test instances, and initiate test execution workflows for each parameter combination. Each test execution workflow calls a step executor for each step of the test definition using parameters for the test instance, and returns the results. Results are aggregated and returned.

Abstract: A system for generating synthetic test cases for fuzz testing. One example includes an electronic processor. The electronic processor is configured to pre-process training data, use the training data to train a discriminator DNN to evaluate a test case to determine whether the test case is likely to expose a software vulnerability, and use the discriminator DNN to train a generator DNN to generate a test case that is likely to expose a software vulnerability. The electronic processor uses the discriminator DNN to train the generator DNN by determining whether a test case generated by the generator DNN is likely to expose a software vulnerability and sending a determination of whether the test case generated by the generator DNN is likely to expose a software vulnerability to the generator DNN. The electronic processor is further configured to, when the generator DNN is trained, generate one or more test cases.

Abstract: Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Abstract: Methods, systems, and devices supporting orchestration for automated performance testing are described. A server may orchestrate performance testing for software applications across multiple different test environments. The server may receive a performance test indicating an application to test and a set of test parameters. The server may determine a local or a non-local test environment for running the performance test. The server may deploy the application to the test environment, where the deploying involves deploying a first component of the performance test to a first test artifact in the test environment and deploying a second component of the performance test different from the first component to a second test artifact in the test environment. The server may execute the performance test to obtain a result set, where the executing involves executing multiple performance test components as well as orchestrating results across multiple test artifacts to obtain the result set.

Abstract: Writing data in a storage system that includes a first type of storage device and a second type of storage device, including: selecting, for one or more unprocessed write requests, a target storage device type from the first type of storage device and the second type of storage device; issuing a first group of write requests to the first type of storage device, the first group of write requests addressed to one or more locations selected in dependence upon an expected address translation to be performed by the first type of storage device; and issuing a second group of write requests to the second type of storage device, the second group of write requests addressed to one or more locations selected in dependence upon a layout of memory in the second type of storage device.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more

Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

Abstract: The present technology includes a memory controller that allocates a new buffer memory area in a buffer memory or stores temporarily stored data in the buffer memory into a memory device based on a state of an auxiliary power device that supplies power to the memory device and the memory controller, and a power state of a host.

Abstract: One or more aspects of the present disclosure relate to cache memory management. In embodiments, a global memory of a storage array into one or more cache partitions based on an anticipated activity of one or more input/output (IO) service level (SL) workload volumes can be dynamically partitioned.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

Abstract: An arithmetic processor including a plurality of core groups each including a plurality of cores and a cache unit, a plurality of home agents each including a tag directory and a store command queue and a store command queue. The store command queue enters the received store request to the entry queue in order of reception, the cache unit stores the data of the store request in a data RAM. The store command queue sets a data ownership acquisition flag of the store request to valid when obtaining a data ownership of the store request and issues a top-of-queue notification to the cache control unit when the flag of the top-of-queue entry is valid. In response to the top-of-queue notification, the cache unit update a cache tag to modified state and issue a store request completion notification.

Abstract: Systems and methods that may be used to implement overlapping data caching for object application program interfaces (APIs). A unique identifier may be assigned to each sub-component of an object API request. The unique identifiers may be used to determine if sub-components of one object API request overlaps with a sub-component of a prior different request such that a data response for the prior different request can be retrieved from the cache and used as part of the data response for the current object API request.

Abstract: The present application discloses a cache access method and an associated graph neural network system. The graph neural network processor is used for performing computation upon a graph neural network. The graph neural network is stored in the memory in compressed sparse row format. The method includes: receiving an address corresponding to a node of the graph neural network and a type of the address; in response to the type is one of a first type or a second type, performing lookup by comparing the address with a tag field of a degree lookup table to at least obtain a degree of the node; determining whether the degree is greater than a predetermined value to obtain a determination result; and determining whether to perform lookup on a region of the cache corresponding to the type according to the determination result.

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.

Abstract: A distributed metadata cache for a distributed object store includes a plurality of cache entries, an active-cache-entry set and an unreferenced-cache-entry set. Each cache entry includes information relating to whether at least one input/output (IO) thread is referencing the cache entry and information relating to whether the cache entry is no longer referenced by at least one IO thread. Each cache entry in the active-cache-entry set includes information that indicates that at least one IO thread is actively referencing the cache entry. Each cache entry in the unreferenced-cache-entry set is eligible for eviction from the distributed metadata cache by including information that indicates that the cache entry is no longer actively referenced by an IO thread.

Abstract: Various embodiments enable read buffering in connection with data block transfer on a memory device. For some embodiments, read buffering from a set of cache blocks is enabled during a period of wait time after data is copied (e.g., data is transferred, such as part of a compaction operation) from the set of cache blocks to a set of non-cache blocks. In various embodiments, after the wait time, data stored on the set of cache blocks is erased (e.g., the set of cache blocks is released) and read buffering from the set of cache blocks is disabled.

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Abstract: A method of providing end-to-end encryption for data stored in a storage system, including: receiving a request to read encrypted data from a logical volume of a storage system; decrypting the encrypted data using a decryption key associated with at least one property of the storage system; performing at least one of a data operation to reconstitute the data; encrypting the data using an encryption key associated with at least one property of the data to generate new encrypted data; and providing a response to the request that includes the new encrypted data.

Abstract: Embodiments of systems and methods for managing an Information Handling System (IHS) using a workspace orchestration system are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to, instantiate a first workspace comprising a cache database, the first workspace being instantiated with a first interface that is configured to communicate with a second interface configured in a second workspace administered by the workspace orchestration system. The cache database being accessed by the second workspace using the first interface.

Abstract: Dock-connected peripherals can be enumerated in a preferred order. When a client computing device is connected to a dock, a dock service can report peripherals connected to the dock one-by-one to ensure that each peripheral is enumerated in the preferred order. The preferred order can be defined based on a user's usage of the peripherals including an order of usage, a usage frequency, and a purpose.

Abstract: A user station for a bus system and a method for transmitting a message at different bit rates in a bus system. The user station includes a communication control unit for creating a message for a further user station of the bus system. The communication control unit provides, in the message, a first phase, which is to be transmitted at a first bit rate, and to provide a second phase, which is to be transmitted at a second bit rate, which is faster than the first bit rate. The communication control unit is designed to provide in the message a first predetermined bit pattern for a bit rate switching between the first and second bit rate and to provide a second predetermined bit pattern for a bit rate switching between the second and first bit rate. The second predetermined pattern differs from all other bit patterns in a valid message.

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Abstract: A memory device including memory cells operating according to a first clock signal having a first clock frequency and accessed based on a data access time. The memory device may include a clock shifter circuit for delaying the access commands based on the data access time. The clock shifter circuitry include a shift register circuit and a phase correction circuit. The shift register circuit delays the access commands using a second clock signal having a fraction of the first clock frequency. The phase correction circuit receives the access commands from the shift register circuitry using the fraction of the first clock frequency, delays the access commands based on phase information of the access commands, and outputs the access commands to the memory cells based on the data access time using the first clock frequency.

Abstract: A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.

Abstract: Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202).

Abstract: A system and a method for detecting baseboard management controller (BMC) includes the BMC and a CPLD. The BMC includes a GPIO and configured to drive the GPIO to output a first signal. The CPLD is connected to the GPIO and is configured to determine a status of the BMC by detecting whether the GPIO outputs the first signal. When the CPLD detects that the GPIO is not outputting the first signal, the CPLD determines that the BMC is in an abnormal status; when the CPLD detects that the GPIO is outputting the first signal and a level status of the first signal is switched in a predetermined time, the CPLD determines that the BMC is in a normal status.

Abstract: A marine-type communication device that reads data from a data bus, dynamically creates new data channels for a plurality of operational systems and performs a volatility assessment to determine when to save the data for transmission to a cloud network and when to transmit the data to the cloud network.

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.

Abstract: The methods and systems may provide a scalable round-robin arbiter tree that performs round-robin arbitration for a plurality of requests received from a set of requestors. The round-robin arbiter may stack a plurality of round-robin cells in stages where an output of a first stage of round-robin cells is an input to a next stage of round-robin cells. The round-robin arbiter may transform an arbitration state at each stage of the arbitration and propagate the arbitration state into the next stage for arbitration. The arbitration state from the final stage round-robin cell is fed back to the first stage of the round-robin cells and used in a subsequent arbitration round.

Abstract: According to examples, an apparatus may include a processor that may access an assignment of a component connected to a downstream USB port, from among a plurality of downstream USB ports that are downstream of a display device, to a first physical host device from among a plurality of physical host devices connected to the display device via respective upstream USB ports. The apparatus may bind, based on the assignment, the downstream USB port to a first upstream USB port that connects the first physical host device to the display device. The binding may cause the component to be coupled to the first physical host device. The apparatus facilitates assignment of individual components connected to downstream USB ports to one of a plurality of upstream USB ports.

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

Abstract: A solid state drive having a drive aggregator configured with multiple host interfaces for parallel and/or redundant connections to one or more host systems. The solid state drive has a plurality of component solid state drives connected to the drive aggregator. Each of the component solid state drives has a controller capable of processing commands from host systems. The drive aggregator is configured to receive commands in the host interfaces concurrently and implement the commands received from the host system using the plurality of component solid state drives.

Abstract: The described techniques address deadlocking issues associated with interconnected hardware devices that share bus lines associated with a digital communication interface. A watchdog-based solution is described that may be implemented internally within the interconnected hardware devices or, alternatively, as an external component. The watchdog circuity may monitor a logic state of one or more internal connections of a hardware device and cause one or more portions of the hardware device to reset when a deadlock condition is detected using this internal monitoring.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: A file storage application that processes file operations is communicably connected with a block storage application that processes block operations by establishing multiple communication sessions between the file storage application and the block storage application. Multiple logical volumes provided by the block storage application are exposed to the file storage application over the multiple communication sessions established between the file storage application and the block storage application using a total number of logical paths to the logical volumes that is equivalent to the total number of the logical volumes provided by the block storage application to the file storage application.

Abstract: A system clock is protected by limiting clock changes, change frequency, and calculating skew. System and secure clocks are initialized to a same time. First and second thresholds are set. The first threshold corresponds to an alert and the second threshold corresponds to an action. At a time interval at which the secure clock is to be updated, a skew is calculated between the system and secure clocks, and a cumulative skew is calculated. Upon a determination that the cumulative skew has reached the first threshold, but not the second threshold, the alert is triggered while deletions of files having retention locks that have expired according to the system clock are allowed to continue. Upon a determination that the cumulative skew has reached the second threshold, the action is triggered. The action includes blocking the deletions of files having retention locks that have expired according to the system clock.

Abstract: Snapsets containing snapshots from a group of storage volumes are assigned snapset IDs. The same snapset ID is applied to each snapshot of the snapset, and is a globally unique value within the storage system. The snapset ID is assigned to a snapshot upon creation, and remains the same regardless of creation or deletion of other snapshots on the storage volume. By assigning a snapset ID to each snapshot of the snapset, and maintaining the snapset ID as a constant value as long as the snapshot is maintained on the storage system, it is possible to easily determine which snapshots form a given snapset. Control operations on particular storage groups or across storage groups are implemented by specifying particular actions to be taken on snapsets or snapshots, which are identified using the snapset IDs.