Abstract: A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.

Abstract: An apparatus comprises prefetch circuitry, and a cache having a plurality of entries to store data for access by processing circuitry and blocks of metadata for reference by the prefetch circuitry. The prefetch circuitry can detect one or more access sequences in dependence on training inputs derived from demand accesses processed by the cache in response to memory access operations performed by the processing circuitry. On detecting a given access sequence, this causes an associated given block of metadata providing information indicative of the given access sequence to be stored in a selected entry of the cache. Eviction control circuitry, responsive to a victimisation event, performs an operation to select a victim entry in the cache, the victim entry being selected from one or more candidate victim entries.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing an extended cache to access an object store efficiently. An embodiment operates by executing a database transaction, thereby causing pages to be written from a buffer cache to an extended cache and to an object store. The embodiment determines a transaction type of the database transaction. The transaction type can a read-only transaction or an update transaction. The embodiment determines a phase of the database transaction based on the determined transaction type. The phase can be an execution phase or a commit phase. The embodiment then applies a caching policy to the extended cache for the evicted pages based on the determined transaction type of the database transaction and the determined phase of the database transaction.

Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

Abstract: Described is a data cache with prediction hints for a cache hit. The data cache includes a plurality of cache lines, where a cache line includes a data field, a tag field, and a prediction hint field. The prediction hint field is configured to store a prediction hint which directs alternate behavior for a cache hit against the cache line. The prediction hint field is integrated with the tag field or is integrated with a way predictor field.

Abstract: A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.

Abstract: In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.

Abstract: Systems and methods for high availability distributed data storage are provided. In embodiments, a method includes: receiving, by a remote direct memory access (RDMA) switch operatively coupled to a computing device, a request to access a page of a database; determining, by the RDMA switch, a validation state of the page; determining, by the RDMA switch, a status of the page; updating, by the RDMA switch, the status of the page based on the validation state and the request; and reporting, by the RDMA switch, the validation state.

Abstract: A method and system of translating addresses is disclosed that includes receiving an effective address for translation, providing a processor and a translation buffer where the translation buffer has a plurality of entries, wherein each entry contains a mapping of an effective address directly to a corresponding real address, and information on a corresponding intermediate virtual address. The method and system further include determining whether the translation buffer has an entry matching the effective address, and in response to the translation buffer having an entry with a matching effective address, providing the real address translation from the entry having the matching effective address.

Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.

Abstract: A system is provided. The system includes a solid state storage including a plurality of banks, a first controller that directs one or more commands to a queue of a set of a plurality of queues, and a second controller configured to receive the one or more commands from the plurality of queues. The one or more commands are separated into the set of the plurality of queues based on a command type of each command of the one or more commands, and each set of the plurality of queues includes a first queue configured to store management commands and a second queue configured to store other commands. Each bank of the plurality of banks corresponds to a different set of the plurality of queues. The second controller is configured to generate subcommands based on the commands and direct the subcommands to a bank of the solid state storage.

Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.

Abstract: A data storage device includes: a housing integrating a control logic, a data protection logic, and a non-volatile storage; and a network interface connector integrated to the housing and is configured to be directly inserted into a network switch. The control logic is configured to store a vehicle data including a video stream in the non-volatile storage. The video stream is received from a video camera that is connected to the network switch. The data protection logic is configured to detect a vehicle event and change an operating mode of the data storage device to a read-only mode prohibiting the vehicle data stored in the non-volatile storage from being erased or tampered.

Abstract: A secure processing system includes a memory having a secure partition and a non-secure partition, a neural network processing unit (NPU) configured to initiate transactions with the memory, and a memory protection unit (MPU) configured to filter the transactions. Each of the transactions includes at least an address of the memory to be accessed, one of a plurality of first master identifiers (IDs) associated with the NPU, and security information indicating whether the NPU is in a secure state or a non-secure state when the transaction is initiated. The MPU is to selectively deny access to the secure partition of the memory based at least in part on the memory address, the first master ID, and the security information associated with each of the transactions.

Abstract: A method for creating a computer macro, the computer macro being executed on a computer, the computer including a processor, a display screen, a peripheral device, and a memory accessible by the processor, peripheral device, the method comprising: detecting, by a computer driver being at least partially resident in the memory, a computer program being at least partially resident in the memory to be executed in the computer; assigning, by the computer driver, at least one computer macro relating to the detected computer program to a key and/or button on the peripheral device; assigning, by the computer driver, a computer macro symbol relating to the assigned computer macro; storing, in the memory, the computer macro, the key and/or button on the peripheral device assigned to the computer macro and/or the assigned computer macro symbol; displaying, on the display screen via the computer driver, an on-screen-display, OSD, wherein the OSD is configured to display the assigned stored computer macro symbol and a re

Abstract: Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

Abstract: A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.

Abstract: Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.

Abstract: Waveform circuitry and related apparatuses and methods are disclosed. An apparatus includes a memory device to store waveform data corresponding to a waveform, a processor, and a waveform circuitry to autonomously pre-process the waveform data independently from the processor and provide the pre-processed waveform data to one or more peripheral devices. A pre-processed waveform corresponding to the pre-processed waveform is data different from the waveform.

Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

Abstract: In a digital communication system, a master device and a number of slave devices are coupled in communication with the master device over a shared data communication bus. During an address assignment procedure, the master device assigns different respective dynamic addresses to the slave devices in order to address the slave devices for data communication; during the address assignment procedure, the slave devices are arranged in a daisy-chain configuration, wherein each slave device has a daisy-chain input and a daisy-chain output, the daisy-chain input of a slave device being coupled to the daisy-chain output of a previous slave device in the daisy chain configuration, the daisy-chain input of a first slave device being coupled to a daisy-chain enabling output of the master device; in particular, the master device is configured to assign the respective dynamic addresses to the slave devices based on their arrangement in the daisy-chain configuration.

Abstract: An all-in-one computer includes a display, a Universal Serial Bus (USB) Type-C port, a plurality of USB Type-A ports, a USB hub, a demultiplexer, and a Power Delivery (PD) controller. The USB hub is coupled to the plurality of USB Type-A ports. The demultiplexer is coupled between the display, the USB Type-C port, and the USB hub. The PD controller is to control the demultiplexer and the USB hub to pass a display signal input to the USB Type-C port to the display and pass signals input to the USB hub from the plurality of USB Type-A ports to the USB Type-C port with a computing device coupled to the USB Type-C port.

Abstract: Traditionally, servers are interconnected inside a data center using regular network cards. It is desired that high-available network-attached storage arrays have the feature of non-disruptive upgrade (NDU) for software and firmware, while one or more applications are still running IO. With the emergence of SmartNICs, there are many functions available now to SmartNIC that may enhance server and entire solution capabilities. Since SmartNIC is a new emerging technology, there are no adequate solutions currently for NDU while running I/O. The present patent document discloses embodiments for upgrading the SmartNIC software without disruption to the host applications. A shared namespace may be implemented inside an emulated NVMe/PCIe device, such as a data processing unit (DPU) or infrastructure processing unit (IPU), such that multiple instances may be enabled to run both old and new target emulation SPDK-based software together using multiple paths to achieve SmartNIC storage NDU.

Abstract: An Information Handling System (IHS) includes multiple hardware devices, and a Baseboard Management Controller (BMC) in communication with the hardware devices. The BMC includes executable code to cause the BMC to receive a message associated with a non-registered hardware device that is not registered to be managed by the BMC in which the message formatted according to a native protocol of the BMC. The code further causes the code to transmit the message to a device plugin associated with the non-registered hardware device in which the device plugin comprises custom instructions that, upon execution by a system processor, cause the IHS to convert the message into a protocol associated with the non-registered hardware device, and forward the converted message to the non-registered hardware device using the protocol of the non-registered hardware device.

Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: A method, a system, and a server for monitoring status of SSD applied in the server allows a volume management device which has been disabled because of conflict to be used to maintain unchanged information of power indicating control bit when an SSD is unplugged. The unchanged information of power indicating control bit is transmitted to a CPLD and decoder information is obtained from the CPLD. Position of the SSD in the register is set according to the decoder information.

Abstract: Please amend the abstract of the specification as follows: Disclosed is a method for configuring an MMIOH base address of a server system. The method includes: when the server system is performing a power-on self-test, detecting a total capacity of all memories in the server system, and determining a minimum MMIOH base address of the server system according to an MMIO specification and the total capacity; if a target MMIOH base address range corresponding to a target PCIE device configured in the server system might be calculated according to a whitelist, and the minimum MMIOH base address is within the target MMIOH base address range, determining that the base address is the MMIOH base address of the server system, and storing the base address in a BIOS of the server system.

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

Abstract: The present disclosure provides a data transmission method and device. The data transmission method is used for transmitting data between an advanced reduced instruction set computing machine (ARM) and a field programmable logic gate array (FPGA) via an Inter-Integrated Circuit (IIC) bus, comprising the following steps: receiving, by the FPGA, communication data transmitted by the ARM via the IIC bus, wherein the communication data comprises first address data, first content data and N second content data, N being an integer greater than 0, the first content data and the N second content data being arranged in sequence, and the first address data being address data corresponding to the first content data; and generating, by the FPGA, second address data corresponding to each of the second content data according to the sequence of the N second content data and the first address data.

Abstract: An electronic device connectable to a network interface device having a plurality of signal lanes may include a first computing device, a second computing device, and an interface to connect the first computing device to a first subset of signal lanes of the plurality of data lanes of the network interface device and connect the second computing device to a second subset of data lanes of the plurality of data lanes of the network computing device.

Abstract: A method for Serial Peripheral Interface (SPI) operating-mode synchronization between an SPI host and an SPI device, which communicate over an SPI bus, includes predefining, in the SPI device, one or more values on the SPI bus as indicative of lack of synchronization of an SPI operating mode between the SPI host and the SPI device. Re-synchronization of the SPI operating mode is initiated in response to receiving any of the predefined values in the SPI device.

Abstract: The present disclosure provides a data transmission method and device for a network on chip and an electronic apparatus. The method includes: receiving, by a second network node, a first data packet sent by a first network node, the first data packet including first identification information and a data packet payload; determining, by the second network node, valid transmission information and second identification information corresponding to the valid transmission information according to the first identification information; determining, by the second network node, a second data packet according to the second identification information and the data packet payload; and sending, by the second network node, the second data packet according to the valid transmission information.

Abstract: An apparatus, a method and a non-transitory computer readable medium are described herein related to extracting SAP archive data on a non-original system. In this way a user may extract business data from any ADK-format archive file in isolation, independent of the original system and without any accompanying metadata. A cloud-based on-demand distributed architecture with a plurality of virtualized SAP Netweaver Application Servers ABAP may speed up the extraction process from ADK-format files by an arbitrary order of magnitude.

Abstract: A system and method for managing files on multiple storage devices, such as USB sticks. The system includes a hub that has multiple input ports for multiple storage devices, wherein has a unique code visually presented next to the respective port. The system can assign a barcode label to each storage device which can be printed and pasted on the respective memory device. The system further scans the files on each of the multiple storage devices to generate a master index based on the unique identification code for each storage device.

Abstract: Disclosed are a medical device and a data management method therefor. The data management method includes: receiving an instruction for selecting a locking rule to determine a target locking rule, wherein the target locking rule is used for screening monitoring data so as to carry out locking; under the trigger of a first trigger condition, screening the monitoring data according to the target locking rule, and locking the screened monitoring data; and under the trigger of a second trigger condition, selectively deleting monitoring data that is not locked. An operator can selectively lock the monitoring data by selecting the locking rule, thereby avoiding the deletion of monitoring data needing to be retained, and facilitating the management of the monitoring data.

Abstract: A method is used in managing truncation of files of file systems. A request is received to delete a portion of a file of a file system. The file system includes a plurality of files. Metadata of the file is evaluated for determining a number of file system blocks associated with the portion of the file that are available for de-allocation. Storage space associated with the file system blocks is reported as available storage space to a user of the file.

Abstract: Database systems and related customization methods are provided. One exemplary method of modifying a database to support a new functionality involves receiving user input indicative of the new functionality from a client device coupled to a network, identifying existing customizations associated with a user of the client device in the database, determining a plurality of different solutions for implementing the new functionality based at least in part on the existing customizations associated with the user, providing a graphical user interface display at the client device including graphical indicia of the plurality of different solutions for implementing the new functionality, and in response to receiving indication of a selected solution of the plurality of different solutions from the client device, automatically instantiating a new customization corresponding to the selected solution in the database.

Abstract: In an approach to improve file recall between storage devices by optimizing file recall for multiple users. Embodiments of the present invention obtain one or more similarities among one or more users based on one or more usage points and divide the one or more users into a plurality of clusters based on a content of the one or more usage points. Further, embodiments select a cluster from the plurality of clusters based on cluster importance, and select the content used by more than a predetermined percentage of the weighted users pertaining to the selected cluster as an automated recall subject. Additionally, embodiments recal one or more selected content from a secondary storage device to a primary storage device.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. The metadata is grouped into buckets. Each bucket is stored in a group of computing devices. However, only the leader of the group is able to directly access a particular bucket at any given time.

Abstract: The subject technology may be implemented by a device that includes at least one processor configured to encrypt a data object based at least in part on an encryption key. The at least one processor may be further configured to sign the encrypted data object with a private key and transmit the signed encrypted data object to a server for retrieval by another device. The at least one processor may be further configured to generate a sharing object corresponding to the data object, wherein the sharing object includes an encryption key and a public key that corresponds to the private key. The at least one processor may be further configured to encrypt the sharing object using a key of the other device and transmit, over a secure channel, the encrypted sharing object to the other device for subsequent retrieval and verification of the signed data object from the server.

Abstract: Methods and systems implement local file systems of computing nodes which translate random-access read and random-access write operation calls to append-based operation calls in accordance with a distributed file system (“DFS”) implemented across storage nodes of a cloud network. Computer-executable applications running on the computing nodes may generate kernel-level read and write system calls by application programming interfaces (“APIs”) such as the Portable Operating System Interface (“POSIX”) standard, to a local file system. The local file system may translate these read and write system calls to file operations at a DFS implementing an append-only file system, as well as perform storage reclamation upon the DFS periodically and/or upon storage thresholds being exceeded.

Abstract: Disclosed herein are various embodiments of a location data processing system. An embodiment operates by configuring a column of a table to store location-based data across a plurality of different coordinate systems. The location-based data to be stored in the configured column is received. The received location-based data is divided into a plurality of fragments, including a first fragment comprising a plurality of data entries. A first data entry in the first fragment includes a coordinate specification including metadata indicating how to evaluate corresponding location-based data of a first coordinate system represented by the first data entry. A query for data from the first fragment is received. The plurality of data entries of the first fragment are evaluated based on the coordinate specification to identify data that satisfies the query. The data is returned responsive to the query.

Abstract: According to one embodiment, a data virtualization apparatus includes a memory and a processor. The processor is configured to acquire first schema information including a first table name of a first source table managed in a first data source, and second schema information including a second table name of a second source table managed in a second data source, convert the first table name into a third table name, and convert the second table name into a third table name, and register first table correspondence information including the first table name and the third table name in the memory, and register second table correspondence information including the second table name and the third table name in the memory.

Abstract: Embodiments include systems and methods for performing data migration using database consolidation. Information and parameters about a plurality of source databases from a source system can be stored, the parameters including a location, a security zone, and processor information for the source databases. Each of the plurality of source databases can be classified to one of a plurality of predetermined database sizes based on the stored information and parameters, wherein the classifying is at least based on the processor information. The classified source databases can be mapped to target database hardware based on the classified sizes and the stored parameters, wherein the target database hardware is segmented into containers that are defined by one or more of the parameters. Data from the source databases can be migrated to the target database hardware based on the mappings.

Abstract: A method for facilitating automated synchronous data migration in live databases is disclosed. The method includes parsing a source database to identify characteristics, the characteristics corresponding to data tables in the source database; categorizing the data tables into groups based on the identified characteristics; validating the data tables in the groups by performing several tests; copying the groups to a target database based on a result of the validating; reviewing the copied groups to detect errors; and automatically initiating corrective actions in response to the detected errors. Additionally, the method further includes receiving new data sets from an application for persistence in the source database, the source database corresponding to a live database; generating duplicate data sets that correspond to the new data sets; and synchronously persisting, in real-time, the new data sets in the source database and the duplicate data sets in the target database.

Abstract: The present disclosure comprises systems and methods to mine association rules from a dataset provided in the input. This comprises methodologies for optimizing the dataset for efficient computation of association rules, other than methodologies for handling partially true data. Moreover, it includes methodologies for evaluating the mining process automatically and removing uninteresting rules. In addition, it includes methodologies for integrating experts in the evaluation of the rules. Finally, methodologies to automatically detect outliers, correct outliers, update truth values and complete missing data in the original dataset. The overall methodology is completely automated and provides numerous tuning parameters to fit most of the use cases, including a default value for each of the tuning parameters to simplify its usage.