Abstract: Examples described herein relate to prioritizing read input/output (IO) queues in non-volatile memory express (NVME) storage devices. An NVME controller includes a host port, which may be associated with a host and communicate with NVME storage devices. A utilization time of the host port is determined. In response to determining that the utilization time of the host port is below a host port utilization threshold, the NVME controller may create a candidate list of NVME storage devices based on utilizations, throughputs, busy time periods, and IO request completions of the NVME storage devices. For each NVME storage device included in the candidate list, a number of read requests in a read IO queue at the NVME storage device may be determined. A priority rank may be assigned to the read IO queue at each NVME storage device based on the number of read requests in that read IO queue.

Abstract: A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Abstract: Systems and methods are described for smoothing-out latency of IO operations processed by a distributed storage system. In some examples, latency is distributed among IO operations to more evenly spread processing of the IO operations over an IO processing interval. A target latency for IO operations for a volume of a distributed storage system is periodically calculated each sample period based on the number of IO operations to be processed during the next IO processing interval for the volume. As IO operations are received for the volume, a latency may be associated with the IO operation based on the target latency and the IO operation may be queued or synchronously processed as appropriate. Responsive to expiration of a time period that is based on at time at which a given IO operation at the head of the queue was received and the assigned latency, the given IO operation is dequeued and processed.

Abstract: Methods, systems, and devices for configurable verify level are described. A host device may determine a target level of reliability for a set of data stored in a memory device. The host device may transmit, to the memory device, a command indicating the target level of reliability and a request to perform one or more error management operations for the set of data based on or in response to the target level of reliability. The memory device may determine the target level of reliability and the corresponding error management operations based on or in response to the command. The memory device may perform the error management operations for the set of data. The memory device may transmit, to the host device, an indication of a level of reliability of the set of data based on or in response to the command and performing the set of error management operations.

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A memory system includes a plurality of non-volatile memory chips and a controller configured to communicate with a host and control the plurality of non-volatile memory chips. The controller is configured to write a data frame that includes write data and a first parity for error detection and correction of the write data into first memory chips of the non-volatile memory chips in a distributed manner. The first memory chips includes N (N is a natural number of two or more) memory chips. The controller is configured to write a second parity for restoring data stored in one of the N first memory chips using data read from the other N?1 of the N first memory chips, into a second memory chip of the non-volatile memory chips that is different from any of the first memory chips.

Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

Abstract: Integrated circuit device having a processor module (2) in communication with a cache memory module (3, 4), and one or more memory control modules (6, 8, 10) each arranged to interface with an associated storage memory unit (5, 7, 9). An authentication module (15) is provided in communication with the memory control modules (6, 8, 10) and the cache memory modules (3, 4). The authentication module (15) is arranged to generate and store a hardware based secure key, read a predetermined set of data from the associated storage memory units (5, 7, 9), and an associated stored hash value, calculate a hash value of the predetermined set of data using the hardware based secure key; and store the predetermined set of data in the cache memory module (3, 4) only if the calculated hash value corresponds to the associated stored hash value.

Abstract: A disk device includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to receive, from a host, a key setting request that includes a cryptographic key, a key ID thereof, and tag information of the cryptographic key and generate generation information of the cryptographic key. The controller is also configured to store a first entry including the tag information, the cryptographic key, and the generation information associated with each other in the volatile memory, and store a second entry including the key ID and the generation information associated with each other in the nonvolatile memory.

Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.

Abstract: Protecting sensitive data in snapshots, including: creating a transformed snapshot portion by applying a transformation specified in an access policy to one or more data objects contained within the portion of the stored snapshot, wherein the stored snapshot is a copy of data in a storage system at a particular point in time prior to a request to access the snapshot; and providing access to the transformed snapshot portion.

Abstract: Systems, apparatus and methods are provided for low temperature management of a storage system. An apparatus may include a temperature sensor to generate a temperature reading, a timer configured with a time interval, a backup battery, one or more non-volatile memory (NVM) devices and a storage controller. The storage controller may be configured to: maintain a standby mode for low temperature management until a host electronic system has been turned off, start the timer and check the temperature reading when the host electronic system is turned off, determine that the temperature reading is below a temperature threshold, set the time interval based on the temperature reading, receive an interrupt from the timer when the timer counts to the time Interval, and perform low-temperature management operations for data stored in the one or more NVM devices using power supplied by the backup battery.

Abstract: A method for determining the memory power consumption includes: receiving a memory control command and controlling an analog memory to enter different working stages according to the memory control command (S410); acquiring an original current change curve of the analog memory in different working stages (S420); determining a target time period corresponding to a target working stage according to a time sequence of the memory control command (S430); intercepting a stage current change curve corresponding to the target working stage from the original current change curve according to the target time period to obtain a target current change curve (S440); selecting target performance parameters from a memory performance parameter table according to the target working stage (S450); and determining the power consumption of the memory according to the target performance parameters and the target current change curve (S460).

Abstract: A storage system, blades, removable modules, and method of configuring a storage system are described. The storage system has blades with computing resources and storage resources. At least one of the blades has, or has added, one or more removable modules.

Abstract: A memory system includes a memory device including a plurality of memory blocks, each memory block including memory cells capable of storing multi-bit data, and a controller configured to allocate the plurality of memory blocks for plural zoned namespaces input from an external device and access a memory block allocated for one of the plural zoned namespaces which is input along with a data input/output request. In response to a first request input from the external device, the controller adjusts a number of bits of data stored in a memory cell included in a memory block, which is allocated for at least one zoned namespace among the plural zoned namespaces, and fixes a storage capacity of the at least one zoned namespace.

Abstract: Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions.

Abstract: Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.

Abstract: Disclosed is an operating method of a storage controller communicating with a host and memory regions, which includes receiving a write request for a first memory region of the memory regions from the host, determining the first memory region as unavailable, based on a status information set, generating redirection information indicating that a second memory region of the memory regions is selected instead of the first memory region, performing a write operation in the second memory region based on the redirection information, updating status information of the second memory region in the status information set based on the write operation, outputting redirection result information indicating that write data of the write request are processed in the second memory region, to the host, and receiving a read request corresponding to the write data and including information of the second memory region from the host.

Abstract: A system and method for updating a configuration of a host system so that the memory sub-system of the host system emulates performance characteristics of a target memory sub-system. An example system includes a memory sub-system; and a processor, operatively coupled with the memory sub-system, to perform operations comprising receiving a request to emulate a characteristic of a target memory sub-system, identifying a candidate configuration that generates a load on a memory sub-system of a host system to decrease a characteristics of the memory sub-system of the host system, and updating a configuration of the host system based at least on the candidate configuration, wherein the updated configuration changes the memory sub-system of the host system to emulate the characteristic of the target memory sub-system.

Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.

Abstract: The present disclosure generally relates to improving programming to data storage devices, such as solid state drives (SSDs). A first memory device has a first XOR element and a second memory device has a second XOR element. The ratio of the first XOR element to the capacity of the first memory device is substantially smaller than the ratio of the second XOR element to the capacity of the second memory device. A read verify operation to find program failures is executed on either a wordline to wordline basis, an erase block to erase block basis, or both a wordline to wordline basis and an erase block to erase block basis. Because the program failures are found and fixed prior to programming to the second memory device, the second XOR element may be decreased substantially.

Abstract: A resource allocation method and a storage device are provided. The storage device includes a disk enclosure and a plurality of controllers. Each controller includes a plurality of processors, each processor includes a plurality of processor cores, the plurality of controllers are separately coupled to the disk enclosure including a plurality of hard disks. The plurality of processors are configured to provide computing resources. The plurality of hard disks are configured to provide storage space. Logical addresses corresponding to the storage space are classified into several address segment sets, each address segment set includes one or more address segments, some of the computing resources are allocated to each address segment set, and are used to execute a data access request for accessing an address segment comprised in the address segment set. Computing resources used to process different address segment sets are from different processors or from different processor cores.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.

Abstract: Techniques are provided for journal replay optimization. A distributed storage architecture can implement a journal within memory for logging write operations into log records. Latency of executing the write operations is improved because the write operations can be responded back to clients as complete once logged within the journal without having to store the data to higher latency disk storage. If there is a failure, then a replay process is performed to replay the write operations logged within the journal in order to bring a file system up-to-date. The time to complete the replay of the write operations is significantly reduced by caching metadata (e.g., indirect blocks, checksums, buftree identifiers, file block numbers, and consistency point counts) directly into log records. Replay can quickly access this metadata for replaying the write operations because the metadata does not need to be retrieved from the higher latency disk storage into memory.

Abstract: Techniques are provided for data management across a persistent memory tier and a file system tier. A block within a persistent memory tier of a node is determined to have up-to-date data compared to a corresponding block within a file system tier of the node. The corresponding block may be marked as a dirty block within the file system tier. Location information of a location of the block within the persistent memory tier is encoded into a container associated with the corresponding block. In response to receiving a read operation, the location information is obtained from the container. The up-to-date data is retrieved from the block within the persistent memory tier using the location information for processing the read operation.

Abstract: Systems and methods for recording information at a granular level; checking and verifying that data is used and processed is consistent with an entity's internal policies and/or external regulations; and producing reports to authorized users (e.g., individuals and organizations) with information are provided. The system and methods capture required data in an immutable fashion so that users outside of an entity (e.g., public, third parties) can check and audit that internal policies and other regulatory policies and frameworks are followed.

Abstract: A method, computer program product, and computer system for maintaining a back pointer from a physical layer block (PLB) to a virtual layer block (VLB) in a multi-level hierarchical file system. A generation number may be maintained in the VLB, wherein the generation number may indicate when data is moved from the PLB to another PLB. An object may be reconstructed in the multi-level hierarchical file system based upon, at least in part, at least one of the back pointer and the generation number.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

Abstract: The disclosure provides a method and for cloud service migration. The method comprises: obtaining a migration request related to a cloud service hosted in a source cluster, the migration request comprising a scheduled migration time to migrate the cloud service from the source cluster to a target cluster; migrating, based on the scheduled migration time, disk data associated with an original instance of the cloud service to a disk for servicing a new instance of the cloud service instantiated in the target cluster, the migration of the disk data being performed based on a migration priority order of the disk data; and configuring a data operation of the cloud service for a disk for servicing the original instance as a data operation for the disk for servicing the new instance.

Abstract: A storage system includes a management node and multiple storage nodes. Each storage node includes a first storage device of a first type (e.g., DRAM) and a second storage device of a second type (e.g., SCM), and a performance level of the first storage device is higher than the second storage device. The management node creates a globe cache including a first tier comprising the first storage device in each storage node, and a second tier comprising the second storage device in each storage node. The first tier is for storing data with a high access frequency, and the second tier is for storing data with a low access frequency. The management node monitors an access frequency of target data stored in the first tier. When the access frequency of the target data is lower than a threshold, the management node instructs the first storage node to migrate the target data from the first tier to the second tier of the globe cache.

Abstract: A volume to which a storage function is applied is migrated without copying data written to a volume as a migration object between computers while maintaining functionality of the storage function. A plurality of computers are accessibly connected to each of one or more physical storage devices. Each computer migrates ownership of the volume as the migration object to a computer as a destination. When the migration object volume from a first computer to a second computer is an owner volume to which a storage function is applied, the storage function requiring control data for I/O of data, the control data being metadata other than domain mapping data (indicating a relationship between a volume region and a storage region and being metadata for the owner volume), in place of or in addition to the domain mapping data.

Abstract: Disclosed are various embodiments for garbage collection for object-based storage systems. A first set of objects stored by an object storage service that have been accessed within a previously defined date range is identified. Then, a second set of objects stored by the object storage service is identified based at least in part on a relationship to one or more objects in the first set of objects. Next, a third set of objects stored by the object storage service that have been created prior to a predefined date is identified. Then, a subset of objects which are members of the third set of objects and not members of the first set of objects or the second set of objects is identified. Finally, a retention action is performed on individual members of the subset of objects based at least in part on a retention policy.

Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

Abstract: A memory system includes a memory device, a system memory, and a controller. The memory device includes a page storing a first chunk including first user data and first meta data and a second chunk including second user data and second meta data. The system memory stores an address map table for a physical address of the page in which the first chunk and the second chunk are stored and a logical address mapped to the physical address. The controller is configured to perform a read operation of the page by recovering the first meta data using the physical address of the first chunk and the address map table, and outputting the second user data using the second meta data of the second chunk on which an error correction operation has passed, when an error correction operation on the first chunk has failed.

Abstract: Disclosed is a method for data processing applied to a solid state drive, a computer device and a computer-readable storage medium. The method includes acquiring an interface protocol command received by the solid state drive. The method also includes parsing the interface protocol command to obtain I/O information from the interface protocol command. The I/O information includes at least an I/O timestamp, an I/O type, and an I/O size. The method further includes invoking machine learning based on the I/O information to predict I/O information of a first future time period, so that a processor of the solid state drive is configured to proactively execute management functions according to the prediction results.

Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.

Abstract: A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Abstract: A time-division memory control device controls a content addressable memory (CAM) cell array of a CAM in a time-division manner and thereby reduces a peak current and mitigates electromigration and voltage variation problems. The time-division memory control device includes a time-division controller and a peripheral circuit. In a search and compare operation, the time-division controller outputs a first group of control signals at a first time point according to a system clock, and outputs a second group of control signals at a second time point later than the first time point. The peripheral circuit includes: a first group of circuits cooperating with a first group of CAM cells of the CAM cell array according to the first group of control signals; and a second group of circuits cooperating with a second group of CAM cells of the CAM cell array according to the second group of control signals.

Abstract: Example embodiments employ a selective memory swapping system for selectively placing non-volatile memory devices of a computer system offline, e.g., for background updating, and online, for use by a computer system, whereby the background updating process includes a mechanism for performing forensics analysis and updating of offline memory devices while an alternate memory device is usable by a user of the first computer system.

Abstract: An electronics assembly including a plurality of midplanes positioned between and coupled to a plurality of electronic components at one side of the plurality of midplanes and at least one electronic component at an opposite side of the plurality of midplanes in a manner so that the midplanes are vertically oriented in parallel relative to each other so as to define spaces therebetween. The midplanes each include electrical traces configured to send signals among and between the plurality of electronic components at the one side of the midplanes and the at least one electronic component at the opposite side of the midplanes.

Abstract: Methods, systems, and devices for memory operations are described. Data for a set of commands associated with a barrier command may be written to a buffer. Based on a portion of the data to be flushed from the buffer, a determination may be made as to whether to update an indication of a last barrier command for which all of the associated data has been written to a memory device. Based on whether the indication of the last barrier command is updated, a flushing operation may be performed that transfers the portion of the data from the buffer to a memory device. During a recovery operation, the portion of the data stored in the memory device may be validated based on determining that the barrier command is associated with the portion of the data and on updating the indication of the last barrier command to indicate the barrier command.

Abstract: A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.

Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.

Abstract: Providing scalable and reliable container-based storage services, including: deploying a containerized storage controller on a first node among of plurality of nodes operable to support execution of the containerized storage controller; associating a dataset stored in backing storage accessible by the first node with one or more virtualized volumes presented by the containerized storage controller; and providing, by the containerized storage controller to one or more client hosts, a set of storage services for the one or more virtualized volumes.

Abstract: Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include writing a memory object to a first memory device of a first type of memory medium. The example method can include determining that a size of the memory object meets or exceeds a threshold data size. The example method can include writing the memory object to a second memory device that comprises a second type of memory medium different than the first type. The first memory medium can be a non-volatile memory comprising phase-change memory or resistive random access memory (RAM) and the second memory medium can be NAND Flash or NOR Flash.

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller for storing a first read command generated in response to a read request and a first physical address in the first read command queue; and a command schedule controller for searching for a first physical address group including at least one second physical address including a page number equal to that of the physical address among the physical addresses stored in the first read command queue and the first physical address, in response to a scheduling event signal provided from the command generation controller.