Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

Abstract: In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of data—one of 2M columns of data within the page buffer, where M<N—with that larger column of data output via the fixed-width data interface over a second burst interval longer than the first burst interval.

Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

Abstract: A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.

Abstract: Embodiments of the disclosure provide a circuit structure and related method to provide a radiation resistant memory cell. A circuit structure may include a first latch having an input node and an output node. A second latch has an input node and an output node, in which the output node of the second latch is coupled to the input node of the first latch, and the input node of the second latch is coupled to the output node of the first latch. A read/write (R/W) circuit includes a plurality of transistors coupling a word line, a bit line, and an inverted bit line to at least two outputs. One of the at least two outputs is coupled to the input node of the first latch and another of the outputs is coupled to the input node of the second latch.

Abstract: A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven.

Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

Abstract: A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Abstract: A semiconductor memory device includes a first memory string including a first select transistor, a first memory cell, a first select element, a second memory cell, and a second select element in series, a second memory string including a second select transistor, a third memory cell, a third select element, a fourth memory cell, and a fourth select element in series, and a control circuit. The control circuit is configured to set the second select transistor to an on state, and to set the third select element and the fourth select element to an off state, when reading data of the first memory cell.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: The disclosure provides an erase method for a memory device. In the method, during a time period, a first positive voltage is applied to a body portion of a memory cell string of the memory device. The memory cell string includes memory cell transistors and select transistors connected in series. A second positive voltage is applied to a bit line signal of the memory cell string. A third positive voltage is applied to a first top select gate signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the bit line signal through the first top select transistor. A ground level voltage or a fourth positive voltage is applied to a word line signal of the memory cell transistors. Both the third and fourth positive voltages are less than the second positive voltage.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A data output control circuit includes a dividing circuit, a timing signal generating circuit and a control signal generating circuit. The dividing circuit divides read enable signals to generate multiple phase clock signals. The timing signal generating circuit generates a plurality of timing signals based on warming-up cycle information and the multiple phase clock signals. The control signal generating circuit generates data output control signals based on the multiple phase clock signals and the plurality of timing signals.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first signal line including a first part and a second part, a second signal line including a third part and a fourth part, a first inverter, a second inverter, and a control circuit. A first signal is input to the first part in a first period. A second signal is input to the third part in a second period. The first inverter outputs, to the second part, a first inverted signal obtained such that a logic of the first signal is inverted. The second inverter outputs, to the fourth part, a second inverted signal obtained such that a logic of the second signal is inverted. The control circuit brings the second signal line into a floating state in the first period, and brings the first signal line into a floating state in the second period.

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including causing a first current to be obtained with respect to cells of a wordline maintained at a first voltage, determining that the cells are at a second voltage lower than the first voltage, in response to determining that the cells are the second voltage, causing a voltage ramp down process to be initiated, causing a second current to be sampled with respect to the cells during the voltage ramp down process, and detecting an existence of charge loss by determining whether the second current satisfies a threshold condition in view of the first current.

Abstract: A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the different data state comprises determining if the memory cells of the other planes that are targeted for programming to the different data state have successfully completed verification of programming for the different data state. The programming process is stopped for those planes that fail the test.

Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.

Abstract: An operating method of a memory device, comprises: a program operation of applying a program voltage to a selected word line to program selected memory cells connected to the selected word line, a first verification operation of applying a first verification voltage to the selected word line and applying a first verification pass voltage to unselected word lines to verify a first program state of the selected memory cells, and a second verification operation of applying a second verification voltage to the selected word line and applying a second verification pass voltage to the unselected word lines to verify a second program state higher than the first program state.

Abstract: An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.

Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.

Abstract: In a method of writing data in a nonvolatile memory device, a write command, a write address and write data to be programmed are received. Offset information representing a verification level is received. The offset information is provided when the write data corresponds to a distribution deterioration pattern by checking an input/output (I/O) pattern of the write data. When the offset information is received, the write data is programmed based on the offset information such that at least one state among a plurality of states included in a distribution of threshold voltages of memory cells in which the write data is stored is changed.

Abstract: A memory system includes: nonvolatile memory devices and a memory controller confirming a programming time for each word line of each of the nonvolatile memory devices and calculating a target programming time on the basis of the programming time for each word line. Each of the nonvolatile memory devices receives the target programming time from the memory controller, and adjusts the programming time for each word line on the basis of the target programming time. When the adjustment of the programming time for each word line is completed, the memory controller confirms a variation width of a writing speed of the memory system for a predetermined time, and sets the target programming time as a final target programming time when the variation width of the writing speed is smaller than a reference value.

Abstract: A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a pre-defined number of blocks of the non-volatile memory, performing a read operation on a first block included in a first super block based on a first read level, storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful, receiving a read request for a second block of the first super block and an address of the second block from a host, and performing a read operation on the second block based on the history read level stored in the history buffer. The pre-defined number is at least two.

Abstract: A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.

Abstract: A method of tuning a resonant frequency of a nano-electromechanical systems (NEMS) drum device is performed by applying a gate voltage between the drum membrane [100] and a back gate [104] to alter the resonant frequency of the membrane to a desired frequency; photoionizing the drum membrane with a laser to detune the membrane resonant frequency to a ground state frequency; and releasing the gate voltage to set the membrane to the desired resonant frequency. The method provides the basis for various applications including NEMS memory and photodetection techniques. The NEMS device may be implemented as a graphene/hBN membrane [100] suspended on a SiO2 layer [102] deposited on a Si substrate [104].

Abstract: The present disclosure provides a chip detection method and a chip detection apparatus. The chip detection method includes: providing a chip to be tested, the chip including a power pump region, and the power pump region including a plurality of power pump structures; detecting a dim light signal emitted from the power pump region when the chip is in a preset working mode; and determining whether the dim light signal matches a corresponding power pump working mode in the preset working mode, and if not, confirming that the power pump region has a defect, the power pump working mode including a working state of the power pump structures in the power pump region.

Abstract: A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.

Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

Abstract: A local region to be repaired including the fail bit is determined. A preliminary repair LR circuit for repairing the local region to be repaired is determined (S210). A region level of the local region to be repaired is determined (S230) according to the number of available GR circuits other than any replacement GR circuit configured for replacing the preliminary repair LR circuit and the number of available LR circuits. It is controlled, according to the region level of the local region to be repaired, to repair the fail bit by the GR circuit or the LR circuit (S240).

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

Abstract: Disclosed is a system including a memory device having a plurality of physical cells and a processing device, operatively coupled with the memory device. The processing device maintains association of block families with a first (second, etc.) bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets. The read voltage offsets are used to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the block families. Responsive to an occurrence of a power event, the processing device performs diagnostics of one or more blocks of various block families and determines whether to maintain association of the block families with current bins of the respective block families or to associate the block families with different bins.

Abstract: Systems and methods are provided for testing a Device Under Test (DUT) in its working environment. A control computer is coupled to an air compressor and generates a temperature control signal that is provided to the air compressor to generate an amount of hot air or cold air to set the temperature of the DUT's working environment to a desired test temperature. The control computer also generates at least one test signal that is sent to a hardware test element for testing at least one memory component of the DUT at the desired test temperature and obtaining test results. The control computer analyzes the test results to determine a parameter adjustment for the at least one memory element so that it operates in a stable manner at the test temperature.

Abstract: The present application relates to the technical field of integrated circuits, and in particular, to a memory test method and a memory test apparatus. The memory test method includes: providing a to-be-tested memory, where the to-be-tested memory includes a plurality of memory cells; alternately writing a first write value and a second write value into a memory cell of the memory cells at a preset frequency; writing a test write value into the memory cell; judging whether a data read from the memory cell is the test write value, and determining that a capacitance-frequency characteristic of the memory cell is abnormal if the data is not the test write value. According to the present application, the capacitance-frequency characteristic of the to-be-tested memory is accurately tested, to improve the field of memory products.

Abstract: A deterioration detection device includes a storage including a first current path and a second current path and configured such that a current is applied to the first current path and the second current path, a storage input control unit configured to compare an internal operating condition of a memory device with a target condition in a first operating mode and to select one of the first current path and the second current path of the storage based on a result of the comparison, and an output unit configured to output an output signal indicated deterioration, accumulated in one of the first current path and the second current path, in a second operating mode.

Abstract: The present disclosure relates to a memory test system and a memory test method. The memory test system comprises: a plurality of test devices, a host computer, and driving modules. Each of the test devices is provided with a test interface used for connecting a memory to be tested. The host computer is respectively connected to the plurality of test devices and configured to control the test devices to test the memory to be tested. The driving modules are connected to the test devices and configured to output, to the test devices, driving signals used for driving the test devices to perform data interaction with the host computer.

Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Abstract: Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Abstract: A word line lead-out structure and a method for preparing the same are provided. A word line extending along an X-axis direction is formed on a substrate. A contact hole covering the word line along a Y-axis direction is formed, the X-axis direction being perpendicular to the Y-axis direction. A metal line covering the contact hole is formed, the contact hole being located between the word line and the metal line and being contacted with the word line and the metal line. The contact area between the contact hole and the metal line is larger than that between the contact hole and the word line.

Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).

Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.

Abstract: The present disclosure provides a sense amplifier, a memory, and a data readout method, and relates to the field of semiconductor memory technologies. The sense amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first switch, a second switch, a third switch, and a fourth switch. During the offset compensation stage of the sense amplifier, the switching states of the first switch to the fourth switch are controlled so that the first NMOS transistor and the second NMOS transistor are configured to be in a cross-coupled amplification mode, and the first PMOS transistor and the second PMOS transistor are configured to be in a diode connection mode. The present disclosure enables to realize the offset compensation of the sense amplifier and improves the correctness of data readout by the memory.