Abstract: An oscillator includes: a resonator; an oscillation circuit configured to generate an oscillation signal by the resonator; a clock output terminal; an output circuit configured to output a clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit configured to execute communication with the processing device by a data signal. In the communication, the output circuit outputs the clock signal to the processing device that is a master for the communication, and the interface circuit that is a slave for the communication receives, via the first terminal, the data signal that is transmitted from the processing device and synchronized with the clock signal, or transmits, via the first terminal, the data signal to the processing apparatus in synchronization with the clock signal.

Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: Envelope tracking schemes for Doherty power amplifiers are provided herein. In certain embodiments, an envelope tracking system includes a carrier amplifier that amplifies a first radio frequency signal, a peaking amplifier that amplifies a second radio frequency signal corresponding to a delayed version of the first radio frequency signal, an envelope tracker that generates a first power supply voltage that powers the carrier amplifier, and a delay circuit that delays the first power supply voltage to generate a second power supply voltage that powers the peaking amplifier. The envelope tracker controls a voltage level of the first power supply voltage to track an envelope of the first radio frequency signal. Thus, supply modulation is used to achieve gains in linearity, efficiency, and/or other performance metrics.

Abstract: A sound system includes a sound source having an analogue audio signal output and a sound volume control; signal amplifier apparatus (10) comprising an analogue signal input (12) configured to be coupled to the analogue audio signal output of the sound source, an analogue signal output (18) and an amplifier module (62) coupled between the signal input and the signal output. The amplifier module (62) has a fixed amplification gain within a range of 10 to 12 decibels. Control of the audio signal is effected solely by the sound volume control of the sound source. The amplifier module (64) also provides a fixed gain bass boost of 6 decibels. The system provides linear amplification and allows a user to reduce the volume of the sound source, which significantly reduces signal distortion. Volume control is at the sound source and not at the amplifier module, which optimises amplification quality and reduces the power requirement of the amplifier apparatus (10).

Abstract: A power control circuit includes a negative feedback loop, and a radio frequency signal path including a first NMOS transistor having a gate configured as a radio frequency signal input end, a drain connected with a source of a second NMOS transistor, and a source connected with a ground terminal. A drain of the second NMOS transistor is configured as a radio frequency signal output end and connected with a first voltage source. The negative feedback loop includes a third NMOS transistor having a gate connected with an output end of a differential amplifier, a source connected with the ground terminal, and a drain connected with a source of a fourth NMOS transistor having a gate connected with a reverse input end of the differential amplifier and with a second voltage source, and a drain connected with a forward input end and a first bias current source.

Abstract: This disclosure relates to a signal generating circuit and an audio processing device. The circuit includes a switch module, a voltage producing module, and a signal generating module; the switch module is connected to the voltage producing module, including at least one control switch, and is used for receiving a frequency division signal. Based on the frequency division signal, the at least one control switch is turned on or turned off; the voltage producing module is separately connected to the switch module and the signal generating module and used for producing a first voltage and a second voltage. The at least one control switch controls the first voltage and the second voltage to change. The signal generating module is connected to the voltage producing module and used for generating a carrier signal with the same frequency as the frequency division signal according to the received first and second voltages.

Abstract: A power amplifier module includes an output-stage amplifier, a driver-stage amplifier, an input switch, an output switch, an input matching circuit, an inter-stage matching circuit, an output matching circuit, and a control circuit. The input switch selectively connects one of a plurality of input signal paths to an input terminal of the driver-stage amplifier. The output switch selectively connects one of a plurality of output signal paths to an output terminal of the output-stage amplifier. The control circuit controls operations of the driver-stage amplifier and the output-stage amplifier. The input switch, the output switch, and the control circuit are integrated into an IC chip. The control circuit is disposed between the input switch and the output switch.

Abstract: A power amplifier circuit includes a power amplification circuit and a diode assembly. The diode assembly is connected in series with a transistor amplification circuit of the power amplification circuit, and the transistor amplification circuit is configured to, when load of power amplifier is mismatched, turn the diode assembly on, so as to divide current voltage to at least two electrodes of the transistor amplification circuit.

Abstract: A transimpedance amplifier may include a voltage-controlled operational amplifier having a non-inverting input connected to ground, an inverting input receiving a current signal to be amplified, an output coupled to the inverting input via a coupling resistor, and a power-down input (PWDN input) activated upon receipt of at least one power-down signal (PWDN) such that at least one internal current source is thereupon deactivated.

Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.

Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.

Abstract: One illustrative high bandwidth transimpedance amplifier includes a distributed amplifier having multiple transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to the input signal's current. An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from a final node of the input signal line via a feedback impedance.

Abstract: A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

Abstract: Provided is a method for audio peak reduction using an all-pass filter, including: determining a delay parameter m and a gain parameter g based on a formula (1): arg ? min m , g max n ? "\[LeftBracketingBar]" y m , g ( n ) ? "\[RightBracketingBar]" , ( 1 ) absolute peak map Y ? ( m , g ) = max n ? "\[LeftBracketingBar]" y m , g ( n ) ? "\[RightBracketingBar]" , ym,g(n) represents a processed signal with a time-domain response function and is calculated based on a formula (2): ym,g(n)=(hs*x)(n)(2), where hs represents an impulse response function, x (n) represents an input signal, and hs is calculated based on formula (3): H S ( z ) = g + z - m 1 + gz - m . ( 3 ) This method is widely used in the reproduction, storage and broadcasting of sound, and the computational complexity is small, which is a supplement to the traditional nonlinear compression algorithm.

Abstract: A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.

Abstract: A method of manufacture for an acoustic resonator device. The method includes forming a nucleation layer characterized by nucleation growth parameters overlying a substrate and forming a strained piezoelectric layer overlying the nucleation layer. The strained piezoelectric layer is characterized by a strain condition and piezoelectric layer parameters. The process of forming the strained piezoelectric layer can include an epitaxial growth process configured by nucleation growth parameters and piezoelectric layer parameters to modulate the strain condition in the strained piezoelectric layer. By modulating the strain condition, the piezoelectric properties of the resulting piezoelectric layer can be adjusted and improved for specific applications.

Abstract: A filter includes an input terminal, an output terminal, a first ground terminal, a second ground terminal, a first inductor having a first end coupled to a first node in a path between the input terminal and the output terminal and a second end coupled to a second node, a second inductor having a first end coupled to the second node and a second end coupled to the first ground terminal, and a third inductor having a first end coupled to the second node and a second end coupled to the second ground terminal.

Abstract: An integrated passive die includes a substrate, an input node, an output node, and RF filtering circuitry. The RF filtering circuitry includes a number of LC tank circuits coupled between the input node and the output node. Each one of the LC tank circuits include an inductor and a capacitor. The inductor is formed by a metal trace over the substrate. The capacitor is coupled in parallel with the inductor over the substrate. The inductor and the capacitor are provided such that a resonance frequency of the combination of the inductor and the capacitor is less than a self-resonance frequency of the inductor.

Abstract: Acoustic filters, resonators and methods of making acoustic filters are disclosed. An acoustic resonator device includes a substrate. A back surface of a piezoelectric plate is attached to the substrate, a portion of the piezoelectric plate forming a diaphragm that spans a cavity in the substrate. A conductor pattern is formed on the front surface of the piezoelectric plate, the conductor pattern including an interdigital transducer (IDTs) with interleaved fingers of the IDT disposed on the diaphragm. A ratio of the mark of the interleaved fingers to the pitch of the interleaved fingers is greater than or equal to 0.2 and less than or equal to 0.3.

Abstract: An acoustic resonator device with low thermal impedance has a substrate and a single-crystal piezoelectric plate having a back surface attached to a top surface of the substrate via a bonding oxide (BOX) layer. An interdigital transducer (IDT) formed on the front surface of the plate has interleaved fingers disposed on the diaphragm. The piezoelectric plate and the BOX layer are removed from a least a portion of the surface area of the device to provide lower thermal resistance between the IDT and the substrate.

Abstract: An acoustic wave device comprises a piezoelectric substrate, interdigital transducer electrodes having an electrode pitch ?0, and first and second reflector gratings disposed on opposite respective sides of the interdigital transducer electrodes in a propagation direction of a main acoustic wave through the acoustic wave device, the first reflector grating having a different electrode pitch ?1 than an electrode pitch ?2 of the second reflector grating to suppress ripples in a conductance curve of the acoustic wave device.

Abstract: Aspects of this disclosure relate to a surface acoustic wave device with a vertical stack over a piezoelectric layer. The vertical stack can include a first acoustic reflector disposed on the piezoelectric layer, a second acoustic reflector disposed on the piezoelectric layer, and an interdigital transducer electrode disposed on the piezoelectric layer and positioned between the first acoustic reflector and the second acoustic reflector. The interdigital transducer electrode has a first side that is closer to the first acoustic reflector and a second side that is closer to the second acoustic reflector. A vertical arrangement of the vertical stack can be configured such that an acoustic wave propagation velocity of a first region between the first side and a first reflector is faster than an acoustic wave propagation velocity of a second region between the first side and the second side.

Abstract: A resonance device that includes a MEMS substrate including a resonator, an upper lid, and a bonding portion bonding the MEMS substrate and the upper lid to seal a vibration space of the resonator. The bonding portion includes a eutectic layer containing a eutectic alloy as a main component thereof. The eutectic alloy is composed of a first metal containing aluminum as a main component thereof, a second metal of germanium or silicon, and a third metal of titanium or nickel.

Abstract: An acoustic resonator assembly and a filter are disclosed. The acoustic resonator assembly includes at least two acoustic resonators vertically connected to each other. The acoustic resonator includes: an acoustic mirror, a bottom electrode layer, a piezoelectric layer, and a top electrode layer that are arranged on a substrate. An active area of the acoustic resonator is defined by an overlapping area of the acoustic mirror, the bottom electrode layer, the piezoelectric layer, and the top electrode layer. The acoustic resonator further includes a support layer arranged on the substrate or the piezoelectric layer on a periphery of a projection of the acoustic mirror on the substrate. The at least two acoustic resonators are vertically connected to each other through the support layer. The filter significantly reduces the volume and the area of a device, improves design freedom and reduces design difficulty, enhances product performance and greatly reduces costs.

Abstract: When a radio-frequency module is viewed in plan in a thickness direction of a mounting substrate, an electronic component overlaps an IC component. The electronic component includes four or more filters, each of which includes an input terminal and an output terminal. The IC component includes a first switch connected to the input terminals of at least four of the four or more filters and a second switch connected to the output terminals of the at least four filters. The input terminals of the at least four filters are in a first region including a center of the electronic component when viewed in plan in the thickness direction of the mounting substrate. The output terminals of the at least four filters are in a second region between the first region and a perimeter of the electronic component when viewed in plan in the thickness direction of the mounting substrate.

Abstract: A multiplexer includes a plurality of filters, in which one input/output terminal of each of the plurality of filters is connected to a common terminal, a first filter included in the plurality of filters is a ladder filter and includes at least one series arm resonator connected on a path connecting the common terminal and another input/output terminal of the first filter, at least one parallel arm resonator connected between a connection node provided on the path and a ground, and a switch which is connected in series to a parallel arm resonator connected most nearby to the common terminal among at least one parallel arm resonator and switches between conduction and non-conduction of a node to which the parallel arm resonator is connected and the ground.

Abstract: A composite filter device includes a connection portion connected to a common terminal, a first filter between the connection portion and a first terminal, a second filter between the connection portion and a second terminal, a first inductor that is connected in series between the second filter and the connection portion, includes a first wiring electrode wound in a predetermined direction, and is provided at an internal layer of a multilayer board, and a second inductor that is connected in series between the common terminal and the connection portion, includes a second wiring electrode wound in the predetermined direction, and is provided at an internal layer of the multilayer board. The first and second wiring electrodes at least partially overlap when the multilayer board is viewed in plan.

Abstract: In a filter device, a transversal elastic wave filter, which defines a delay element, is connected in parallel with a band pass filter. The transversal elastic wave filter has the same amplitude characteristic as and the opposite phase to the band pass filter at a desired frequency inside an attenuation range of the band pass filter. When a wavelength determined by an electrode finger period of IDTs and is denoted by ?, the distance between the first IDT and the second IDT of the elastic wave filter is about 12? or less.

Abstract: A multiplexer includes: a switch capable of connecting a common terminal to at least one of a first selection terminal, a second selection terminal, and a third selection terminal at the same time; a first filter connected to the first selection terminal, the first filter having a first pass band; a second filter connected to the second selection terminal, the second filter having a second pass band that is different from the first pass band; and a coupling circuit connected to the third selection terminal and the first filter, the coupling circuit forming a signal path between the third selection terminal and the first filter by electromagnetic coupling.

Abstract: A protective circuit for a semiconductor switch includes a clamp diode, an NPN bipolar transistor, a PNP bipolar transistor, a capacitor connected in parallel with the base-emitter path of the PNP bipolar transistor, and at least three resistors. The bipolar transistors are connected to a thyristor structure that is connected to the cathode of the clamp diode. A first resistor is connected in parallel with the base-emitter path of the NPN bipolar transistor. A first terminal of the second resistor is connected to the base of the PNP bipolar transistor. Either a third resistor is connected in parallel with the base-emitter path of the PNP bipolar transistor, or a first terminal of the third resistor is connected to the emitter of the PNP bipolar transistor and the second terminal of the third resistor is connected to the second terminal of the second resistor.

Abstract: To prevent deterioration of current detection accuracy due to a difference in deterioration between a main MOS and a sense MOS. The load drive device includes a main MOS (101) for supplying a load current to a load, a sense MOS (102) to be used for detection of the load current, and an equalizer circuit (110) and a switch (120) which are provided in parallel between the source terminal of the main MOS and the source terminal of the sense MOS. The drain terminal of the main MOS and the drain terminal of the sense MOS have a common connection, and when a current is detected, the terminal voltage of the main MOS and the terminal voltage of the sense MOS are equalized by the equalizer circuit, and the switch is opened. When a current is not detected, the equalizer circuit is stopped and the switch short-circuits the source terminal of the main MOS and the source terminal of the sense MOS.

Abstract: A post driver and a chip with overdrive capability are shown. A first bias circuit is configured to provide a first voltage shift between the output terminal of the post driver and the gate terminal of the first p-channel metal-oxide-semiconductor (PMOS) transistor of a pull-up circuit when the pull-down circuit is enabled. A second bias circuit is configured to provide a second voltage shift between the output terminal of the post driver and the gate terminal of the first n-channel metal-oxide-semiconductor (NMOS) transistor of the pull-down circuit when the pull-up circuit is enabled. Accordingly, the PMOS transistors in the pull-up circuit and the NMOS transistors in the pull-down circuit are all well protected although they are powered by an overdrive voltage.

Abstract: The invention provides a method for checking a semiconductor switch for a fault, wherein the semiconductor switch is driven with a PWM signal with a variable duty cycle. To the benefit of determining faults on the semiconductor switch reliably and cost-effectively, it is provided that if the semiconductor switch is operated with a duty cycle of 100% or 0%, the current measurement of the overall system is evaluated, while if the semiconductor switch is operated with a duty cycle of between 0% and 100%, the generated voltage pulses across the semiconductor switch are evaluated.

Abstract: A relay circuit may include a solid state relay switch, coupled to an external voltage line and to an charging capacitor; and a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may be arranged to: turn the solid state relay switch to an OFF state when a capacitor voltage of the charging capacitor falls below a low threshold value; and change the solid state relay switch from the OFF state to an ON state when the capacitor voltage increases above a high threshold value.

Abstract: A driving apparatus drives a load. An N-channel MOSFET is disposed downstream of the load on a current path of a current that flows via the load. A circuit resistor is connected between a direct current power source and the gate of the MOSFET. A first switch is connected between the gate and the source of the MOSFET. A microcomputer outputs a voltage relative to a potential at an output terminal of a second switch to a control terminal of the second switch. As a result, the second switch is turned ON or OFF. A switching circuit turns the first switch ON when the second switch is turned ON and turns the first switch OFF when the second switch is turned OFF.

Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

Abstract: An operator for controlling electrically adjustable furniture includes a housing and an actuation panel movably supported in the housing to form a cover body. A circuit board is provided in the housing, and a main control unit for detecting an actuation signal is provided on the circuit board. A first switch for generating a first actuation signal and a second switch for generating a second actuation signal are provided between the actuation panel and the main control unit, and a third switch for generating a third actuation signal is provided between a bottom wall of the housing and the main control unit. The main control unit issues a first command when simultaneously detecting the first actuation signal and the second actuation signal, and the main control unit issues a second command when simultaneously detecting the first actuation signal, the second actuation signal, and the third actuation signal.

Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.

Abstract: A level shifter circuit of a driving device includes first and second pulse generators, first and second level shifters, and a determination circuit. The first pulse generator provides a first input signal according to a high-voltage signal. The first input signal includes a pulse signal having a first current level and a sustain signal having a second current level following the pulse signal. The first level shifter receives the first input signal to generate a first indication signal. The second pulse generator provides a second input signal according to the high-voltage signal. The second input signal includes the pulse signal and the sustain signal following the pulse signal. The second level shifter receives the second input signal to generate a second indication signal. The determination circuit generates a low-voltage signal according to the first indication signal and the second indication signal.

Abstract: A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.

Abstract: A method of resetting a digital counter for a personal care appliance by sending an electrical output signal from an optical sensor to a control circuit. The electrical output signal is compared to a predetermined value with the control circuit or a change in the electrical output signal from the optical sensor is detected over time. A signal is sent to a consumer user interface by the control circuit based on the electrical output signal and the predetermined value or based on the change in the electrical output signal from the optical sensor. The digital counter is reset based on an input signal from the consumer user interface.

Abstract: A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Abstract: A circuit includes an inverter coupled between an input and an output. The inverter includes first and second pull-down transistors having control terminals coupled to the input, a pull-up resistor, and a pull-up transistor having a control terminal coupled to the input. The first and second pull-down transistors are coupled in series along a pull-down path extending between a first voltage supply terminal and the output. The pull-up resistor and pull-up transistor are coupled in series along a pull-up path extending between a second voltage supply terminal and the output. A hysteresis transistor has a control terminal coupled to the output. The hysteresis transistor is coupled to the inverter along a hysteresis path extending between the first voltage supply terminal and the pull-up path. A clamp circuit is coupled to the inverter along a clamp path extending between the first voltage supply terminal and the pull-down path.

Abstract: A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: A switching method, including: electrically coupling a switching circuit to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generation circuit and a negative terminal of the frequency generation circuit; adjusting an impedance value of the second impedance circuit according to a first clock signal and a second clock signal outputted by the frequency generation circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit by a first switching unit of the switching circuit; and periodically conducting the positive terminal to the other one of the first impedance circuit and the second impedance circuit by a second switching unit of the switching circuit.