Abstract: A method of adjusting elements of a GUI to reflect multi-selection of GUI items, comprising presenting a plurality of selectable GUI items each characterized by one or more unique attributes and one or more action GUI configured to initiate one or more actions adjusted according to a multi-selection of the selectable GUI items, analyzing user input to detect multiple indications gradually indicated by a user to select a group of selectable GUI items, responsive to detection of each of the indications, appending the unique attribute(s) of the respective selectable GUI item selected in the respective indication to the action GUI element(s) such that the action GUI element(s) is dynamically adjusted to aggregate the unique attribute(s) of all of the selectable GUI items of the group, and responsive to activation of the action GUI element(s), initiate the action(s) adjusted according to all of the selectable GUI items of the group.

Abstract: Systems, methods, and non-transitory computer-readable media are provided for data analysis. A user interface comprising boards corresponding to one or more objects and one or more operations on the input and/or output objects of the boards can be generated for high-scale top-down data analysis.

Abstract: Methods and systems are disclosed for dynamically and automatically modifying a user interface (UI) of an application based on the UI capabilities of a computer device running the application, in particular whether the computer device is touch-enabled or not.

Abstract: A touch sensor system includes touch sensors, drive-sense circuits (DSCs), memory, and a processing module. A DSC drives a first signal via a single line coupling to a touch sensor and simultaneously senses, when present, a second signal that is uniquely associated with a user. The DSC processes the first signal and/or the second signal to generate a digital signal that is representative of an electrical characteristic of the touch sensor. The processing module executes operational instructions (stored in the memory) to process the digital signal to detect interaction of the user with the touch sensor and to determine whether the interaction of the user with the touch sensor compares favorably with authorization. When not authorized, the processing module aborts execution of operation(s) associated with the interaction of the user with the touch sensor. Alternatively, when authorized, the processing module facilitates execution of the operation(s).

Abstract: At least certain embodiments of the present disclosure include an environment with a framework of software code interacting with a plurality of applications to provide gesture operations in response to user inputs detected on a display of a device. A method for operating through an application programming interface (API) in this environment includes displaying a user interface that includes a respective view that is associated with a respective application of the plurality of applications. The method includes, while displaying the respective view, detecting, via the software code, a user input within the region of the touch-sensitive surface that corresponds to the respective view, and, in response, in accordance with a determination that the user input is an inadvertent user input, ignoring the user input. The determination that the user input is an inadvertent user input is made based on an inadvertent user input call transferred through the API.

Abstract: An electronic device displays a messaging user interface of a messaging application, including a conversation transcript of a messaging session between a user of the electronic device and another user, a message-input area, and a representation corresponding to the other user. In response to detecting a first user input corresponding to the representation of the other user, a menu is displayed that contains an activatable menu item for initiating a payment action with the other user. While displaying the menu, in response to detecting a second user input corresponding to the activatable menu item for initiating a payment action with the first other user, a user interface configured to initiate sending of payment to, and/or requesting payment from, the first other user is displayed.

Abstract: Disclosed is an electronic device comprising: a communication unit comprising communication circuitry configured to communicate with an input device; a camera; and at least one processor operably connected to the communication unit and the camera, wherein the at least one processor is configured to: determine whether a condition for generating a virtual input interface is satisfied, generate the virtual input interface on based on the determination, acquire information about the movement of the input device through the communication unit and/or the camera, and transmit, to the input device, feedback information about the movement of the input device, generated on the virtual input interface, through the communication unit.

Abstract: Vehicle systems and methods are provided for associating text entry components with software applications in a decoupled software environment. One method involves a user input management service associating a user input from a user input device with an interactive application based on a location associated with the user input, providing the user input to the application based on the association, wherein the application responds to the user input, receiving indication of selection of a text input element by the user input from the application. In response to the indication of selection of the text input element, the user input management service associates a text entry component with the application and thereafter provides a text input received from the associated text entry component to the application based on the association between the text entry component and the application, wherein the application responds to the text input.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first logical partition in the communication fabric that includes a first processing device and a memory device, and directing transfer of configuration data for storage by the memory device over the first logical partition. After transfer of the configuration data, the method includes instructing the communication fabric to remove the first logical partition in the communication fabric, where the configuration data remains stored by the memory device after removal of the first logical partition. The method also includes instructing the communication fabric to establish a second logical partition in the communication fabric that includes at least a second processing device and the memory device comprising the configuration data, where the second processing device is operated using the configuration data.

Abstract: Disclosed by the present application are a system and method for multi-device media data management, and a robot device. A detection module detects a device located within a detection range, and determines according to a detection result whether to add the device to a device management list. A storage module obtains media data generated by each device in the device management list and stores the media data in a backup system in association with a corresponding tag. An instruction module receives an instruction of a user and analyzes the content of the instruction, the content comprising a tag and management type corresponding to the media data. A management module performs a management operation on corresponding media data according to the analyzed content.

Abstract: A processing load is reduced when a flash memory is used. A storage management device acquires an archive associated with an application, stores the acquired archive to one or more blocks among a plurality of blocks contained in the flash memory, and deletes one block among the plurality of blocks. In the archive storage, the acquired archive is stored in one of the blocks not storing an archive associated with an application different from that of the acquired archive, and in the deletion of one block, when an application is deleted, a block storing an archive associated with the application to be deleted is deleted.

Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.

Abstract: A computer-implemented method enables workload scheduling in a storage system for optimized deduplication. The method includes determining dynamic correlations of deduplications between workload processes in a prior time window. Workload processes include one or more tasks with defined execution timing parameters. The method further includes determining deduplication ratios based on the correlations of the deduplications between the workload processes. The method further includes scheduling multiple workload processes based on a highest determined deduplication ratio of the determined deduplication ratios.

Abstract: Embodiments of the present disclosure provide a data processing method, a controller, a storage device, and a storage system. The controller adds an execution time of an IO request to the IO request, and the execution time is used to instruct the storage device to complete the IO request before the execution time expires. The controller sends, to the storage device, the IO request to which the execution time is added. When receiving the IO request, the storage device can execute the IO request based on the execution time of the IO request.

Abstract: A data storage device and method for detecting malware on a data storage device. The device includes a non-volatile storage medium configured to store at least one file system control block and user data block(s) to store user data. The file system control block comprises at least one reference data structure. The data storage device further comprises a buffer to temporarily store user data. The data storage device further comprises a controller to scan each write command in the user data to be transferred for protocol commands or malicious data. The controller also stops the data transfer of user data from the buffer to the non-volatile storage medium if at least one of protocol commands or malicious data is detected in at least one write command.

Abstract: The present disclosure generally relates to increasing data storage device lifetime by detecting synthetic PLP tests. Both upper and lower PLP time thresholds are set. When the PLP time is above the upper threshold, the data storage device is in a defensive PLP idle state. When the PLP time is between the upper and lower thresholds, the data storage device is in a defensive PLP detecting state. When the PLP time is below the lower threshold, the data storage device may enter the defensive PLP state if the number of times the PLP time is below the lower PLP time threshold either a consecutive number of times or a set number of times within a predefined window of time. While in the defensive PLP state, mounting is not completed and hence, a host device will not send any I/O commands and thus, not waste a PEC count.

Abstract: Reliability in a storage system can be easily and appropriately improved. In a computer system including a storage system configured to provide a plurality of instances in any one of a plurality of subzones divided by risk boundaries, a processor of the computer system is configured to make a storage controller that controls I/O processing for a volume based on a capacity pool provided by a plurality of storages redundant to the plurality of instances provided in the plurality of subzones.

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

Abstract: A method, a computer program product, and a system for initializing components to monitor for unauthorized encryptions of filesystem objects stored on a computing system. The method includes configuring an encryption monitor register to establish monitoring preferences of filesystem objects and allocating a predetermined size of persistent memory as a backup memory area for storing pre-encrypted versions of the filesystem objects. The method also includes inserting a starting address of the backup memory area in data bits of the encryption monitor register, and setting encryption monitor bits of page table entries in a hardware page table that correspond to at least one filesystem object, thereby establishing encryption monitoring of the filesystem object.

Abstract: A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

Abstract: A memory allocation device includes a storage including at least one memory pool in which a memory piece used to search for a route is previously generated and a controller that determines whether it is possible to search for the route using the previously generated memory piece and determines an added amount of memory pieces to previously allocate a memory of the storage, when it is impossible to search for the route.

Abstract: Disclosed is a nonvolatile memory, which includes a plurality of input/output pads connectable to a plurality of data lines, an enable input pad, an enable output pad, and a chip address initialization circuit. The chip address initialization circuit receives a current chip address through the plurality of input/output pads, stores the current chip address in response to a current enable signal received through the enable input pad, outputs a next enable signal through the enable output pad, and outputs a next chip address through the plurality of input/output pads.

Abstract: A data storage system includes a plurality of data storage drives, and a system controller coupled to each data storage drive of the plurality of data storage drives. The system controller is configured to store internal drive management data for each data storage drive of the plurality of data storage drives.

Abstract: Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

Abstract: An apparatus, system, and method are provided each of which stores data that is received in a memory; acquires transfer history information indicating a transfer state of the data, from an information processing system configured to transfer the data to an external storage; identifies data to be transmitted from within the data stored in the memory, based on the transfer history information; and transmits the identified data to the information processing system.

Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured, for each of a plurality of logical storage devices of a storage system, to determine in a multi-path layer of a layered software stack of a host device a performance level for that logical storage device, to communicate the performance levels for respective ones of the logical storage devices from the multi-path layer of the layered software stack of the host device to at least one additional layer of the software stack above the multi-path layer, and to select particular ones of the logical storage devices for assignment to particular storage roles in the additional layer based at least in part on the communicated performance levels. The additional layer in some embodiments comprises an application layer configured to automatically select a particular one of the logical storage devices for a particular storage role.

Abstract: A system and method for two-level indexing for key-value persistent storage. The method may include: sorting two or more key-value pairs to form a sorted key-value pair set; determining an address of a first key-value pair of the key-value pairs, the first key-value pair including a first key and a first value; determining an address of a second key-value pair of the key-value pairs, the second key-value pair including a second key and a second value; and training a first linear regression model to generate a first line corresponding to the key-value pairs, the training including training the first linear regression model with key-value pairs including the first key-value pair and the second key-value pair.

Abstract: A method is provided for use in a storage processor, the method comprising: receiving a write request, the write request including a request to store user data in an array that includes a plurality of solid-state drives (SSD); executing the write request by: identifying metadata that is associated with the write request, and writing the user data and the metadata to different data streams that are opened on the plurality of SSDs; wherein writing the user data and the metadata to different data streams causes: (i) the user data to be stored in one or more first erase units of any of the plurality of SSDs, and (ii) the metadata to be stored in one or more second erase units of any of the plurality of SSDs, such that no part of the metadata is stored on any of the one or more first erase units, and no part of the user data is stored on any of the one or more second erase units.

Abstract: A memory system includes a plurality of memory devices including first and second memory devices and a controller coupled to the plurality of memory devices to control operations performed on the plurality of memory devices. Each of the first and second memory devices includes a plurality of memory blocks, and memory blocks of the first and second memory devices form superblocks. The superblocks include a first superblock that includes memory blocks of the first and second memory devices and a second superblock that includes memory blocks of the first and second memory devices. The controller includes a first core unit and a second core unit configured to perform a first search operation and a second search operation, respectively, wherein the first and second search operations are performed in parallel.

Abstract: Techniques are provided for combining data block and checksum block I/O into a single I/O operation. Many storage systems utilize checksums to verify the integrity of data blocks stored within storage devices managed by a storage stack. However, when a storage system reads a data block from a storage device, a corresponding checksum must also be read to verify integrity of the data in the data block. This results in increased latency because two read operations are being processed through the storage stack and are being executed upon the storage device. To reduce this latency and improve I/O operations per second, a single combined I/O operation corresponding to a contiguous range of blocks including the data block and the checksum block is processed through the storage stack instead of two separate I/O operations. Additionally, I/O operation may be combined into a single request that is executed upon the storage device.

Abstract: The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.

Abstract: A storage device includes a memory device, and a memory controller configured to receive data and a log related to a property of the data from an external host, allocate a super block in which the data in the memory device is to be stored and a physical zone in the super block based on the log of the data, and store information for the log of the data stored for each physical zone and a time point at which a physical zone of a full state in which an empty area does not exist is switched to the full state. The memory controller controls the memory device to perform garbage collection according to the number of physical zones of an empty state, and selects a victim physical zone based on the information for the log of the data and a full state switch time point.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

Abstract: A request to perform a first operation in a system that stores deduplicated data can be received. The system can include a data block stored at multiple logical address each referencing the data block. A reference count can be associated with the data block and can denote a number of logical addresses referencing the data block. Processing can be performed to service the request and perform the first operation, wherein the processing can include: acquiring a non-exclusive lock for a page that includes the reference count of the data block; storing, in a metadata log while holding the non-exclusive lock on the page, an entry to decrement the reference count of the data block; and releasing the non-exclusive lock on the page.

Abstract: In an approach to improve magnetic tape file systems through tape-to-tape copying between nodes on a Linear Tape File System using a cluster-wide named pipe. Embodiments transfer data between a first node and a second node. Additionally, both the first node and the second node implement a parallel shared-disk file system through a data path for node data reading and writing from a shared-disk and to the shared-disk. Further, to transfer data between the first node and the second node, embodiments, write, by the first node, the data for tape-to-tape copy from a first tape drive to the shared-disk, and write, by the second node, the data written from the shared-disk to a second tape drive.

Abstract: A method for performing a backup operation includes obtaining, by a backup server, a backup request, wherein the backup request specifies a virtual machine to be backed up, wherein the virtual machine is hosted by a production host, and in response to the backup request: obtaining classification data from the backup agent, initiating a backup classification on an unprocessed backup associated with the virtual machine based on the classification data to obtain a sensitivity tag, and initiating a data processing on the unprocessed backup based on the sensitivity tag.

Abstract: A system and method for bidirectionally based electrical information storage, processing and communication. Bidirectional memory (tristate) offers the capability to store and interpret multiple bits (Shannon's) of information per memory cell, for structures such as dynamic random-access memory (DRAM), and read-only memory (ROM), and communication circuits, for operation, rather than traditional memory able to store a single “bit” (Shannon) of information per cell. Where, instead of traditional memory cells capable of two possible states (binary digit) and a single defined bit (1 Shannon), bidirectional memory is capable of three states (tristate), where the third information representing state can be a specifically defined state capable of representing multiple bits (multiple Shannon's) for each individual cell, which may be defined to represent a specific sequence of bits (sequence of Shannon's).

Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

Abstract: Methods, systems, and devices for cache management in a memory subsystem are described. An interface controller may include a first buffer and a second buffer. The interface controller may use the first and second buffers to facilitate operating a volatile memory as a cache for a non-volatile memory. During an access operation, the interface controller may use the buffer to transfer data between the volatile memory, non-volatile memory, and another device. In response to the access operation, the interface controller may use the second buffer to transfer second data from the volatile memory to the non-volatile memory.

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.

Abstract: A storage device including a non-volatile memory device which receives an operating command and performs an operation corresponding to the operating command, a voltage generating circuit which generates an operating voltage according to the operating command, and a flag generating circuit which receives a busy signal indicative of the non-volatile memory device performing the operation and a pump enable signal instructing pumping of the operating voltage, and outputs a flag signal based on the busy signal and the pump enable signal. The busy signal has a first level when the non-volatile memory device performs the operation, and the flag signal transitions from a second level to the first level in response to the operating voltage becoming equal to or higher than a first reference voltage while the busy signal is at the first level.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Each computing device is operable to access one or more memory blocks within the storage devices and maintain a registry over the same one or more memory blocks. The registry may be adaptively resized according to the access of the one or more memory blocks.

Abstract: A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

Abstract: According to an embodiment, a memory system includes memory chips operable in parallel and a memory controller. The memory chips each include first storage areas. The memory controller generates first groups each including first storage areas selected from different memory chips. The memory controller generates second groups each being constituted by a minimum number of first storage areas composed by excluding one or more first storage areas from each of the first groups. The minimum number of first storage areas are capable of storing at least a first amount of data received from the host. The memory controller executes writing of the data to all the minimum number of first storage areas constituting one second group.

Abstract: An information processing apparatus that functions as a SUB controller that, for a command group formed of pairs each formed by a command prepared by a host controller and a status, executes processing of each command and returns a status of an execution result of the command processing. In response to a request for processing the command group from the host controller, the SUB controller acquires the command group therefrom as an original command sequence. The original command sequence is divided into a plurality of segments each formed by one or more commands and having a total volume not larger than a threshold. Command groups each formed of pairs each formed by a command and a status are independently set in one or more storage devices connected to the information processing apparatus. Each storage device is notified of a command processing request on a segment-by-segment basis.

Abstract: Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.

Abstract: Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.

Abstract: According to one embodiment, a memory system includes a communication interface connectable to a plurality of hosts. A virtual controller creation unit creates a virtual controller based on connection of a host to the communication interface. An access management unit manages permission information indicating a correspondence between each of the plurality of namespaces and a host permitted to access the namespace. The virtual controller creation unit create, based on the permission information, a first virtual controller to which a namespace that a first host connected to the communication interface is permitted to access is attached, as a virtual controller to be used by the first host to access a nonvolatile memory.