Abstract: A remote data recovery system is determined to be unsuitable for communications. A stream of source system storage changes associated with an object is received at a backup system from a source system while the remote data recovery system is unsuitable for communications. The backup system is utilized to generate one or more reference restoration points based on the stream of source system storage changes associated with the object. The remote data recovery system is determined to be suitable for communications. In response to determining that the remote data recovery system is suitable for communications, a hot standby of the object hosted by the remote data recovery system is updated to a reference restoration point generated by the backup system prior to the remote data recovery system becoming suitable for communications.

Abstract: The invention relates to a computer-implemented system for recovering data in case of a computer network failure. The invention also relates to a computer-implemented method for recovering data in case of a computer network failure, preferably by making use of the computer-implemented system according to the invention. The invention further relates to a non-transitory computer-readable program storage device, comprising computer readable instructions executable by one or more processors to perform the computer-implemented method according to the invention.

Abstract: A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and M redundant banks, where each of P, N and M is a positive integer, and N is greater than M The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. One of the M redundant banks is coupled with at least two main banks of the N main banks through the I/O circuit. The I/O control logic is configured to in responding to K main banks of the P groups of banks failed, determine the P×N working banks including K redundant banks of P×M redundant banks, where K is a positive integer not greater than P, and control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

Abstract: Disclosed are various example embodiments which may be configured to: collect a measurement time-series relating to a performance indicator of a communication network resource; compute a representative vector of said measurement time-series; provide a clustering model comprising a set of clusters, wherein the clustering model has been trained on a plurality of training time-series, wherein a cluster of the set of clusters comprises partial time-series that meet a similarity condition, wherein a cluster anomaly label is associated with said cluster; select a subset of the set of clusters, wherein the subset comprises at least one cluster for which the partial time-series within the cluster meet a distance condition with the representative vector; and associate an anomaly label with the measurement time-series, wherein the anomaly label is computed as a function of the cluster anomaly label.

Abstract: System and methods for testing input/output (I/O) points in an automation system. A control system software agent in the automation system is configured to send and receive test setpoints for the automation system. A testing server specifies the test setpoints to the automation system for a plurality of I/O points to be tested and generates a web user interface presenting instructions for conducting testing of the I/O points using the specified test setpoints. A user computing device associated with the I/O points to be tested receives the web user interface and displays the instructions, communicates the instructions to a smart meter for applying input signals to the I/O points to be tested and/or measuring output signals from the I/O points to be tested in accordance with the instructions, and communicates results of the testing to the testing server for generating documentation.

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

Abstract: A detection method includes sending a first command to a first electronic device; receiving a first target value sent by the first electronic device, where the first target value includes a quantity of allocated memory blocks in the first electronic device in a case that the first electronic device performs a first operation; sending a second command to the first electronic device in a case that the first electronic device performs a second operation; receiving a second target value sent by the first electronic device, where the second target value includes a quantity of allocated memory blocks in the first electronic device in the case that the first electronic device performs the second operation; and determining, in a case that the second target value is greater than the first target value, that there is a memory leak in the first electronic device.

Abstract: A computing system may receive an indication of a gaming application and an indication of a computing device. The computing system may determine, using collaborative filtering of performance scores of a plurality of gaming applications executing at a plurality of computing devices, a predicted performance of the gaming application executing at the computing device. The computing system may send an indication of the predicted performance of the gaming application executing at the computing device.

Abstract: Provided is an information processing apparatus that allows a plurality of systems to efficiently share information regarding an alert. An information processing apparatus includes an ID assigning computer that assigns a log ID to collected log data of a device, a first processing computer that stores the log data and the log ID and detects an abnormality based on the log data, and a second processing computer that stores the log data and the log ID, detects an abnormality based on the log data, and transmits the log ID of the log data in which the abnormality is detected and a detection result of the abnormality to the first processing computer. The first processing computer stores the log data stored in the first processing computer and the received detection result in association with each other based on the log ID received from the second processing computer.

Abstract: Techniques for failure prediction of controllers are disclosed. For example, a method comprises collecting data corresponding to operation of a plurality of controllers from one or more devices, and predicting, using one or more machine learning algorithms, at least one of degradation and failure of one or more controllers of the plurality of controllers based, at least in part, on the data corresponding to the operation of the plurality of controllers. Using the one or more machine learning algorithms, one or more corrective actions to prevent the at least one of the degradation and the failure of the one or more controllers are identified. Instructions comprising the one or more corrective actions are generated and transmitted to at least one user device.

Abstract: Techniques for evaluating software systems are provided, including measurement of performance ratings of features of an app-under-test are described. The evaluation may include analysis of a video recording of the user interface of the app-under-test, where the video analysis may include comparing the changes over time of co-located pixel in the video to produce a performance rating, for example a speed index. The results of multiple such tests can be compared by comparing the performance rating produced during execution of different tests.

Abstract: Techniques are disclosed relating to the execution of queries in an online manner. For example, in some embodiments, a server system may include a distributed computing system that, in turn, includes a distributed storage system operable to store transaction data associated with a plurality of users, and a distributed computing engine operable to perform distributed processing jobs based on the transaction data. In various embodiments, the server system preemptively creates a compute session on the distributed computing engine, where the compute session provides access to various functionalities of the distributed computing engine. The distributed computing engine may then use these preemptively created compute sessions to execute queries (e.g., for end users of the server system) against the transaction data and return the results dataset to the requesting users in an online manner.

Abstract: A relay and metering test instrument includes an application processor circuitry to control functional operation of the relay and metering test instrument. The application processor circuitry may receive a user selected source code state program, and operational parameters input by the user. The application processor circuitry may compile the source code state program and the operational parameters into a test routine for storage in a memory circuitry with other test routines. The relay and metering instrument may also include a real time processor circuitry and an input/output processor circuitry. The real time processor circuitry may selectively and independently execute the test routine or one of the other test routines to perform one or more respective testing stages. The input/output processor circuitry may cooperatively operate with the real time processor circuitry to output test signals and monitor for receipt of input test signals according to execution of the test routine.

Abstract: An application in production may communicate with one or more heterogeneous services, including requesting and receiving data from a one or more data sources. The communication between the application and the services can include complicated scenarios making facilitating end-to-end testing of the application difficult. The disclosed service virtualization solution works in two stages of ‘record and replay’ to simulate a backend service. During the recording stage, the disclosed tool intercepts the data flow between the client and the service and records the data and during the replay stage, the disclosed tool creates a proxy service that simulates the responses of service application by reading the recorded session file, allowing for the client application to be tested without having to connect to the actual service application.

Abstract: This disclosure describes systems, methods, and devices related to remotely testing virtual network functions with edge gateways. A method may include providing an application for receiving user inputs for testing a virtual network function (VNF); receiving, via the application, a first user input associated with adding an image of a virtual machine instance to the application; downloading, via the application, the image based on the first user input; receiving, via the application, a second user input associated with instantiating a service associated with the virtual machine instance; instantiating, via the application, the service based on the second user input; receiving, via the application, a third user input associated with testing the VNF with the edge gateway device using the image and the service; and executing, via the application, a test of the VNF with an edge gateway using the image and the service based on the third user input.

Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

Abstract: In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.

Abstract: A computer-implemented method dimensions a buffer memory configured to be used by multiple executable tasks. The executable tasks, according to a predetermined time scheduling, at least one of write data elements in the buffer memory or read data elements from the buffer memory. The method includes determining a plurality of writing and reading operations of the plurality of executable tasks. The method includes determining a largest set of data elements to be stored in the buffer memory according to the plurality of writing and reading operations. The method includes dimensioning the buffer memory according to the largest set of data elements.

Abstract: A storage device may generate mapping information between a plurality of memory regions and one or more namespaces. The storage device may record information on empty memory regions among the plurality of memory regions in an empty table, and may determine empty memory regions to be mapped to a target namespace among the empty memory regions recorded in the empty table.

Abstract: Disclosed is a method of adjusting the performance of a wear leveling operation depending on the pattern of a workload according to a command inputted to a storage device, thereby managing a difference in the count of erase operations between storage areas included in a memory not to exceed a limit value and enabling a wear leveling operation to be performed.

Abstract: A method includes collecting resource utilization statistics associated with execution of an application, identifying calls to a function associated with management of the application, and adjusting an allocation of computing resources for executing the application in view of the resource utilization statistics and the calls to the function.

Abstract: A cache management method, a solid state drive controller, and a solid state drive are provided. The solid state drive comprises a cache space, and the cache space comprises a dirty data block linked list. The method comprises: obtaining a write command and generating a first dirty data block used to record data information of the write command; and if the first dirty data block conflicts in address range with a second dirty data block in the dirty data block linked list, marking data in the conflicting region of the second dirty data block as invalid and inserting the first dirty data block into the dirty data block linked list.

Abstract: Described are examples for storing data on a storage device, including storing, in a live write stream cache, one or more logical blocks (LBs) corresponding to a data segment, writing, for each LB in the data segment, a cache element of a cache entry that points to the LB in the live write stream cache, where the cache entry includes multiple cache elements corresponding to the multiple LBs of the data segment, writing, for the cache entry, a table entry in a mapping table that points to the cache entry, and when a storage policy is triggered for the cache entry, writing the multiple LBs, pointed to by each cache element of the cache entry, to a stream for storing as contiguous LBs on the storage device, and updating the table entry to point to a physical address of a first LB of the contiguous LBs on the storage device.

Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.

Abstract: The present application discloses a data caching method, system and device in an AI cluster, and a computer medium. The method comprises: determining a target data set to be cached; obtaining a weight value of the target data set on each cluster node in the AI cluster, determining a target cluster node for caching the target data set; obtaining a target shortest path from remaining cluster nodes comprising nodes except the target cluster node in the AI cluster, and on the basis of the weight value, the target shortest path, and the preceding node, determining a cache path for caching the target cluster node, so as to cache the target data set to the target cluster node according to the cache path.

Abstract: A method for managing a memory write request in a cache device is provided. The cache device is coupled between a central processing unit and a system memory. The cache memory includes plural levels. An Nth level of the cache device includes an Nth-level command buffer, an Nth-level cache memory and a write allocation buffer, wherein N is an integer larger than 1. The method includes the following steps. Firstly, a request is received from a previous level. If the request is the memory write request, the memory write request is temporarily stored into a free entry of the write allocation buffer. The memory write request contains an address information and a write data. If the request is not the memory write request, the request is temporarily stored into a free entry of the Nth-level command buffer.

Abstract: An example disclosed apparatus comprises a trigger monitor to detect an event satisfying a cache scrape trigger rule during execution of a workload, and a cache scraper to scrape cache data from cache in hardware during the execution of the workload.

Abstract: Disclosed is a method of operating a swap memory device configured to communicate with a host device and a main memory device. The method includes receiving, from the host device, a request corresponding to target data, determining, by the swap memory device, a first address of the target data and a second address of a target data block that includes the target data, based on the request, providing, by the swap memory device, the target data to the host device based on the first address, and providing, by the swap memory device, the target data block to the main memory device based on the second address.

Abstract: The disclosure provides a method for caching data. The method generally includes receiving, from an application running in a first container, an I/O to write data in a storage virtual disk to a block associated with an LBA, determining a cache is assigned to the first container and the storage virtual disk using a container mapping table comprising a first container mapping table entry mapping the first container and the disk to the cache and a second container mapping table entry mapping a second container and the disk to the cache, writing the data to the block in the storage virtual disk and to a cache block in the cache, computing a hash of the data, adding an entry that maps the LBA to the hash in an LBA table, and adding an entry that maps the hash to the cache block and to the disk in a hash table.

Abstract: The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

Abstract: A hybrid scheme is provided for performing translation lookaside buffer (TLB) shootdowns in a computer system whose processing cores support both inter-processor interrupt (IPI) and broadcast TLB invalidate (TLBI) shootdown mechanisms. In one set of embodiments, this hybrid scheme dynamically determines, for each instance where a TLB shootdown is needed, whether to use the IPI mechanism or the broadcast TLBI mechanism to optimize shootdown performance (or otherwise make the TLB shootdown operation functional/practical).

Abstract: A system is described. The system may include a host processor, a host memory connected to the host processor, and a storage device connected to the host processor. An accelerator may communicate with the host processor. The accelerator may produce an output. The accelerator may also include a local memory, which may include a first region and a second region. The first region of the local memory of the accelerator may support a first mode, and the second region of the local memory of the accelerator may support a second mode. The accelerator may store the output of the accelerator in a destination, which may include the host memory, the storage device, the first region of the local memory of the accelerator, or the second region of the local memory of the accelerator.

Abstract: For a given application, increasing the size of a cache is beneficial up to a certain point and the number of hits does not increase significantly with a greater cache size. This disclosure provides a method to determine a miss ratio curve, for a cache having data blocks with a time-to-live. A hashed value of a data block's key address can be used to generate a 2D HLL counter for storing expiry times of the data blocks. The 2D HLL counter can be converted to a 1D array, from which a stack distance can be calculated. A frequency distribution of stack distances can then be converted into a miss ratio curve, from which an appropriate cache size can be selected.

Abstract: Provided are a computing storage separation system and a data access method therefor, the method includes: acquiring a data access request; acquiring, based on a type of the data access request, an index table on a master node of the computing storage separation system or synchronization metadata information of the master node and a slave node of the master node; when the data access request is a data read request, querying an index item of a to-be-read data block in the index table, and reading the to-be-read data block based on an index item query result; and/or when the data access request is a data write request, writing a to-be-written data block into an idle space of a persistent memory on the slave node based on the synchronization metadata information.

Abstract: A self-detecting and data rewriting system and application method thereof, mainly comprising: a computer with a data protecting unit installed internally that stores and records at least the computer's boot data and set hotkeys, and an external protection device that has an internal firmware collocated with a data storage unit, the external protection device includes an external connector to be connected with the computer to form information connection, so that the data storage unit is able to update automatically after comparing with and referring to the data protecting unit, to obtain the information of the booting and set hotkeys from the computer and stored and recorded in the external protection device. Thereby, when the computer fails to operate normally, use the external protection device to be connected to the computer so that the computer operating system can be restored and resumed with normal operation.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

Abstract: This application relates to a data format conversion apparatus and method. The data format conversion apparatus is located in a DMA module of a processor. A data format that is of tensor data and that is supported by the processor is a first data format. The DMA module includes: a DMA controller DMAC. If a second data format of tensor data stored in an external memory is different from the first data format, the DMAC is configured to convert, in a process of transmitting to-be-converted tensor data between a memory of the processor and the external memory, the to-be-converted tensor data from the first data format into the second data format or from the second data format into the first data format, to obtain converted tensor data.

Abstract: A modular communication system for connection to a master unit, including a device which is configured in a decentralized manner and includes at least a first module and a second module, wherein the first module is configured and set up to be directly connected to the master unit, and wherein the second module is directly connected to the first module and is configured and set up to be indirectly connected to the master unit via the first module, wherein the first module is further configured and set up to receive a data signal from the master unit. The data signal includes at least a first data set usable by the first module, and at least a second data set usable by the second module. The present disclosure further relates to a summing frame method, to a block frame method and to an indexing method for operating the communication system.

Abstract: The present disclosure relates to a Controller Area Network, CAN, controller, comprising: an input interface, a transmit data, TXD, interface, and a processing unit, wherein the input interface is coupled to the processing unit, wherein the processing unit is configured to receive via the input interface a data packet comprising a packet priority field, a packet payload field, wherein the processing unit is configured to generate a first CAN frame based on the data packet, such that a first payload field of the first CAN frame represents at least the packet payload field and a first identifier field of the first CAN frame comprises a first identifier part and a second identifier part, wherein the first identifier part represents predefined data for identifying the CAN controller, and wherein the second identifier part represents the packet priority field and/or comprises a queue field representing a queue priority for the first CAN frame, wherein the processing unit is coupled to the TXD interface, and wherei

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

Abstract: A host device of a serial device system having a serial communications connection The host device including a host serial communication transceiver connected to a peripheral serial communication transceiver of a peripheral device via a serial connection of a serial communications cable having communication lines. The host device measures electrical power consumption of the host serial communication transceiver to determine when serial communications is prevented due to the serial communications cable being disconnected which includes at least one of the communication lines being detached from the host, detached from the peripheral device, or broken.

Abstract: Example methods and apparatus for data access are described. In one example, a memory expansion card receives a first data access request generated by a computing device based on an internal bus protocol. Then, the memory expansion card performs protocol conversion on the first data access request to obtain a second data access request in an external bus protocol format, where the external bus protocol includes a bus protocol for accessing external memory space of the computing device. Further, the memory expansion card accesses the external memory space based on the second data access request. The memory expansion card shields a difference between the bus protocols, and provides internal memory space for the computing device.

Abstract: Passage of data packets on a data pipeline is arbitrated in a distributed manner along the pipeline. Multiple data arbiters each operate to merge data from a respective data source to the data pipeline at a distinct point in the pipeline. At each stage, a multiplexer selectively passes, to the data pipeline, an upstream data packet or a local data packet from the respective data source. A register stores an indication of data packets passed by the multiplexer based on the respective data source originating the data packet. A controller controls the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.

Abstract: A building management system includes a communications bus, and devices coupled to the communications bus. The devices are coupled to the communications bus and configured to communicate on the communications bus using a master-slave token passing protocol. A first one of the devices has an active node table stored therein. The active node table includes multiple nodes. Each node represents one of the devices participating in a token passing ring used to exchange information among the devices via the communications bus using the master-slave token passing protocol. The first device is configured to monitor the active node table for new nodes and to identify a new device communicating on the communications bus in response to a determination that the active node table includes a new node.

Abstract: A method for transmitting data from and to an electronic device configured to implement at least transmissions of metering data on consumption of a physical quantity, said transmissions being implemented by said electronic device according to at least one data communication protocol (for example DLMS/COSEM) referring to data defined according to an object oriented data model, said data model defining a plurality of classes of communication interface objects, making it possible to access elements of the electronic device, said method being such that said object oriented data model comprises at least one class of communication interface objects comprising attributes and methods for implementing communications via a communication port of the serial port type included in said electronic device or connected thereto. The invention also relates to an electronic device implementing the method.

Abstract: Embodiments described herein provide SPI systems that can accommodate more peripheral devices on a serial data signal line. The present disclosure relates to various configurations of SPI communication interfaces that operably connect one or more peripheral devices serially to a controller device. The configurations of serially-connected peripheral devices can enable more peripheral devices to be supported on a serial data signal line in each SPI system. The present disclosure reduces or eliminates the limitation regarding the driving capability of the controller device or the peripheral devices. The present disclosure further reduces the restriction regarding the pin count requirement for the select signals.

Abstract: A modular IoT sensor system for Internet of things includes a network module and an expanded sensor module. The expanded sensor module includes a male connector and a female connector respectively disposed in two connection surfaces of the expanded sensor module, configured to detachably connect to a female connector of the network module. Shape and size of the female connector of the network module and the male connector and the female connector of the expanded sensor module conform to a USB type-C specification and pin definitions thereof are complied with a first pin definition different from USB type-C specification.