Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: A semiconductor device includes an active pattern disposed on a substrate. A gate insulating film is disposed on the active pattern and extends along the active pattern. A work function adjustment pattern is disposed on the gate insulating film and extends along the gate insulating film. A gate electrode is disposed on the work function adjustment pattern. The work function adjustment pattern includes a first work function adjustment film, a second work function adjustment film that includes aluminum and wraps the first work function adjustment film, and a barrier film including titanium silicon nitride (TiSiN). A silicon concentration of the barrier film is in a range of about 30 at % or less.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 ?m and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

Abstract: A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

Abstract: A semiconductor device includes an active layer having first and second active regions, first and second source electrodes, first and second drain electrodes, first and second gate electrodes, a first source metal layer, first and second drain metal layers, and a source pad electrically connected to the first source metal layer. The second drain metal layer is electrically connected to the second drain electrode and the first source metal layer. A projection of the second drain metal layer on the active layer forms a drain metal layer region. An projection of the source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.

Abstract: A trench power MOSFET includes a body region disposed on a semiconductor substrate, a trench passing through the body region, an top electrode and a bottom electrode spaced apart from each other in a vertical direction in the trench, an inter-electrode dielectric layer disposed between the top electrode and the bottom electrode, and a plurality of dielectric layers, disposed between a sidewall of the trench and the bottom electrode, comprising a first oxide layer disposed on the sidewall of the trench, an barrier layer disposed on the first oxide layer, and a second oxide layer disposed on the barrier layer. The barrier layer is formed of a material different from materials of the first and second oxide layers.

Abstract: A transistor arrangement includes a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor, and wherein a resistance of the second source conductor is different from a resistance of the first source conductor.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf1-xZrxO2, in which x is greater than 0.5 and is lower than 1.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: A highly reliable semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator; a first conductor and a second conductor over the first insulator; an oxide provided between the first conductor and the second conductor; a second insulator over the first conductor, the second conductor, and the oxide; and a third conductor over the second insulator. A side surface of the first conductor includes a region in contact with one side surface of the oxide, a side surface of the second conductor includes a region in contact with the other side surface of the oxide. The level of a top surface of the first conductor, the level of a top surface of the second conductor, and the level of a top surface of the oxide are substantially the same. The conductivity of the first conductor is higher than that of the oxide, and the conductivity of the second conductor is higher than that of the oxide.

Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

Abstract: The present disclosure provides a thin film transistor, a display panel and a display device. The thin film transistor includes a semiconductor material layer, a first insulating layer and a gate layer. The semiconductor material layer is at a side of a base substrate, and includes a first channel portion, a first doped portion and a second channel portion sequentially connected. The first insulating layer is at a side of the semiconductor material layer facing away from the base substrate. The gate layer is at a side of the first insulating layer facing away from the semiconductor material layer, and includes a first gate portion and a second gate portion. An orthographic projection of the first gate portion on the base substrate coincides with an orthographic projection of the first channel portion on the base substrate, and the first gate portion is configured to receive a gate driving signal.

Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.

Abstract: The present disclosure relates to an image sensor. The image sensor includes a substrate and a photodetector in the substrate. The image sensor further includes an absorption enhancement structure. The absorption enhancement structure is defined by a substrate depression along a first side of the substrate. The substrate depression is defined by a first plurality of sidewalls that slope toward a first common point and by a second plurality of sidewalls that slope toward a second common point. The first plurality of sidewalls extend over the second plurality of sidewalls.

Abstract: A solar cell is provided. The solar cell includes: an N-type silicon substrate having a first surface and a second surface, a tunnel passivation structure and a first passivation and anti-reflection film formed on the first surface, a boron-doped emitter structure layer including a first emitter layer and a second emitter region formed on the second surface, a second passivation and anti-reflection film formed on the emitter structure layer, a first electrode configured to be in electrical contact with the second emitter region, and a second electrode configured to be in electrical contact with the tunnel passivation structure. The solar cell of the present application has a selective emitter structure. The metal contact region has a large junction depth to meet the metallization requirements. The region outside the metal contact region has a small junction depth to improve the optical response.

Abstract: Provided is a see-through thin film solar cell module including a transparent substrate, a first back electrode deposited on a first surface of the transparent substrate, a second back electrode deposited on the first back electrode and including a MoSe2 layer, an absorber layer deposited on the second back electrode and including selenium (Se) or sulfur (S), and a laser scribing pattern formed by partially removing the absorber layer.

Abstract: A photovoltaic module includes a front protective layer, a back protective layer, a plurality of solar cells, and a filler. The front protective layer is transmissive to light and has a first surface and a second surface opposite to the first surface. The back protective layer faces the second surface. The plurality of solar cells are between the second surface and the back protective layer. The filler is between the front protective layer and the plurality of solar cells and covers the plurality of solar cells. The filler includes a material with a chemical structure to generate a free acid. The front protective layer includes a weather-resistance resin. At least a part of the first surface is exposed to a space external to the photovoltaic module.

Abstract: A solar cell according to an embodiment of the present disclosure is positioned so that a second solar cell adjacent to a first solar cell in a first direction have an adjacent portion in contact with or overlapping with the first solar cell in the first direction on a front surface of the first solar cell. In this case, a plurality of wiring members connecting the first and second solar cells are formed to be extended to the front surface of the first solar cell, the adjacent portion, and the rear surface of the second solar cell.

Abstract: In one aspect, optoelectronic devices are described herein. In some implementations, an optoelectronic device comprises a photovoltaic cell. The photovoltaic cell comprises a space-charge region, a quasi-neutral region, and a low bandgap absorber region (LBAR) layer or an improved transport (IT) layer at least partially positioned in the quasi-neutral region of the cell.

Abstract: The present invention relates to a solar cell manufacturing method, a solar cell manufactured thereby, and a substrate for a solar cell. The solar cell manufacturing method involves forming a separating portion for separating a substrate, which is for manufacturing the solar cell, into a plurality of pieces. The solar cell manufacturing method comprises: a step for preparing the substrate; a first substrate etching step for forming a first groove in one surface of the substrate; a second substrate etching step for forming a second groove inside the first groove; and a third substrate etching step for etching the substrate including the second groove, wherein the separating portion includes the first groove and the second groove.

Abstract: Discussed is a display device and a method for manufacturing same, specifically, to a display device using semiconductor light-emitting elements of a few micrometers to tens of micrometers in size, and includes substrate having a wiring electrode, and a plurality of semiconductor light-emitting elements electrically connected to the wiring electrode, wherein each of the plurality of light-emitting elements includes of a buffer layer and an oxide layer formed on the buffer layer, and the oxide layer includes of an oxide of the buffer layer.

Abstract: An LED display fabrication tool includes a plurality of process chambers and a plurality of transfer chambers. The plurality of process chambers include first and second dispensing chambers to deliver first and second color conversion precursors onto a workpiece for fabrication of a light emitting diode (LED) displays, and first and second washing/drying chambers to remove uncured portions of the first and second color conversion precursors from the workpiece and then dries the workpiece. The plurality of transfer chambers are coupled to two process chambers by two respective sealable ports. First and second curing stations cure the precursors to form the first and second color conversion layers over a first set of LEDs on the workpiece.

Abstract: A light-emitting device is provided. The light-emitting device generates a white light and includes at least one light-emitting diode. The at least one light-emitting diode generates a light beam with a broadband blue spectrum and includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well structure. The multiple quantum well structure is located between the first semiconductor layer and the second semiconductor layer, and includes well layers and barrier layers. The well layers include a first well layer, a second well layer and third well layers different in indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of the well layers that are closest to the first semiconductor layer are the third well layers, and the first well layer is closer to the second semiconductor layer than the first semiconductor layer.

Abstract: A display apparatus is provided. The display apparatus includes a display panel; and a light emitting diode (LED) chip configured to emit light to the display panel. The LED chip includes: a light emitting layer configured to emit light; a semiconductor layer provided on the light emitting layer; and a growth substrate provided on the semiconductor layer. The light emitting layer is arranged to be biased toward a first side of the growth substrate such that a center of an upper surface of the growth substrate is provided between a center of the light emitting layer and a center of the semiconductor layer.

Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.

Abstract: A display device includes a first electrode, a second electrode spaced apart from the first electrode to face the first electrode, a first insulation layer, at least one light emitting element, a second insulation layer, a first contact electrode, and a second contact electrode. The first insulation layer includes an overlapping area which overlaps the at least one light emitting element, a first non-overlapping area which extends outward from the first end of the at least one light emitting element and does not overlap the at least one light emitting element, and a second non-overlapping area which extends outward from the second end of the at least one light emitting element and does not overlap the at least one light emitting element.

Abstract: An embodiment provides a semiconductor device comprising: a semiconductor structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, and a plurality of first recesses and second recesses which extend through the second conductive semiconductor layer and the active layer and are arranged up to one region of the first conductive semiconductor layer, a first electrode disposed inside each of the first recesses and second recesses to be electrically connected to the first conductive semiconductor layer, and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer, the active layer, the second conductive semiconductor layer include aluminum, and the number of most adjacent recesses in the plurality of second recesses is fewer than that in the plurality of first recesses and the plurality of second recesses include multiple recesses, each having an area larger than that of each

Abstract: A method for producing a conversion element comprising the following steps is described: providing a conversion layer having a matrix, in which phosphor particles are brought in, the phosphor particles comprising a host lattice having activator ions and being concentrated in a enrichment zone, providing a compensation layer having the matrix, in which compensation particles are brought in, which comprise the host lattice and are concentrated in a enrichment zone, and joining the conversion layer and the compensation layer in such a way that the enrichment zone of the conversion layer and the enrichment zone of the compensation layer are arranged symmetrically to one another with respect to a symmetry plane of the conversion element. A conversion element and a component are also specified.

Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

Abstract: An electronic device including a substrate and at least one light emitting unit is provided. The at least one light emitting unit is disposed on the substrate. The at least one light emitting unit includes a light emitting diode and a protective layer. The protective layer includes a portion overlapped with the light emitting diode, and the portion has a concave part adjacent to an edge of the light emitting diode in a top view of the electronic device.

Abstract: The present disclosure relates to a display substrate, a display device, and a method for manufacturing a display substrate. The display substrate includes a base substrate having a first side and a second side opposite to the first side, a via provided in the base substrate, a thin film transistor provided on the first side of the base substrate, a first conductive structure provided on the first side of the base substrate, wherein a first sub-portion of the first conductive structure is located in the via, and wherein a material of the first conductive structure is the same as a material of a source/drain electrode of the thin film transistor.

Abstract: The invention is a small-sized vertical light emitting diode chip with high energy efficiency, wherein a PN junction structure is arranged on a light-emitting region platform of an interface structure; a highly reflective metal layer is arranged under the light-emitting region platform; the interface structure is provided with a P-type ohmic contact area under an outwardly extending platform adjacent to the light-emitting region platform; an insulating layer is formed on the outwardly extending platform; an N-type ohmic contact electrode is in ohmic contact with the PN junction structure and covers the border covering region at a position opposite to the outwardly extending platform; the current conduction is achieved diagonally on the opposite sides by locally diagonally symmetric geometric positioning of the N-type ohmic contact electrode and the P-type ohmic contact area.

Abstract: An electronic device includes a substrate, a first conductive wire, a plurality of semiconductors, an insulation layer and a plurality of conductive elements. The first conductive wire is disposed on the substrate and extends along a first direction. The semiconductors are disposed on the substrate and arranged along the first direction. The semiconductors are overlapped with the first conductive wire in a top view of the electronic device. The insulation layer is disposed between the first conductive wire and the semiconductors. The insulation layer includes a plurality of holes. The conductive elements are disposed on the substrate and overlapped with the semiconductors respectively in the top view of the electronic device. In the top view of the electronic device, each one of the holes overlaps with at least one semiconductor, and a number of the holes is less than a number of the conductive elements.

Abstract: A light-emitting device includes a carrier, a light-emitting element and a connection structure. The carrier includes a first electrical conduction portion. The light-emitting element includes a first light-emitting layer capable of emitting first light and a first contact electrode formed under the light-emitting layer. The first contact electrode is corresponded to the first electrical conduction portion. The connection structure includes a first electrical connection portion and a protective portion surrounding the first contact electrode and the first electrical connection portion. The first electrical connection portion includes an upper portion, a lower portion and a neck portion arranged between the upper portion and the lower portion. An edge of the upper portion is protruded beyond the neck portion, and an edge of the lower portion is protruded beyond the upper portion.

Abstract: Provided are a guide hopper and an apparatus for manufacturing secondary battery including the same. The guide hopper includes a guide space adjusted by movement of a corner member defining the guide space. The guide hopper includes a housing, in which an inner space having upper and lower portions is defined, and a variable assembly disposed in the inner space of the housing. The variable assembly includes four corner members of which bent inner sides define a guide space having a rectangular shape. The size of the guide space is adjustable by movement of the corner members in a first direction or in a second direction perpendicular to the first direction.

Abstract: A battery cell includes: a casing; an end cap assembly including an end cap body and an electrode terminal located on the end cap body; and an electrode assembly arranged in the casing and including a first electrode sheet and a second electrode sheet with opposite polarities; the first electrode sheet includes a first main portion and a first electrode tab protruding from the first main portion, and the second electrode sheet includes a second main portion and a second electrode tab protruding from the second main portion; an end of the winding body includes a first conductive region and a second conductive region, the first electrode tab is led out from the first conductive region, the second electrode tab is led out from the second conductive region, and adjacent first conductive region and second conductive region are arranged to be spaced along a radial direction of the winding body.

Abstract: A pouch type secondary battery in which an electrode lead of the pouch type secondary battery and an electrode lead of an adjacent different pouch type secondary battery are welded together to construct a battery module is provided. The electrode lead of the pouch type secondary battery includes a length extended part so that, after cutting a welded part of the electrode leads of the pouch type secondary battery and the adjacent different pouch type secondary battery to form electrode leads of remaining length, the electrode leads of remaining length are welded together again. A battery module and method of reusing the battery module are also provided.

Abstract: Provided are materials that may be used in or as a separator in an electrochemical cell such as a lithium sulfur battery. The separator includes a material capable of absorbing and desorbing a polysulfide. The inclusion of the materials in a separator provide for reduced sulfur loss from a cathode during cycling thereby improving cycle life.

Abstract: The present disclosure aims to provide, even when a strong impact is applied to a battery, a nonaqueous electrolyte secondary battery excellent in impact resistance so as not to ignite, smoke, and the like by internal short circuit. A nonaqueous electrolyte secondary battery according to one example of an embodiment: includes a positive electrode in which exposed portions and are formed at central portions in a longitudinal direction of a positive electrode collector; a positive electrode tab bonded to the exposed portion; an insulating tape adhered to the positive electrode to cover the exposed portion; and an insulating tape adhered to the positive electrode to cover the exposed portion. The insulating tapes are adhered to the positive electrode so that width-direction ends and/or the other width-direction ends are not overlapped with each other in a thickness direction of the positive electrode.