Abstract: Embodiments of process kits for use in a process chamber are provided herein. In some embodiments, a process kit for use in a process chamber includes: a deposition ring including a first portion having an first inner ledge and a second portion having a second inner ledge, wherein in a first position, the first portion is spaced from the second portion, and wherein in a second position, the second portion is configured to engage the first portion so that the first inner ledge is aligned with the second inner ledge along a common plane to form a clamping surface.

Abstract: Disclosed is a He-3 detector arrangement that generally comprises a mass spectrometer that has an intake funnel configured to receive (sniff out) He-3 through an intake port directly from an open environment. The intake funnel is configured to direct the He-3 into the mass spectrometer. The arrangement further comprises a heating element configured to liberate the He-3 from regolith via heat. A mobile carrier is configured to position the intake port the regolith to obtain samples of the He-3.

Abstract: An analysis system includes a degassing cell, at least one first valve, and at least one second valve. The at least one first valve is fluidly coupled with a top of the degassing cell, the at least one first valve configured selectably connect the degassing cell to a displacement gas flow and to a vacuum source. The at least one second valve is fluidly connected with a lateral side of the degassing cell and separately fluidly connected with a bottom of the degassing cell. The at least one second valve is selectably coupled with any of a source of a sample-carrying fluid, a transfer line configured to deliver a sample to an analysis device, or a waste output.

Abstract: An ion analyzer includes an ion optical element having four rod electrodes around an optical axis, for transferring ions from their surrounding space to the subsequent stage while converging the ions. To create an RF electric field within this space, a voltage supplier applies RF voltages of opposite polarities to two pairs of electrodes facing each other across the axis. The cross-sectional shape of each electrode in a plane orthogonal to the axis has a first side having width w facing the axis and is tangent to a circle of radius r0 around the axis, and two adjacent sides connected to the ends of the first side at an angle determined so that an RF field created by the adjacent sides exerts no influence within the space. The ratio w/r0 is determined so that the amount of dodecapole field component becomes a predetermined value or does not exceed it.

Abstract: The invention relates to the generation of desolvated ions by electrospraying to be investigated analytically, e.g. according to the charge-related mass m/z and/or ion mobility. The cloud of highly charged droplets drawn from the spray capillary by a high voltage is usually focused and stabilized by a beam of nebulizing gas surrounding the cloud of tiny droplets. For a fast drying of the droplets, an additional desolvation gas is usually heated to a temperature of up to several hundred degrees centigrade and blown into the cloud of droplets. The invention particularly relates to the heating of the gas which is instrumental in the generation of desolvated ions as part of the electrospraying process without any mechanical or electrical contact between the heating power supply and the heater itself, but rather by heating the heater for the gas using electromagnetic induction.

Abstract: A time-of-flight mass spectrometer (TOF MS) comprises a mass analyzer, an ion pushing device, a filtering device, a multi-pass reflector, a detector, and a decoder. The ion pushing device is arranged to push ions into the mass analyzer. The filtering device is arranged to filter a portion of the ions based on a mass range of the ions. The multi-pass reflector is arranged to selectively reflect the ions for further passes through the mass analyzer. The detector is arranged to receive the ions. The decoder is arranged to reconstruct a mass spectrum for the entire mass range of the ions.

Abstract: An energy spectrometer with dynamic focus for a transmission electron microscope (TEM) is disclosed herein. An example energy spectrometer and TEM at least includes a charged particle column including a projection system arranged after a sample plane, the projection system is operated in a first configuration; an energy spectrometer coupled to the charged particle column to acquire one or more energy loss spectra. The energy spectrometer including a dispersive element, a bias tube, optics for magnifying the energy loss spectrum and for correcting aberrations, and a detector arranged conjugate to a spectrum plane of the energy spectrometer, wherein the energy spectrometer further includes an optical element electrically biased to refocus at least a portion of a spectrum onto the detector, and wherein the value of the electrical bias is at least partially based on the first configuration of the charged particle column.

Abstract: A method for cleaning a substrate with pattern structures comprises the following steps: using gas-liquid atomization to clean a substrate surface (601); using TEBO megasonic to clean the substrate surface (602); and drying the substrate (603). The TEBO megasonic cleaning is used to remove small size particles on the substrate and the gas-liquid atomization cleaning is used to remove large size particles on the substrate. The method enables achieving an effect of cleaning the substrate without or with less device damage. A substrate cleaning apparatus is also provided.

Abstract: A substrate cleaning apparatus has: a substrate rotating part that rotates a substrate; an edge cleaning member for cleaning an edge part of the substrate; an edge rotating part that rotates the edge cleaning member around an edge rotary shaft that extends in a direction orthogonal to a substrate rotary shaft; a moving part that moves a position of the edge cleaning member with respect to the edge part of the substrate; and a control part that controls the moving part to move the position of the edge cleaning member with respect to the edge part of the substrate, and causes the edge cleaning member to clean a one-side edge area including a face on one side, a side face area including a side face, and an another-side edge area including a face on another side in the edge part of the substrate.

Abstract: A method of post-deposition treatment for silicon oxide film includes: providing in a reaction space a substrate having a recess pattern on which a silicon oxide film is deposited; supplying a reforming gas for reforming the silicon oxide film to the reaction space in the absence of a film-forming precursor, said reforming gas being composed primarily of He and/or H2; and irradiating the reforming gas with microwaves in the reaction space having a pressure of 200 Pa or less to generate a direct microwave plasma to which the substrate is exposed, thereby reforming the silicon oxide film.

Abstract: Using the first robot, the carrier standing by in the load lock chamber is deposited into the reaction chamber without mounting the wafer before processing, and cleaning gas is supplied while the reaction chamber is maintained at a predetermined cleaning temperature, and the carrier that has been cleaned in the reaction chamber is transferred to the load lock chamber using the first robot. The carrier is cleaned at a predetermined frequency.

Abstract: A method of processing a substrate that includes: depositing a photoactive metal-based hard mask (photo-MHM) over an underlying layer, the underlying layer formed over a substrate, the photo-MHM including a metal; depositing a dielectric over the photo-MHM; etching a portion of the dielectric to form a first feature; depositing a spacer material over the first feature; etching the spacer material to expose top surfaces of the dielectric and a first portion of the photo-MHM; exposing the photo-MHM to a first ultraviolet light (UV) radiation through a first photomask, a first unmasked region of the photo-MHM being photoreacted due to the exposure to the first UV radiation; after the exposure, developing the photo-MHM to form a second feature in the photo-MHM; and etching the underlying layer using the photo-MHM as an etch mask.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: A method for forming a self-aligned double pattern and semiconductor structures are provided. The method for forming a self-aligned double pattern includes the following steps: providing a substrate; sequentially forming a first mask layer, a second mask layer and a third mask layer on an upper surface of the substrate, and etching downwards from an upper surface of the third mask layer in a direction perpendicular to the upper surface of the substrate until a first trench exposing an upper surface of the first mask layer is formed; removing the third mask layer, and partially removing the first mask layer, so as to deepen the first trench; forming a spacer layer on an inner wall of the first trench, and filling the first trench with a fourth mask layer; and partially removing the spacer layer to form a second trench exposing the substrate.

Abstract: An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

Abstract: A sacrificial sealing layer is formed on a high-? metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-? metal oxide layer on the interfacial layer, the high-? metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-? metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-? metal oxide layer to form a dipole region.

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.

Abstract: Methods of forming patterned structures suitable for a multiple patterning process are disclosed. Exemplary methods include forming a silicon nitride layer overlying the substrate by providing a silicon precursor to the reaction chamber for a silicon precursor pulse period, providing a nitrogen reactant to the reaction chamber, providing a hydrogen reactant to the reaction chamber, and providing a plasma power to form a plasma within the reaction chamber for a plasma pulse period. An etch profile of sacrificial features on the substrate can be controlled by controlling an amount of hydrogen provided to the reaction chamber and/or using other process parameters.

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Abstract: Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.

Abstract: A dry etching method according to one embodiment of the present disclosure includes plasmatizing a dry etching agent and etching a silicon oxide or a silicon nitride with the plasmatized dry etching agent, wherein the dry etching agent comprises CF3I and a C2-C3 fluorine-containing linear nitrile compound, and wherein the concentration of the C2-C3 fluorine-containing linear nitrile compound relative to the CF3I is higher than or equal to 1 vol. ppm and lower than or equal to 1 vol %.

Abstract: Embodiments of the present disclosure provide an etching method with a metal hard mask. The method is performed on a wafer surface and includes sequentially forming a metal hard mask layer and at least one functional film layer on a wafer surface in a direction away from the wafer surface. The method includes performing a plurality of etching processes on the at least one functional layer and the metal hard mask layer sequentially in a direction close to the wafer surface. An etching gas adopted by at least one etching process includes a hydrogen element and a fluorine element. A ratio of a content of the hydrogen element in the etching gas to a content of the fluorine element in the etching gas is smaller than a predetermined threshold to reduce generation of a byproduct of hydrogen fluorine.

Abstract: A wet etching apparatus includes a process bath having an internal space configured to receive an etchant and having a support unit, on which a wafer is disposed to be in contact with the etchant. A laser unit is disposed above the process bath and is configured to direct a laser beam to the wafer and to heat the wafer thereby. An etchant supply unit is configured to supply the etchant to the internal space of the process bath.

Abstract: A heater assembly includes a substrate, a plurality of resistive heating elements disposed along a perimeter of the substrate, and a common ground electrical lead connected to at least some of the plurality of resistive heating elements and having a portion extending along the perimeter of the substrate. The plurality of resistive heating elements are independently controllable to provide azimuthal temperature control of the heater assembly.

Abstract: A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

Abstract: A gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.

Abstract: The wafer transfer device includes a first supporting mechanism, a second supporting mechanism, a first picking-conveying mechanism and a second picking-conveying mechanism, wherein the first picking-conveying mechanism and the second picking-conveying mechanism include tail end execution parts facing opposite directions. The wafer transfer device further includes a rotating mechanism and a rotating driving part, wherein the first supporting mechanism and the second supporting mechanism are fixedly arranged at the rotating mechanism, and the rotating driving part drives the rotating mechanism to rotate and then drives the first supporting mechanism and the second supporting mechanism to rotate synchronously. The wafer transfer device can extend the picking and conveying range of a wafer, thus facilitating the improvement of the productivity.

Abstract: Provided is a magnetic collet. The magnetic collet includes adsorption rubber including a plurality of individual holes passing therethrough from a contact surface, which is one surface of the adsorption rubber, coming into contact with a semiconductor chip to the other surface thereof, and a metal plate including a common hole which passes therethrough from one surface of the metal plate to the other surface thereof and provides a common passage connected to the individual holes and stacked on the adsorption rubber.

Abstract: One or more embodiments described herein generally relate to methods for chucking and de-chucking a substrate to/from an electrostatic chuck used in a semiconductor processing system. Generally, in embodiments described herein, the method includes: (1) applying a first voltage from a direct current (DC) power source to an electrode disposed within a pedestal; (2) introducing process gases into a process chamber; (3) applying power from a radio frequency (RF) power source to a showerhead; (4) performing a process on the substrate; (5) stopping application of the RF power; (6) removing the process gases from the process chamber; and (7) stopping applying the DC power.

Abstract: An electrostatic chuck includes a ceramic dielectric substrate, a base plate, a bonding part, a gas inlet path, a counterbore part, a ceramic porous part, and an elastic body. The base plate supports the ceramic dielectric substrate. The bonding part is located between the ceramic dielectric substrate and the base plate. The gas inlet path extends through the ceramic dielectric substrate, the base plate, and the bonding part. The gas inlet path includes a first hole part, a second hole part and a third hole part. The first hole part is positioned at the ceramic dielectric substrate. The third hole part is positioned at the bonding part. The counterbore part is located in the first hole part. The ceramic porous part is located in the counterbore part. The elastic body faces an end part of the bonding part at the third hole part side.

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

Abstract: A plate-shaped workpiece holding tool includes a holding base having a joint port coupled to a suction source and a holding surface for holding the plate-shaped workpiece thereon, a first O-ring disposed on the holding surface, a second O-ring disposed on the holding surface radially inwardly of the first O-ring, a suction port that is open in the holding surface between the first O-ring and the second O-ring and held in fluid communication with the joint port, and a liquid supply mechanism for forming a liquid seal between the holding surface and the plate-shaped workpiece radially outwardly of the first O-ring.

Abstract: Embodiments of packaged chamber components and methods of packaging chamber components are provided herein. In some embodiments, a packaged chamber component for use in a process chamber includes: an insert having an annular trench disposed about a raised inner portion, wherein the annular trench is disposed between the raised inner portion and an outer lip, wherein a ledge couples the raised inner portion to the outer lip, wherein the ledge includes a first portion and a second portion disposed radially outward of the first portion, and wherein the second portion includes a resting surface that extends upward and radially outward of an upper surface of the first portion; and a chamber component disposed in the annular trench of the insert and supported by the resting surface such that one or more critical surfaces of the chamber component are spaced apart from the insert.

Abstract: Embodiments of the present disclosure generally relate to lift pins and to apparatus for controlling lift pin movement. In an embodiment, an apparatus for positioning a substrate in a chamber is provided. The apparatus includes a chamber component, a lift pin having a top surface for supporting the substrate and a lift pin shaft and a stopper. The apparatus further includes a compressible element positioned between the chamber component and the stopper, the compressible element further positioned around the lift pin shaft, the lift pin being moveable relative to a substrate transfer plane by movement of a substrate support in contact with the compressible element.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: filling a trench of a stacking structure with a bottom anti-reflection coated material to form a dummy via in the trench, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and etching the dummy via by performing a first etching process and a second etching process.

Abstract: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies, each die comprising one integrated circuit. The process comprises: disposing a coating upon the wafer; removing at least a portion of the coating to expose regions of the wafer, along which the wafer is to be diced, to form a workpiece; disposing the workpiece upon a platen within a processing chamber; plasma treating the workpiece with a set of plasma treatment conditions to etch a portion of the exposed regions of the wafer to form a wafer groove which extends laterally beneath the coating to form an undercut; and plasma etching the workpiece with a set of plasma etch conditions, which are different to the plasma treatment conditions, to etch through the wafer and dice the wafer along the wafer groove.

Abstract: In a processing method for a wafer with a mark formed in an outer peripheral portion thereof, a frame unit having the wafer, a tape, and a ring frame is provided, a set of processing conditions for processing the wafer is selected, and a representative image associated with the set of processing conditions is displayed on a display unit. The ring frame includes a notch formed in an outer periphery thereof. In the frame unit, the mark and the notch are in a positional relationship set in accordance with the set of processing conditions. The positional relationship is presented in the representative image.

Abstract: A method of processing a wafer having a plurality of intersecting streets on a face side thereof with protrusions on the streets includes a holding step of holding a protective sheet of a wafer unit on a holding table, an upper surface heightwise position detecting step of detecting a heightwise position of an upper surface of a reverse side of the wafer along the streets, and a laser beam applying step of applying a laser beam having a wavelength transmittable through the wafer to the wafer from the reverse side thereof along the streets while positioning a focused point of the laser beam within the wafer on the basis of the heightwise position, to thereby form modified layers in the wafer along the streets.

Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.

Abstract: Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

Abstract: A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.

Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.

Abstract: A semiconductor device includes first and second conductive parts, a first bonding wire connecting the first and second conductive parts and having a non-flat portion between opposite ends thereof so that a portion between the opposite ends is away from the first and second conductive parts, a case having a housing space to accommodate the first and second conductive parts, including a sidewall having first to fourth lateral faces surrounding the housing space to form a rectangular shape in a plan view, and a cover disposed on the sidewall, a sealing member filling the case to seal the first bonding wire, and a first stress relaxer for relieving a stress in the first bonding wire. The first bonding wire extends from the second lateral face toward the fourth lateral face, and the first stress relaxer is positioned between the first bonding wire and the first lateral face.