Abstract: A capacitor bank includes a printed circuit board adapted for a first capacitor disposed on a first surface of the printed circuit board and a second capacitor disposed on a second, opposing surface of the printed circuit board. The first and second capacitor are connected to the printed circuit board at surface mounts pads on opposing sides of the printed circuit board that may be in electronic communication with each other. The capacitors may be connected in series or parallel. Multiple printed circuit boards with capacitors on opposing surfaces may include flexible printed circuit board portions to allow the capacitor bank to be folded into an available space.

Abstract: An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes at multilayer body end surfaces and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surfaces and the board side surfaces. One of the board main surfaces is in a vicinity of the electronic element and is joined with one of the multilayer body main surfaces in a vicinity of the interposer board. The interposer board is an alumina board. A maximum length of the interposer board is smaller than a length of the electronic element. A width of the interposer board is smaller than a width of the electronic element.

Abstract: A wiring board includes a base material, a through hole that is formed in the base material, a magnetic member that is embedded in the through hole, and a plating film that covers end faces of the magnetic member exposed from the through hole. The magnetic member includes a conductor wire that is covered by a magnetic body. A wiring board manufacturing method includes forming a through hole in a base material, forming a magnetic member by covering a conductor wire by a magnetic body, embedding the magnetic member in the through hole, and forming a plating film that covers end faces of the magnetic member exposed from the through hole.

Abstract: The present disclosure provides an engaging connection structure and an engaging connection method thereof. The engaging connection structure includes at least one vertical insert portion and an assembly portion. The assembly portion is configured to be assembled at an object, and the vertical insert portion is configured for an insert to be inserted vertically therein. Thus, the engaging connection structure and the engaging connection method thereof of the present disclosure are enabled to provide a required object and an insert with a stable assembly effect.

Abstract: A plurality of driven gears respectively provided on the plurality of nozzle shafts are arranged along the peripheral edges of the drive gears and engaged with the drive gears. Accordingly, the plurality of shafts can be turned by turning the drive gears. Moreover, since the turning of the drive gears, which are scissors gears, is transmitted to the nozzle shafts by the engagement of the drive gears and the plurality of respective driven gears, backlash between the drive gears and the driven gears is suppressed, it is not necessary to provide a backlashless gear (scissors gear) on each of the plurality of nozzle shafts, and the cost of the mounting head is suppressed.

Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

Abstract: Provided is a method for manufacturing a printed circuit board with electronic component, including: mounting an electronic component on an insulating substrate; applying an insulating first coating resin to at least a part of the electronic component; curing the first coating resin; applying an insulating second coating resin to the cured first coating resin; and curing the second coating resin.

Abstract: In a method for manufacturing a circuit board according to an additive manufacturing shaping method, a circuit board manufacturing method and a circuit board manufacturing device that can reduce the influence of thermal stress on a circuit board by reducing the number of heating steps are provided.

Abstract: A supporting structure that supports a flexible screen includes planar supporting portions and a bending supporting portion. The bending supporting portion includes a bending skeleton and a flexible supporting bar coupled to the bending skeleton, and the flexible supporting bar is in direct contact with the flexible screen. The flexible supporting bar includes a supporting portion and a plurality of connecting portions that are distributed at intervals and fastened to the supporting portion. The supporting portion is coupled to the flexible screen. The connecting portions are located on a side of the supporting portion away from the flexible screen, and an end of each of the plurality of connecting portions away from the supporting portion is coupled to the bending skeleton.

Abstract: A display apparatus includes a display module, a rolling cylinder which the display module is wound on and unwound from, and a lifting block unit disposed on a rear surface of the display module. The lifting block unit includes a first block portion, a second block portion coupled to the first block portion and movable up and down with respect to the first block portion, and a third block portion connected to an upper portion of the display module and coupled to the second block portion and movable up and down with respect to the second block portion. The second block portion is inserted into a first accommodation space defined above the first block portion and a second accommodation space defined under the third block portion.

Abstract: A display assembly includes a framework, an electronic display subassembly connected to the framework at an elevated position, and an open, unobstructed, pass-through area located below the electronic display subassembly and within the framework. The pass-through area may assist with sightlines through the display assembly, by way of example. Wiring may be routed from a base along or through upward extending members of the framework.

Abstract: Techniques are disclosed for systems and methods associated with a modular electrical power distribution system with module detection. A modular electrical power distribution system may include a plurality of controllers, a shared serial communication bus between the plurality of controllers, and a module detection signal line coupled through the plurality of controllers. The plurality of controllers may include a master controller, a power input controller, and one or more load controllers disposed between the master controller and the power input controller.

Abstract: A connector module that is provided with an input port and an output port that are configured to be connected to an external member, and is to be mounted on a substrate, the connector module including: a bus bar that is separated from the substrate and connects a terminal of the input port and a terminal of the output port to each other; and an insulating member that is interposed between the bus bar and the substrate.

Abstract: A method and a device for locking an equipment with a rack are presented. The device may include a trigger and an equipment locking mechanism, wherein upon the trigger automatically activates the equipment locking mechanism upon contacting a portion of the rack. The automatic locking initiates when the equipment reaches a desired position within the rack.

Abstract: A cartridge module alignment and mounting system, apparatus and method for mounting of a plurality of removable modules where the modules can be densely packed within the apparatus and where physical alignment of the module is maintained during insertion and removal so that the modules are easily connected or disconnected to a printed circuit board. The system includes an alignment pin affixable to the printed circuit board, and a carrier attachable to an electronic device such as a data storage device. The carrier can include a pin bore configured to receive a portion of the alignment pin thereby removably connecting and aligning the electronic device to the printed circuit board so that a space is defined between adjacent electronic devices. The space allows airflow or fluid flow to pass therebetween increasing heat dissipation of the electronic devices and the printed circuit board.

Abstract: A method for manufacturing networking devices includes providing circuit boards each having an NPU mounted to that circuit board, and respective cable connectors mounted to that circuit board and coupled to that NPU. First networking devices are manufactured by providing one of the circuit boards in a chassis in each first networking device, and cabling at least some of the cable connectors on that circuit board to first subsystem(s) in that first networking device in order to configure that first networking device to perform first functionality. Second networking devices are manufactured by providing a respective one of the circuit boards in a chassis in each second networking device, and cabling at least some of the cable connectors on that circuit board to second subsystem(s) in that second networking device in order to configure that second networking device to perform second functionality that is different than the first functionality.

Abstract: An electronic apparatus includes: a chassis; a substrate housed in the chassis and with a processing device mounted thereon; a speaker device housed in the chassis and having a speaker unit and a speaker box; and a cooling device housed in the chassis and used to cool the processing device. The substrate is placed vertically along the vertical direction of the chassis. The cooling device includes: a fan having air intake ports provided on upper and lower surfaces, exhaust ports provided on side surfaces, and an impeller, and being placed horizontally in the chassis with a rotating shaft of the impeller placed along the vertical direction of the chassis; a fin placed facing the exhaust port of the fan and placed horizontally in the chassis; and a heat pipe with a first end connected to the processing device and a second end connected to the fin.

Abstract: An apparatus cools electronic circuitry. A housing encloses the electronic circuitry and includes a plurality of surfaces, each configured to face an adjacent inner wall of the back box upon the housing being mounted inside the back box. A rear surface faces a rear wall of the inner walls of the back box. A mounting plate is disposed opposite to the rear surface, is in thermal contact with the housing, and faces away from the back box. A touch plate is atop of, and in thermal contact with, the mounting plate. The mounting plate and the touch plate combine to provide a path for conducting heat generated by the electronic circuitry away from the housing and for radiating the heat to ambient air. The mounting plate or the touch plate is made of a higher thermal conductivity material to facilitate conduction of heat away from the housing.

Abstract: Cooling systems having cooling and augmentation loops for electronic components and related methods are disclosed. According to an aspect, a cooling system for an electronic component includes a cooling loop in thermal transfer interface with a first electronic component. The cooling loop is configured to contain a first flow of a cooling liquid between an inlet and an outlet. The cooling system also includes at least one augmentation loop configured to contain a second flow of the cooling liquid and alternately engage and disengage with respect to the cooling loop, such that engaging the augmentation loop to the cooling loop converts a series flow pattern with the first flow of the cooling liquid into a parallel flow pattern of a portion of the first flow of the cooling liquid with the second flow of the cooling liquid, without disconnection of the cooling loop from the inlet and outlet.

Abstract: A liquid cooling device includes a base plate, a cooling body, and a cover plate. The cooling body includes a frame. A cooling layer is provided in the frame and a reflux layer is provided above the cooling layer. The cooling layer is provided with a plurality of cooling channels extending from a center portion of the cooling body to the frame. The reflux layer is provided with a plurality of reflux channels in communication with the plurality of cooling channels. A periphery of the reflux layer is provided with a drainage flow channel in communication with the plurality of the reflux channels. A center portion of the cover plate being provided with a liquid inlet in communication with the plurality of cooling channels, and the cover plate is further provided with a liquid outlet in communication with the drainage flow channel.

Abstract: An immersion cooling system includes a catch pan, a heat-generating electronic device, a housing, and a fluid pump. The housing is positioned around the heat-generating electronic device, and at least part of the housing is positioned above the catch pan. The fluid pump is configured to circulate a working fluid from the catch pan to the housing.

Abstract: An electronic apparatus includes: a heating element; and a plurality of heat pipes that is thermally connected to the heating element. Each of the heat pipes has a cross section having a rectangular shape, a heat receiving surface thermally connected to the heating element, and a side surface orthogonal to the heat receiving surface. The side surfaces of the heat pipes, which are adjacent to each other, are in surface contact with each other.

Abstract: A mobile terminal includes a main board, a heat dissipation layer, a first support, and a housing that are sequentially stacked. A heat generation element is disposed on the main board, and an orthographic projection of the heat generation element on the housing is located in an orthographic projection of the first support on the housing. The heat dissipation layer is disposed in contact with the heat generation element, and an area of an orthographic projection of the heat dissipation layer on the housing is larger than an area of the orthographic projection of the first support on the housing.

Abstract: A data center in an environment has modules. Each module has a housing and an air mover. The housing contains processing devices that generate heat during operation. Each module has an air inlet on a first side of the housing and receives air from the environment. Each module also has an air outlet on a second side of the housing to exhaust air from the housing. At least three modules are spaced apart to form lateral spaces between adjacent modules. The modules form an interior region to receive the exhausted air of the modules. Each air mover generates a pressure differential between a top portion of the interior region and a bottom portion of the interior region using the exhausted air. The lateral spaces reduce the pressure differential between the top portion of the interior region and the bottom portion of the interior region.

Abstract: Systems are provided for a heat exchanger assembly. In one example the system may include a top plate, a fluid inlet and a fluid outlet, a bottom plate coupled to the top plate, a perforated plate positioned between the top plate and the bottom plate having an underside facing the bottom plate and including perforations shaped to generate an impingement jet onto the bottom plate, and at least one of the following: the top plate comprising a portion being inclined with respect to a longitudinal axis of the heat exchanger assembly; the perforated plate being inclined with respect to the longitudinal axis or a lateral axis of the heat exchanger assembly; and the heat exchanger assembly further comprising a flow control plate.

Abstract: The power conversion apparatus includes a housing attached to a roof of a vehicle, a heat-receiving block, and one or more heat pipes. The housing has an opening on the top in the vertical direction, and accommodates electronic components. The electronic components are attached to a first main surface, which is one of the main surfaces of the heat-receiving block. The heat-receiving block is attached to the housing and closes the opening. The one or more heat pipes are attached to a second main surface, which is the other of the main surfaces of the heat-receiving block, extend in a direction away from the heat-receiving block, and accommodate refrigerant therein.

Abstract: Embodiments of the present application provide a display panel and a display device, the display panel includes a flexible screen, an adhesive layer, a first heat dissipation layer, a support layer, and a second heat dissipation layer. Both the first heat dissipation layer and the second heat dissipation layer are disposed as metal heat dissipation layers. By arranging the heat dissipation layers as metal heat dissipation materials, heat formed during operation of the display panel can be quickly transferred and dissipated, thereby effectively improving performance of the display panel.

Abstract: An electronic device includes a first electrical element, a heat dissipation sheet having a heat diffusion member for diffusing the heat generated from the first electrical element, and an anti-shock member arranged to be stacked with at least a part of the heat diffusion member; and a bracket which provides a space for accommodating the heat dissipation sheet. The heat dissipation sheet includes a first area, a second area, and a third area arranged between the first area and the second area.

Abstract: An imaging device according to the present disclosure includes a front case, a rear case, and a shield member. The front case supports an imaging optical unit. The rear case includes an electrically conductive output mechanism configured to output a signal output from the imaging optical unit. The shield member electrically connects the front case and the output mechanism.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a radiation shield that includes a zipper. The radiation shield can include a wall that extends from a support structure of the electronic device, a first portion that is coupled to a cold plate over a radiation source, a second portion that is coupled to the wall, and a zipper that can zip the first portion to the second portion together and can unzip to separate the first portion from the second portion.

Abstract: The present invention provides an electromagnetic wave-absorbing composite material and a manufacturing method therefor, the electromagnetic wave-absorbing composite material comprising: a polymer composite including a refractive index-adjusting material therein; and a plurality of conductive wires formed on at least one surface of the polymer composite, wherein electromagnetic waves reflected in a matching frequency (f) range derived through Mathematical Formulas 1 to 3 described in the present invention are 0.2 dB or less.

Abstract: A differential signal transmission cable includes an insulation layer extending in a longitudinal direction of the differential signal transmission cable, a pair of signal lines extending in the longitudinal direction and buried inside the insulation layer, an intermediate layer covering an outer circumferential surface of the insulation layer, a shield, and catalyst particles. The shield includes an electroless plating layer covering an outer circumferential surface of the intermediate layer. The catalyst particles are dispersed between the intermediate layer and the electroless plating layer.

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

Abstract: The present disclosure provides an anti-fuse type one-time programmable memory cell. The memory cell includes a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate including an active region and an isolation region; in which the gate capacitor includes a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer; in which a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.

Abstract: A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

Abstract: A semiconductor device may include: a gate structure including insulating layers and control gates, which are alternately stacked; a channel layer penetrating the gate structure; floating gates respectively located between the control gates and the channel layer; first blocking patterns respectively located between the control gates and the floating gates; and a second blocking pattern located between the first blocking patterns and the control gates and between the control gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is higher than that of the first blocking patterns.

Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.

Abstract: According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.

Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor disposed within at least one recess(es). The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Abstract: A NAND flash memory and manufacturing method thereof are provided. The NAND flash memory is capable of preventing a short circuit between gates extending along a vertical direction. The NAND flash memory includes a substrate; a plurality of channel stacks formed on the substrate and extending along an X direction; an interlayer dielectric formed between the channel stacks; a plurality of trenches formed apart from each other in the interlayer dielectric and arranged along a Y direction; an insulator stack including a charge storage layer formed to cover sidewalls of each of the trenches; and a plurality of conductive vertical gates elongating along the vertical direction in a space formed by the insulator stack in each of the trenches and extending along the Y direction.

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack and cavities are formed in the hard mask layer. A cladding liner is formed on sidewalls of the cavities in the hard mask layer. Via openings are formed through each layer within the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavities through the alternating stack.

Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.

Abstract: A semiconductor device having a large storage capacity per unit area is provided.

Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.