Electron Beam Patents (Class 117/905)
  • Patent number: 8647436
    Abstract: Isotopically-enriched graphene and isotope junctions are epitaxially grown on a catalyst substrate using a focused carbon ion beam technique. The focused carbon ion beam is filtered to pass substantially a single ion species including a single desired carbon isotope. The ion beam and filtering together provide a means to selectively isotopically-enrich the epitaxially-grown graphene from given carbon precursor and to selectively deposit graphene enriched with different carbon isotopes in different regions.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 11, 2014
    Assignees: Raytheon Company, The Arizona Board of Regents
    Inventors: Delmar L. Barker, William R. Owens, John Warren Beck
  • Patent number: 8591653
    Abstract: A compound semiconductor single-crystal manufacturing device (1) is furnished with: a laser light source (6) making it possible to sublime a source material by directing a laser beam onto the material; a reaction vessel (2) having a laser entry window (5) through which the laser beam output from the laser light source (6) can be transmitted to introduce the beam into the vessel interior, and that is capable of retaining a starting substrate (3) where sublimed source material is recrystallized; and a heater (7) making it possible to heat the starting substrate (3). The laser beam is shone on, to heat and thereby sublime, the source material within the reaction vessel (2), and compound semiconductor single crystal is grown by recrystallizing the sublimed source material onto the starting substrate (3); afterwards the laser beam is employed to separate the compound semiconductor single crystal from the starting substrate (3).
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: November 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Naho Mizuhara, Keisuke Tanizaki, Michimasa Miyanaga, Takashi Sakurada, Hideaki Nakahata
  • Patent number: 7682451
    Abstract: There is disclosed a PBN container in which a conductive film is deposited on a surface of a body formed by depositing PBN (pyrolytic boron nitride), wherein, at least, an angle between a PBN cut face of the body and at least one wall surface adjacent to the PBN cut face is 20°-80°, and a method for producing a PBN (pyrolytic boron nitride) container comprising at least steps of depositing PBN to form a body, processing a PBN cut face of the formed body so that at least, an angle between the PBN cut face and at least one wall surface adjacent to the PBN cut face is 20°-80°, and coating a surface of the processed body with a conductive film. Thus, there can be provided a PBN container excellent in durability where a conductive film is laminated on a surface of a body formed by depositing PBN, and a method for producing the PBN container.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 23, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Noboru Kimura, Takuma Kushihashi
  • Patent number: 7572335
    Abstract: A crystallization apparatus includes an illumination system which illuminates a phase-shift mask and an image-forming optical system arranged in an optical path between the phase-shift mask and a semiconductor film. The semiconductor film is irradiated with a light beam having a light intensity distribution of inverted peak patterns whose light intensity is the lowest in portions corresponding to phase shift sections to form a crystallized semiconductor film. The image-forming optical system is located to optically conjugate the phase-shift mask and the semiconductor film and has an aberration corresponding to the given wavelength range to form a light intensity distribution of inverted peak patterns with no swell of intensity in the middle portion.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: August 11, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Patent number: 7341628
    Abstract: Gallium Nitride layers grown as single crystals by epitaxy such as Hydride Vapor Phase Epitaxy (HVPE) contain large numbers of crystal defects such as hexagonal pits, which limit the yield and performance of opto- and electronic devices. In this method, the Gallium Nitride layer is first coated with an Aluminum layer of approximate thickness of 0.1 microns. Next, Nitrogen is ion implanted through the Aluminum layer so as to occupy mostly the top 0.1 to 0.5 microns of the Gallium Nitride layer. Finally, through a pulsed directed energy beam such as electron or photons, with a fluence of approximately 1 Joule/cm2 the top approximately 0.5 microns are converted to a single crystal with reduced defect density.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 11, 2008
    Inventor: Andreas A. Melas
  • Patent number: 7306670
    Abstract: In the case of the epitaxial growth according to the prior art, a number o strips often have to be produced in a plane in order to restore an area to be repaired. This leads to overlapping and misorientation of the crystalline structures. In the case of the method according to the invention, the strip is of such a width that no overlapping occurs, since the width is adapted to the contour of the area to be repaired.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Beck, Georg Bostanjoglo, Nigel-Philip Cox, Rolf Wilkenhöner
  • Patent number: 7250081
    Abstract: Methods for repair of single crystal superalloys by laser welding and products thereof have been disclosed. The laser welding process may be hand held or automated. Laser types include: CO2, Nd:YAG, diode and fiber lasers. Parameters for operating the laser process are disclosed. Filler materials, which may be either wire or powder superalloys are used to weld at least one portion of a single crystal superalloy substrate.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: July 31, 2007
    Assignee: Honeywell International, Inc.
    Inventors: Yiping Hu, William F. Hehmann, Murali Madhava
  • Patent number: 7153359
    Abstract: A crystalline semiconductor film, the crystalline semiconductor film being formed over an insulative substrate, and including semiconductor crystal grains laterally grown along a surface of the insulative substrate, wherein the laterally-grown semiconductor crystal grains are in contact with each other at grain boundaries, and a distance between adjacent grain boundaries is equal to or smaller than two times a lateral growth distance of the semiconductor crystal grains.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: December 26, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masashi Maekawa, Keiichi Fukuyama, Michinori Iwai, Kohei Tanaka
  • Patent number: 6902617
    Abstract: A method of single crystal welding is provided for the production of a single crystal region (1) on a surface (2) of a moncrystalline substrate (3) by means of an energy beam (4). The method of single crystal welding includes the supply of a coating material (5), the formation of a melt (6) by melting the coating material (5) by means of the energy beam (4) and the melting of a surface layer (71, 72) of the single crystal substrate (3) by the energy beam (4). The characteristic (8) of the energy distribution in the energy beam (4) is set, in this connection, such that the lateral thermal flow (H1) from the melt into the single crystal substrate (3) is minimized.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: June 7, 2005
    Assignee: Sulzer Markets and Technology AG
    Inventor: Jürgen Betz
  • Patent number: 6743292
    Abstract: A thin film structure is provided including a silicon substrate with a layer of silicon dioxide on a surface thereof, and a layer of cubic oxide material deposited upon the layer of silicon dioxide by ion-beam-assisted-deposition, said layer of cubic oxide material characterized as biaxially oriented. Preferably, the cubic oxide material is yttria-stabilized zirconia. Additional thin layers of biaxially oriented ruthenium oxide or lanthanum strontium cobalt oxide are deposited upon the layer of yttria-stabilized zirconia. An intermediate layer of cerium oxide is employed between the yttria-stabilized zirconia layer and the lanthanum strontium cobalt oxide layer. Also, a layer of barium strontium titanium oxide can be upon the layer of biaxially oriented ruthenium oxide or lanthanum strontium cobalt oxide.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 1, 2004
    Assignee: The Regents of the University of California
    Inventors: Quanxi Jia, Paul N. Arendt
  • Patent number: 6589447
    Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Junya Ishizaki, Nobuhiko Noto
  • Patent number: 6344082
    Abstract: Si nanocrystals are formed by irradiating SiO2 substrates with electron beams at a temperature of 400° C. or higher, thereby causing electron-stimulated decomposition reaction. As a result of the said reaction, single crystalline Si nanostructures are fabricated on the SiO2 substrate with good size and positional controllability.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Japan Agency of Industrial Science and Technology as represented by Director General of National Research Institute for Metals
    Inventors: Kazuo Furuya, Masaki Takeguchi, Kazuhiro Yoshihara
  • Patent number: 5814150
    Abstract: In order to form a single-crystalline thin film on a polycrystalline substrate using plasma CVD, a downwardly directed mainly neutral Ne atom current is formed by an ECR ion generator (2). A reaction gas such as silane gas which is supplied from a reaction gas inlet pipe (13) is sprayed onto an SiO.sub.2 substrate (11) by an action of the Ne atom current, so that an amorphous Si thin film is grown on the substrate (11) by a plasma CVD reaction. At the same time, a part of the Ne atom current having high directivity is directly incident upon the substrate (11), while another part thereof is incident upon the substrate (11) after its course is bent by a reflector (12). The reflector (12) is so set that all directions of the parts of the Ne atom current which are incident upon the substrate (11) are perpendicular to densest planes of single-crystalline Si.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: September 29, 1998
    Assignees: Neuralsystems Corporation, Mega Chips Corporation
    Inventors: Toshifumi Asakawa, Masahiro Shindo, Toshikazu Yoshimizu, Sumiyoshi Ueyama
  • Patent number: 5788767
    Abstract: The present invention is a method for using a single SiN layer as a passivation film. The single layer SiN can be strengthened to withstand stress by adjusting the process parameters during formation of the SiN layer. In general, the process can be changed by increasing the low frequency power 5% during the deposition. Alternatively, the pressure of the SiN deposition may be decreased about 20% in pressure.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: August 4, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jun-Cheng Ko, Liang-Tung Tony Chang
  • Patent number: 5409867
    Abstract: After partially crystallizing an amorphous semiconductor deposited on a substrate, the irradition of infrared ray is conducted to grow a polycrystalline semiconductor layer on the crystallized region and the amorphous region by thermal decomposition while the temperature of the crystallized region is kept higher than that of the amorphous region. Since the polycystalline layer is formed of polycystalline grains grown from nuclei of the cystallized region, the crystal grain thereof is large.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: April 25, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Akihiko Asano