Single-crystal Of Complex Geometry (e.g., Patterned, Elo) {c30b 29/66} Patents (Class 117/923)
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Patent number: 11725081Abstract: An organopolysiloxane cured film which can be made thin, has an extremely low number of defects on a surface and inside of the film, and exhibits high dielectric breakdown strength with regard to a load voltage is provided. Also provided are applications thereof and a method of manufacturing. The organopolysiloxane cured film has an average thickness within a range of 1 to 200 ?m. In general, the number of surface defects is 0 to 1, and the number of internal defects is 0 to 20, when measuring the number of surface defects using optical means in an arbitrary position on the organopolysiloxane cured film with a unit area of 15 mm×15 mm. The organopolysiloxane cured film may be obtained by a rolling step in a clean room or the like, or may be obtained by curing between separators provided with a release layer.Type: GrantFiled: July 16, 2019Date of Patent: August 15, 2023Assignee: DOW TORAY CO., LTD.Inventors: Hiroshi Fukui, Yoichi Kaminaga, Takeaki Tsuda
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Patent number: 10690852Abstract: A III-V semiconductor waveguide nanoridge structure having a narrow supporting base with a freestanding wider body portion on top, is disclosed. In one aspect, the III-V waveguide includes a PIN diode. The waveguide comprises a III-V semiconductor waveguide core formed in the freestanding wider body portion; at least one heterojunction incorporated in the III-V semiconductor waveguide core; a bottom doped region of a first polarity positioned at a bottom of the narrow supporting base, forming a lower contact; and an upper doped region of a second polarity, forming an upper contact. The upper contact is positioned in at least one side wall of the freestanding wider body portion.Type: GrantFiled: December 20, 2018Date of Patent: June 23, 2020Assignees: IMEC vzw, Universiteit GentInventors: Joris Van Campenhout, Ashwyn Srinivasan, Bernardette Kunert, Maria Ioanna Pantouvaki
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Patent number: 10680126Abstract: Structures including crystalline material disposed in openings defined in a non-crystalline mask layer disposed over a substrate. A photovoltaic cell may be disposed above the crystalline material.Type: GrantFiled: November 23, 2016Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jizhong Li, Anthony J. Lochtefeld, Calvin Sheen, Zhiyuan Cheng
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Patent number: 10048533Abstract: The disclosure provides a liquid crystal display, including a liquid crystal cell, the liquid crystal cell includes a first substrate, a second substrate and a liquid crystal layer between the first substrate and the second substrate, the first substrate at least includes a transparent base, a metallic wiring disposed on the transparent base towards the liquid crystal layer and a first polarizer disposed on an external surface of the transparent base, the liquid crystal display further includes a solar cell disposed on the transparent base of the first substrate right below the metallic wiring, the first polarizer includes a hollow region revealing the transparent base, the solar cell shelters the hollow region.Type: GrantFiled: July 27, 2016Date of Patent: August 14, 2018Assignee: Wuhan China Star Optoelectronics Technology Co., LtdInventor: Chang Xie
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Patent number: 10032863Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.Type: GrantFiled: April 4, 2016Date of Patent: July 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Daniel Nelson Carothers, Jeffrey R. Debord
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Patent number: 9548417Abstract: An epitaxial structure including an epitaxial substrate, a first buffer layer, a first pattern mask layer, a second buffer layer and a second pattern mask layer. The first buffer layer is disposed on the epitaxial substrate. The first pattern mask layer is disposed on the first buffer layer. The second buffer layer is disposed on the first pattern mask layer and a part of the first buffer layer. The second pattern mask layer is disposed on the second buffer layer. A projection of the first pattern mask layer projected on the first buffer layer and a projection of the second pattern mask layer projected on the first buffer layer cover at least 70% of the total area of the first buffer layer.Type: GrantFiled: July 26, 2015Date of Patent: January 17, 2017Assignee: PlayNitride Inc.Inventors: Yen-Lin Lai, Jyun-De Wu
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Patent number: 9373504Abstract: The present invention relates to a method for manufacturing an epitactic silicon layer made up of crystallites with a size no lower than 20 ?m, including: providing a layer of crystallized silicon the surface of which, being inhomogeneous in terms of the size of the crystallites, is made up of large crystallites with a size no lower than 20 ?m, and small crystallites of a smaller size; forming, on the surface of the inhomogeneous silicon layer, a layer of at least one non-nucleating material for the silicon, the thickness of which is adjusted such to cover the entire outer surface of the small crystallites, while leaving all or part of the outer surface of the large crystallites accessible; and carrying out epitaxial growth of a silicon layer on the surface of the assembly obtained at the end of step, under conditions that are suitable for forming the expected epitactic layer.Type: GrantFiled: May 22, 2013Date of Patent: June 21, 2016Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jean-Paul Garandet, Etienne Pihan
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Patent number: 9330959Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.Type: GrantFiled: June 11, 2014Date of Patent: May 3, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEdInventors: Daniel Nelson Carothers, Jeffrey R. Debord
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Patent number: 8906487Abstract: In a base material with a single-crystal silicon carbide film according to an embodiment of the invention, a plurality of recessed portions is formed on the surface of a silicon substrate, an insulating film including silicon oxide is formed across the surface of the silicon substrate including the inner surfaces of the recessed portions, the top surfaces of side wall portions of recessed portions of the insulating film form flat surfaces, a single-crystal silicon carbide film is joined on the flat surfaces, and the recessed portions below the single-crystal silicon carbide film form holes.Type: GrantFiled: June 30, 2011Date of Patent: December 9, 2014Assignee: Seiko Epson CorporationInventor: Hiroyuki Shimada
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Patent number: 8795431Abstract: A gallium nitride layer is produced using a seed crystal substrate by flux method. The seed crystal substrate 8A includes a supporting body 1, a plurality of seed crystal layers 4A each comprising gallium nitride single crystal and separated from one another, a low temperature buffer layer 2 provided between the seed crystal layers 4A and the supporting body and made of a nitride of a group III metal element, and an exposed layer 3 exposed to spaces between the adjacent seed crystal layers 4A and made of aluminum nitride single crystal or aluminum gallium nitride single crystal. The gallium nitride layer is grown on the seed crystal layers by flux method.Type: GrantFiled: September 20, 2013Date of Patent: August 5, 2014Assignee: NGK Insulators, Ltd.Inventors: Katsuhiro Imai, Makota Iwai, Takanao Shimodaira, Masahiro Sakai, Shuhei Higashihara, Takayuki Hirao
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Patent number: 8119505Abstract: A method of making a group III nitride-based compound semiconductor includes providing a semiconductor substrate comprising group III nitride-based compound semiconductor, polishing a surface of said semiconductor substrate such that said polished surface includes an inclined surface that has an off-angle ? of 0.15 degrees or more and 0.6 degrees or less to one of an a-face, a c-face and an m-face of the semiconductor substrate, providing a stripe-shaped specific region on the polished surface, the specific region comprising a material that prevents the growth of the group III nitride-based compound semiconductor on its surface, and growing a semiconductor epitaxial growth layer of group III nitride-based compound semiconductor on the polished surface of the semiconductor substrate.Type: GrantFiled: March 2, 2010Date of Patent: February 21, 2012Assignees: Toyoda Gosei Co., Ltd., Sumitomo Electric Industries, Ltd.Inventor: Ryo Nakamura
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Patent number: 7837792Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that accelerates the crystallization of silicon, an adverse influence of this metal element can be suppressed. A semiconductor device manufacturing method is comprised of the steps of: forming an amorphous silicon film on a substrate having an insulating surface; patterning the amorphous silicon film to form a predetermined pattern; holding a metal element that accelerates the crystallization of silicon in such a manner that the metal element is brought into contact with the amorphous silicon film; performing a heating process to crystalize the amorphous silicon film, thereby being converted into a crystalline silicon film; and etching a peripheral portion of the pattern of the crystalline silicon film.Type: GrantFiled: September 22, 2004Date of Patent: November 23, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto, Shunpei Yamazaki
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Patent number: 7547359Abstract: An aerosol of a powder composed of helium carrier gas and particles of a hexagonal aluminum nitride is charged through a transfer pipe 3 into a film deposition chamber 4 whose interior is depressurized by gas evacuation using a vacuum pump 5 to maintain a degree of vacuum of 200-8000 Pa during supply of the carrier gas and the aerosol is blown from a nozzle 6 provided on the end of the transfer pipe 3 inside the film deposition chamber 4 to impinge on a substrate fastened to a substrate holder 7 to make the impact force of the particles at collision with the substrate 4 GPa or greater, thereby transforming the crystal structure of the aluminum nitride from hexagonal to cubic to deposit cubic aluminum nitride on the substrate.Type: GrantFiled: March 19, 2004Date of Patent: June 16, 2009Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Atsushi Iwata, Jun Akedo
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Patent number: 7531037Abstract: Disclosed is a macromolecule-crystal forming apparatus and method capable of obtaining a macromolecule crystal in a simplified and efficient manner. The device comprises a first container containing a sample of macromolecule, a second container containing a gel acting as a buffer material during the crystallization of the macromolecule, and a third container containing a precipitant solution having a function of facilitating the aggregation of molecules during the crystallization of the macromolecule. These containers are connected together in a given manner so as to allow the macromolecule sample and the precipitant to be brought into contact with one another through the gel to induce the crystallization of the macromolecule.Type: GrantFiled: November 28, 2005Date of Patent: May 12, 2009Assignee: Japan Aerospace Exploration AgencyInventors: Izumi Yoshizaki, Satoshi Sano, Tomoyuki Kobayashi, Masaru Sato, Moritoshi Motohara, Hiroaki Tanaka, Sachiko Takahashi, Shinichi Shinozaki, Mari Yamanaka, Koji Inaka
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Patent number: 7294201Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations as well as a method of manufacturing a crystal and a method of manufacturing a device with the use thereof are disclosed. On a basal body, formed in order are a base crystal layer of, for example, gallium nitride (GaN), a first mask pattern of, for example, silicon dioxide (SiO2), an intermediate crystal layer of, for example, gallium nitride, a second mask pattern of, for example, silicon dioxide, and a top crystal layer of, for example, gallium nitride. The first and second mask patterns have stripes arranged at least in one direction at unequally spaced intervals. The stripes are different in pitch from pattern to pattern. Thus, the mask patterns at least partly overlie one another in the direction of the thickness of the crystal layers.Type: GrantFiled: November 30, 2000Date of Patent: November 13, 2007Assignee: Sony CorporationInventor: Etsuo Morita
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Patent number: 6830617Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that promotes the crystallization of silicon, an influence of this metal element can be suppressed. A nickel element 104 is retained in contact with a surface of an amorphous silicon film 103 patterned to form a predetermined pattern in such a manner that the metal element is brought into contact with the amorphous silicon film 103 patterned to form a predetermined pattern. Next, the crystalline silicon film 105 is formed by a heat treatment. At this time, the nickel element is segregated in the edge region of the pattern. Further, a crystalline silicon film 100 having no region to which the metal element concentrated by patterning using a mask 107. By using this crystalline silicon film 100 as an active layer, the thin film transistor is fabricated.Type: GrantFiled: August 1, 1996Date of Patent: December 14, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto, Shunpei Yamazaki
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Patent number: 6780241Abstract: The present invention provides methods of manufacturing and integrating optical devices. In one embodiment, a method of integrating an optical device may include forming a first device over a substrate, and forming a second device over the substrate and adjacent the first device with a deposition gas having an etchant selective to a deposited component of the deposition gas.Type: GrantFiled: September 26, 2002Date of Patent: August 24, 2004Assignee: TriQuint Technology Holding Co.Inventors: Abdallah Ougazzaden, Justin Larry Peticolas, Jr., Andrei Sirenko
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Patent number: 6758900Abstract: A micro three-dimensional structure capable of producing a micro three-dimensional structure (micrometer-to nanometer-order outer shape) having a complicated structure, a production method therefor and production device therefor are provided. In the production method for the micro three-dimensional structure, performed are the step of irradiating a focused ion beam (4) to a sample (1) while supplying a material gas (3) to form a first-layer deposit (5), the step of releasing secondary electrons (6) from the first-layer deposit (5) hit by ions to allow the secondary electrons (6) to form a terrace (7) on the first-layer deposit (5), a step of deflecting the focused ion beam (4) in a desired direction of the terrace (7) based on a set amount from a focal position controlling apparatus, a step of forming a second-layer deposit (8) in a deflected position on the terrace (7) based on the deflection amount, and a step of repeating the above steps to form a set micro three-dimensional structure.Type: GrantFiled: August 22, 2002Date of Patent: July 6, 2004Assignee: NEC CorporationInventor: Shinji Matsui
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Patent number: 6597492Abstract: A method of fabricating an invertedly poled domain structure having alternating sections of opposite electric polarities, from a ferroelectric crystal wafer (1) having two opposite polar surfaces, comprises patterning at least one of the two polar surfaces of the wafer to comprise a plurality of alternating discrete regions, of which first regions are adapted for and second regions are protected from the direct application thereto of an electric contact; applying to both polar surfaces of the wafer electrically conducting electrodes (10 and 11) so that the first regions are in direct contact with the electrodes and the second regions are protected from such a contact; and applying to the electrodes an electrical field (20) of the intensity E. The electrical field is applied to the wafer at a working temperature by heater/cooler (15).Type: GrantFiled: April 28, 2000Date of Patent: July 22, 2003Assignees: The State of Israel Atomic Energy Commission Soreq Nuclear Research Center, Ramot University Authority for Applied Research & Industrial Development Ltd.Inventors: Gil Rosenman, Alexander Skliar, Moshe Oron, David Eger, Mordechai Katz
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Patent number: 6368405Abstract: A single crystal silicon growth apparatus, comprising: a chamber where a silicon substrate is to be inserted; a heat source for rising the temperature in an interior of the chamber; a cooling line for rapidly dropping the temperature in the interior of the chamber; a gas sprayer for providing a source gas and a purge gas inside the chamber; a gas inflow line connected to the gas sprayer for inflowing the source gas and the purge gas into the gas sprayer; and a gas exhausting line for maintaining the interior of the chamber with a vacuum.Type: GrantFiled: December 13, 1999Date of Patent: April 9, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Seung Woo Shin
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Patent number: 6270573Abstract: A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a <1{overscore (1)}00> direction is effective to prevent an occurrence of twin.Type: GrantFiled: April 26, 1999Date of Patent: August 7, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi
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Patent number: 6159284Abstract: A process and a device will produce a cylindrical single crystal of semicuctor material with the smallest possible alignment error of the crystal lattice. A process for cutting semiconductor wafers from two or more such single crystals is by means of wire sawing. The process for producing the single crystal is as follows: (a) a single crystal with an alignment error of the crystal lattice equal to at most 1.5.degree.Type: GrantFiled: May 25, 1999Date of Patent: December 12, 2000Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AGInventors: Hans Olkrug, Holger Lundt, Christian Andrae, Josef Frumm
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Patent number: 6110278Abstract: A template for seeding growth of a desired single-crystal material (e.g., Si, GaAs) is created by passing through a monocrystalline channelizing mask, in a channelizing direction thereof, at least one of a nucleation-friendly species (e.g., Si, Ga) and a knock-off species (e.g., Ar, F) for respective implant of a nucleation-friendly species within or removal of a nucleation-unfriendly material (e.g., SiO.sub.2) of a supplied substrate. The desired single-crystal material is then grown in epitaxial-like manner from the thus-formed seeding-template. In one embodiment, silicon ions are projected through a monocrystalline silicon mask of a selected crystal orientation ((100), or (111)) in its channelizing direction so as to implant the silicon ions in a silicon dioxide layer of a supplied substrate according to the selected crystal orientation of the channelizing mask. Monocrystalline silicon is then epitaxially grown on top of the silicon dioxide layer with the same crystal orientation.Type: GrantFiled: August 10, 1998Date of Patent: August 29, 2000Inventor: Arjun N. Saxena
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Patent number: 6103019Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.Type: GrantFiled: February 18, 1998Date of Patent: August 15, 2000Inventor: Arjun Saxena
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Patent number: 6036773Abstract: A Group III atomic layer required for fabrication of a semiconductor quantum nanostructure is grown to be properly restricted to a monolayer.A substrate is configured to have a fast-growth surface portion where growth of a Ga atomic layer proceeds at a relatively high rate and a slow-growth surface portion where the growth of the Ga atomic layer proceeds at a relatively low rate. Ga atoms are supplied to the fast-growth surface portion in an amount not less than that which grows one layer of the Group III atoms. Excess Ga atoms on the fast-growth surface portion are allowed to migrate to the slow-growth surface portion by surface migration, thereby growing only one layer of the Ga atoms on the fast-growth surface portion.Type: GrantFiled: March 27, 1997Date of Patent: March 14, 2000Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & IndustryInventors: Xue-Lun Wang, Mutsuo Ogura
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Patent number: 6030452Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate having a step on a surface thereof and growing a group III-V compound semiconductor layer on a surface of the semiconductor substrate by metal organic vapor phase epitaxy using a source gas added with halogenated hydrocarbon containing one or two halogen atoms per one molecule. The surface of a substrate with a step thereon can be planarized by depositing an embedding layer on a lower level area.Type: GrantFiled: May 24, 1995Date of Patent: February 29, 2000Assignee: Fujitsu LimitedInventor: Tatsuya Takeuchi
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Patent number: 5943571Abstract: For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.Type: GrantFiled: June 26, 1997Date of Patent: August 24, 1999Assignee: Siemens AktiengesellschaftInventors: Herbert Schaefer, Martin Franosch, Reinhard Stengl, Volker Lehmann, Hans Reisinger, Hermann Wendt
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Patent number: 5935323Abstract: Articles with a tenaciously adherent diamond coating are made by forming a diamond coating on a base material by vapor-phase synthesis without causing any warpage of the coating. The diamond coating layer is formed on the surface of a base material having a number of pores formed by electric discharge or laser beams and having a depth of 0.0001-0.2 mm and a diameter of 0.001-0.02 mm. The pores may be connected to one another to form a groove. Suitable examples of the base material include molybdenum, tungsten, silicon, tungsten carbide, silicon carbide, silicon nitride, and cemented carbide mainly comprising tungsten carbide and cobalt and/or nickel.Type: GrantFiled: March 20, 1998Date of Patent: August 10, 1999Assignee: Toyo Kohan Co., Ltd.Inventors: Michifumi Tanga, Takahiro Kitagawa
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Patent number: 5865888Abstract: A semiconductor device epitaxial layer lateral growth rate control method using CBr.sub.4 gas involves regulating an epitaxial layer lateral growth rate in accordance with the CBr.sub.4 amount doped into the epitaxial layer during the epitaxial layer growth occurring on a patterned GaAs substrate by means of a metalorganic chemical vapor deposition (MOCVD) process. The lateral growth rate may be regulated by varying the growth temperature and the V/III doping ratio.Type: GrantFiled: July 22, 1996Date of Patent: February 2, 1999Assignee: Korea Institute of Science and TechnologyInventors: Suk-Ki Min, Moo sung Kim, Seong-Il Kim
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Patent number: 5849077Abstract: A method of growing epitaxial regions comprising the steps of providing a silicon substrate, forming a patterned oxide layer having a planar upper surface on the substrate, the oxide layer having an aperture therein extending to the substrate, forming a layer of silicon in the aperture extending above the surface of the oxide layer and removing the portion of the layer of silicon extending above the surface of the oxide layer. The sidewalls of the oxide layer defining the aperture are outwardly sloped in the direction of the upper surface. The layer of silicon is formed by a procedure which forms crystalline silicon in the aperture and forms no silicon over the oxide layer. The portion of the layer of silicon extending above the surface of the oxide layer is removed by a chemical-mechanical polishing operation. In addition, to provide auto-alignment, the layer of oxide is selectively etched relative to the layer of silicon to provide a step at the interface of the layer of oxide and the layer of silicon.Type: GrantFiled: June 14, 1996Date of Patent: December 15, 1998Assignee: Texas Instruments IncorporatedInventor: Danny J. Kenney
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Patent number: 5746826Abstract: Utilizing rugged pattern of atomic size present on a crystalline substrate of a semiconductor such as silicon or selenium or the like, a microstructure body is produced on the substrate by forming a layer of a first element of one monolayer or less by arranging at the position of the substrate most stable in energy formed by ruggedness the atoms of the first element such as gold, silver, copper, nickel, palladium, platinum or an element of group IV and then depositing successively atoms of at least one second element of group III, group IV and group V on only at a part of the surface of the substrate on which said layer of one monolayer or less by vapor deposition, sputtering or the like.Type: GrantFiled: December 2, 1994Date of Patent: May 5, 1998Assignee: Hitachi, Ltd.Inventors: Tsuyoshi Hasegawa, Shigeyuki Hosoki, Makiko Kohno, Masakazu Ichikawa, Hitoshi Nakahara, Toshiyuki Usagawa
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Patent number: 5741360Abstract: In a method of selectively growing a crystal of a compound semiconductor layer which is composed of gallium and arsenic, a selective growth is selectively carried out on a substrate by using a combination of metallic gallium and a reactive gas, such as trisdimethylminoarsine, which includes a metallic compound of arsenic specified by at least one amine. The combination may includes organometallic gallium, such as trimethylgallium, triethylgallium instead of the metallic gallium. Such a combination serves to selectively deposit the compound semiconductor layer only on an exposed portion uncovered with a mask. Any other compound semiconductor layer may be selectively deposited on the exposed portion. The exposed portion may be composed of GaAs, AlGaAs, or InGaAs.Type: GrantFiled: August 11, 1995Date of Patent: April 21, 1998Assignee: Optoelectronics Technology Research CorporationInventors: Shigeo Goto, Yasuhiko Nomura, Yoshitaka Morishita, Seikoh Yoshida, Masahiro Sasaki
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Patent number: 5718761Abstract: A method of forming a crystalline compound semiconductor film comprises introducing into a crystal forming space housing a substrate on which a non-nucleation surface (S.sub.NDS) having a smaller nucleation density and a nucleation surface (S.sub.NDL) having a fine surface area sufficient for crystal growth only from a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (NDs) of the non-nucleation surface (S.sub.NDS) are arranged adjacent to each other an organometallic compound (VI) for supplying an element belonging to the group VI of Periodic Table represented by the general formula R.sub.1 --X.sub.n --R.sub.2 wherein n is an integer of 2 or more; R.sub.1 and R.sub.Type: GrantFiled: April 17, 1996Date of Patent: February 17, 1998Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Jun-ichi Hanna, Isamu Shimizu
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Patent number: 5610095Abstract: A fabrication technique for improved dielectric isolation of adjacent, electronic devices or electrically controllable optical devices provides an inter-device resistance in excess of 1 M.OMEGA.. Strips of a silicon oxide material, such as SiO.sub.2, are formed between the devices after device formation but prior to regrowth of an electrically conductive cap layer and subsequent metallization. The presence of the SiO.sub.2 strips prevents regrowth of the cap layer between the adjacent devices.Type: GrantFiled: August 31, 1994Date of Patent: March 11, 1997Assignee: Lucent Technologies Inc.Inventor: Martin Zirngibl
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Patent number: 5591666Abstract: A method of fabricating semiconductor devices including defining an area on the surface of a substrate, selectively growing, on the area, a crystalline material with at least one defined crystallographic facet, and selectively growing a semiconductor device on the crystallographic facet. In a second embodiment, an area is defined on the surface of a substrate and chemical beam epitaxy is used to selectively grow, on the area, a layer of indium arsenide with at least one defined crystallographic facet.Type: GrantFiled: August 7, 1995Date of Patent: January 7, 1997Assignee: MotorolaInventors: Kumar Shiralagi, Raymond K. Tsui, Herbert Goronkin
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Patent number: 5582641Abstract: A crystal article comprises a substrate and single crystals provided on said substrate, with the shape of the contacted surface of said single crystals with said substrate being n-gonal (provided that n.gtoreq.5) or circular.Type: GrantFiled: May 22, 1995Date of Patent: December 10, 1996Assignee: Canon Kabushiki KaishaInventor: Nobuhiko Sato
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Patent number: 5525536Abstract: A SOI substrate has a first insulating film formed on a semiconductor substrate. A first opening is formed thereon and a dummy layer is formed on the first opening and the first insulating film. A second opening is formed in the dummy layer and a second insulating film is formed and the dummy layer is removed by etching through the third opening to form a cavity. A semiconductor crystal layer is epitaxially grown within the cavity with use of the semiconductor substrate as a seed. The second insulating film is then removed from the semiconductor crystal layer.Type: GrantFiled: April 13, 1994Date of Patent: June 11, 1996Assignee: Rohm Co., Ltd.Inventor: Sigeyuki Ueda
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Patent number: 5518953Abstract: A semiconductor device is manufactured by forming an epitaxial layer (22) insulated from a silicon substrate (2), and forming a device in the epitaxial layer (22). On the semiconductor substrate (2), a silicon dioxide layer (4) is formed (FIG. 2A). Then the silicon dioxide layer (4) is provided with openings (14) (FIG. 2D). Silicon carbide is grown until it protrudes from the openings (14) to thereby form a silicon carbide seed crystal layer (16) (FIG. 2E). Next, oxidation is carried out, allowing a field oxide layer (20) to be connected at the portion under the openings (14) and the silicon carbide seed crystal layer (16) to be insulated from the silicon substrate (2). Thereafter, epitaxial growth is effected from the silicon carbide seed crystal layer (16). The growth is stopped before silicon grown layers (22) connect to one another, thus obtaining epitaxially grown layers (22) having regions which are separate from one another. The MOS device is formed in this epitaxially grown layer (22).Type: GrantFiled: March 15, 1994Date of Patent: May 21, 1996Assignee: Rohm Co., Ltd.Inventor: Hidemi Takasu
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Patent number: 5482002Abstract: A microprobe is provided which comprises a single crystal provided on a part of one main surface of a substrate or a part of a thin film formed on one main surface of the substrate. The microprobe may have a single crystal having an apex portion surrounded by facets having a specific plane direction and comprising a specific crystal face. The method for preparing the microprobe and an electronic device employing the microprobe also provided which is useful for recording and reproducing.Type: GrantFiled: July 8, 1993Date of Patent: January 9, 1996Assignee: Canon Kabushiki KaishaInventors: Hisaaki Kawade, Haruki Kawada, Kunihiro Sakai, Hiroshi Matsuda, Yuko Morikawa, Yoshihiro Yanagisawa, Tetsuya Kaneko, Toshimitsu Kawase, Hideya Kumomi, Hiroyasu Nose, Eigo Kawakami
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Patent number: 5432120Abstract: For producing a laterally limited, single-crystal region on a substrate, for example the collector of a bipolar transistor or the active region of a MOS transistor, a mask layer having an opening is produced on the surface of a substrate. The surface of the substrate is exposed within the opening. The cross-section of the opening parallel to the surface of the substrate at the surface of the substrate projects laterally beyond that cross-section at the surface of the mask layer. The sidewall of the opening proceeds essentially perpendicularly relative to the surface of the substrate in the region of the surface of the mask layer and has a step-shaped profile in cross-section perpendicularly relative to the surface of the substrate. The single-crystal region is formed by selective epitaxy within the opening.Type: GrantFiled: November 19, 1993Date of Patent: July 11, 1995Assignee: Siemens AktiengesellschaftInventors: Thomas Meister, Reinhard Stengl
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Patent number: 5388548Abstract: A method of fabricating a plurality of optoelectronic components on a semiconductor substrate, each optoelectronic component comprising several layers grown in a reactor. Every layer is being grown under a predetermined individual pressure. The active layers of all the components are lying substantially at the same height. Control of the pressure in the reactor during growth allows the thickness of the layer grown to be constant or to vary over the substrate area.Type: GrantFiled: April 11, 1994Date of Patent: February 14, 1995Assignee: Interuniversitair Micro-Elektronica VZWInventors: Geert F. M. Coudenys, Piet P. A. R. Demeester
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Patent number: 5363800Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.Type: GrantFiled: November 9, 1992Date of Patent: November 15, 1994Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: David J. Larkin, Powell, J. Anthony
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Patent number: 5310446Abstract: A method for producing a semiconductor film comprising steps of: preparing a first substrate and a second substrate; superposing the first substrate on the second substrate to form an assembly of combined substrates; applying energy to the assembly of combined substrates to melt a portion within the assembly to form a molten portion therein; cooling the molten portion to crystallize the portion to form a single crystal structure therein; and separating the first substrate from the second substrate. The method makes it possible to control the crystal axis orientation of the recrystallized single crystal structure.Type: GrantFiled: July 13, 1992Date of Patent: May 10, 1994Assignee: Ricoh Company, Ltd.Inventors: Junichi Konishi, Kouichi Maari, Toshihiko Taneda, Akiko Kishimoto