Silicon From Solid Or Gel State {c30b 29/06} Patents (Class 117/930)
-
Patent number: 8975093Abstract: The instant disclosure relates to a device and method for recrystallising a silicon wafer or a wafer comprising at least one silicon layer. The silicon wafer or the at least one silicon layer of the wafer is totally molten.Type: GrantFiled: July 22, 2010Date of Patent: March 10, 2015Assignee: S'TileInventor: Alain Straboni
-
Patent number: 8834627Abstract: Silicon single crystals are grown by a method of remelting silicon granules, by crystallizing a conically extended section of the single crystal with the aid of an induction heating coil arranged below a rotating plate composed of silicon; feeding inductively melted silicon through a conical tube in the plate, the tube enclosing a central opening of the plate and extending below the plate, to a melt situated on the conically extended section of the single crystal in contact with a tube end of the conical tube, wherein by means of the induction heating coil below the plate, sufficient energy is provided to ensure that the external diameter of the tube end is not smaller than 15 mm as long as the conically extended section of the single crystal has a diameter of 15 to 30 mm.Type: GrantFiled: October 28, 2010Date of Patent: September 16, 2014Assignee: Siltronic AGInventors: Wilfried von Ammon, Ludwig Altmannshofer, Martin Wasner
-
Patent number: 8734583Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.Type: GrantFiled: April 4, 2006Date of Patent: May 27, 2014Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
-
Patent number: 8252404Abstract: Disclosed are high resistivity silicon wafers, wherein the interstitial oxygen concentration thereof is 8×1017 atoms/cm3 (ASTM F121-1979) or less, BMD (Bulk Micro Defect) density—oxygen precipitate within wafer—is 5×107 pieces/cm3 or less, and an electric resistivity thereof is 100 ?·cm or more. And further disclosed are high resistivity silicon wafers having an electric resistivity of 100 ?·cm or more, which are cut from crystal region where no COP (Crystal Originated Particle) exist, and in which neither COP (Crystal Originated Particle) nor oxygen precipitate exist at the area from wafer surface to the depth of 5 ?m or more owing to high temperature treatment. It is preferable that, in said high resistivity wafers, carbon concentration in wafers is 1×1016 atoms/cm3 or more (ASTM F123-1981), and/or nitrogen concentration is 1×1013 atoms/cm3 or more.Type: GrantFiled: November 12, 2004Date of Patent: August 28, 2012Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Shinsuke Sadamitsu, Masataka Hourai
-
Patent number: 7955582Abstract: A method for producing crystallized silicon according to the EFG process by using a shaping part, between which part and a silicon melt, crystallized silicon grows in a growth zone. Inert gas and at least water vapor are fed into the silicon melt and/or growth zone, by means of which the oxygen content of the crystallized silicon is increased. From 50 to 250 ppm of vapor water is added to the inert gas, and the inert gas has an oxygen, CO and/or CO2 content of less than 20 ppm total.Type: GrantFiled: December 14, 2007Date of Patent: June 7, 2011Assignee: Schott Solar GmbHInventors: Albrecht Seidl, Ingo Schwirtlich
-
Patent number: 7497906Abstract: A seed crystal fixing apparatus for fixing the seed crystal on the seed crystal setting part of a reaction vessel with interposition of the adhesive, has a chamber configured to place the seed crystal setting part and form a hermetic atmosphere within the chamber; and a pressure part placed within the chamber for uniformly applying a pressure on the entire surface of the seed crystal.Type: GrantFiled: March 8, 2007Date of Patent: March 3, 2009Assignee: Bridgestone CorporationInventors: Daisuke Kondo, Takuya Monbara
-
Patent number: 7413430Abstract: The upper block 12 contacts the bearing block 20, and the bearing block 20 is coupled to the upper plate 21. The upper block 12 has a protruding part 22 on the upper surface that is worked into a convex surface with a radius of R1, and the bearing block 20 has a recessed part 23 in the undersurface that is worked into a concave surface with a radius of R2 (R2>R1). As a result of such a construction being used, the pressing surface of the upper pressing plate 15 always conforms to the surface of the quartz crystal substrate 11 during pressing, so that a uniform load is applied to the quartz crystal substrate 11. As a result, the surface of the quartz crystal can be uniformly pressed in the hot pressing method.Type: GrantFiled: September 18, 2003Date of Patent: August 19, 2008Assignee: National Institute for Materials ScienceInventors: Sunao Kurimura, Masaki Harada
-
Patent number: 7300516Abstract: When a laser beam is radiated on a semiconductor film under appropriate conditions, the semiconductor film can be crystallized into single crystal-like grains connected in a scanning direction of the laser beam (laser annealing). The most efficient laser annealing condition is studied. When a length of one side of a rectangular substrate on which a semiconductor film is formed is b, a scanning speed is V, and acceleration necessary to attain the scanning speed V of the laser beam relative to the substrate is g, and when V=(gb/5.477)1/2 is satisfied, a time necessary for the laser annealing is made shortest. The acceleration g is made constant, however, when it is a function of time, a time-averaged value thereof can be used in place of the constant.Type: GrantFiled: October 13, 2004Date of Patent: November 27, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Koichiro Tanaka
-
Patent number: 7261778Abstract: Rectangular protruding parts 2 are formed on the surface of one side of a quartz crystal substrate 1; these protruding parts 2 are formed as aggregates of rectangular protruding parts 4 of an even finer pattern. Recessed parts 5 which are lower than the surfaces of the protruding parts 4 are formed between the protruding parts 4; however, the width of these recessed parts 5 is narrow, so that when the protruding parts 4 are viewed on the macroscopic scale, numerous protruding parts 4 are aggregated, and appear to form single protruding parts 2. Such a quartz crystal substrate 1 is clamped between heater blocks from above and below, and the temperature of the quartz crystal substrate is elevated. At the point in time at which this temperature reaches a desired temperature, the substrate 1 is pressed by means of a press. Consequently, stress acts only on the portions corresponding to the protruding parts 4, so that the crystal axis components are inverted only in these portions.Type: GrantFiled: September 18, 2003Date of Patent: August 28, 2007Assignee: National Institute for Materials ScienceInventors: Sunao Kurimura, Masaki Harada
-
Patent number: 7232488Abstract: The present invention relates to a method of fabrication of a substrate for an epitaxial growth. A relaxed epitaxial base layer is obtained on an auxiliary substrate. The invention allows the fabrication of substrates with a more efficient epitaxial growth of a material with a desired lattice parameter on another material with a different lattice parameter. The material can be grown with a high thermodynamic and crystallographic stability. At least a part of the epitaxial base layer is transferred onto a carrier substrate, forming a base substrate, and growing the material of the epitaxial base layer is further grown on the carrier substrate.Type: GrantFiled: April 20, 2004Date of Patent: June 19, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Takeshi Akatsu, Cecile Aulnette, Bruno Ghyselen
-
Patent number: 7226504Abstract: A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm?2 to 5·1016 cm?2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.Type: GrantFiled: January 31, 2002Date of Patent: June 5, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-Shen Maa, Douglas James Tweet, Tingkai Li, Jong-Jan Lee, Sheng Teng Hsu
-
Patent number: 7214903Abstract: An apparatus and method for heating materials or substances in an oven at an oven temperature below their melting and/or vaporization points to either melt and/or vaporize the substance. Substances are inserted into a substantially spherical envelope. The envelope is sealed at a preset pressure. The solid is heated in an oven at an oven temperature substantially below the melting or vaporization temperature of the substance at the preset pressure for a time sufficient to either melt or vaporize the substance.Type: GrantFiled: November 23, 2005Date of Patent: May 8, 2007Assignee: CZ Technologies, Inc.Inventor: Susana Curatolo
-
Patent number: 7161110Abstract: An apparatus and method for heating materials or substances in an oven at an oven temperature below their melting and/or vaporization points to either melt and/or vaporize the substance. Substances are inserted into a substantially spherical envelope. The envelope is sealed at a preset pressure. The solid is heated in an oven at an oven temperature substantially below the melting or vaporization temperature of the substance at the preset pressure for a time sufficient to either melt or vaporize the substance.Type: GrantFiled: January 7, 2004Date of Patent: January 9, 2007Assignee: CZT, Inc.Inventor: Susana Curatolo
-
Patent number: 7118789Abstract: A silica glass crucible is manufactured by introducing into a rotating crucible mold bulk silica grain to form a bulky wall including a bottom wall and a side wall. After heating the interior of the mold to begin to fuse the bulk silica grains, an inner silica grain, doped with aluminum, is introduced. The heat at least partially melts the inner silica grain, allowing it to fuse to the wall to form an inner layer. The crucible is cooled, the fused silica grains forming nuclei of crystalline silica within the inner layer.Type: GrantFiled: July 16, 2001Date of Patent: October 10, 2006Assignee: Heraeus Shin-Etsu AmericaInventors: Katsuhiko Kemmochi, Robert O. Mosier, Paul G. Spencer
-
Patent number: 6997985Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.Type: GrantFiled: December 18, 1996Date of Patent: February 14, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang, Toru Takayama, Hideki Uochi
-
Patent number: 6878451Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment, which is a factor for increasing the number of production steps and production costs.Type: GrantFiled: March 11, 2003Date of Patent: April 12, 2005Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo
-
Patent number: 6733584Abstract: To provide a method of promoting quality of crystals and increasing growth rate in a process of carrying out crystal growth in a horizontal direction of an amorphous silicon film by using a catalyst element expediting crystallization, in respect of the amorphous silicon film for carrying out horizontal growth by using a catalyst element of nickel or the like, irregularities of a matrix (underlayer film or substrate) in contact with the amorphous silicon film are made smaller than the film thickness of the amorphous silicon film by which crystal growth occurs substantially entirely by the catalyst element and interruption of growth caused by natural crystallization or the irregularities of a matrix can be prevented.Type: GrantFiled: December 22, 1997Date of Patent: May 11, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hisashi Ohtani
-
Patent number: 6610142Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400 to 650° C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.Type: GrantFiled: November 24, 1997Date of Patent: August 26, 2003Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Hongyong Zhang, Shunpei Yamazaki, Yasuhiko Takemura
-
Patent number: 6558802Abstract: A hybrid silicon-on-silicon substrate. A thin film (2101) of single-crystal silicon is bonded to a target wafer (46). A high-quality bond is formed between the thin film and the target wafer during a high-temperature annealing process. It is believed that the high-temperature annealing process forms covalent bonds between the layers at the interface (2305). The resulting hybrid wafer is suitable for use in integrated circuit manufacturing processes, similar to wafers with an epitaxial layer.Type: GrantFiled: February 29, 2000Date of Patent: May 6, 2003Assignee: Silicon Genesis CorporationInventors: Francois J. Henley, Nathan W. Cheung
-
Patent number: 6544332Abstract: A method for producing a silicon single crystal in accordance with CZ method, characterized in that before producing the crystal having a predetermined kind and concentration of impurity, another silicon single crystal having the same kind and concentration of impurity as the crystal to be produced is grown to thereby determine an agglomeration temperature zone of grown-in defects thereof, and then based on the temperature, growth condition of the crystal to be produced or temperature distribution within a furnace of a pulling apparatus is set such that a cooling rate of the crystal for passing through the agglomeration temperature zone is a desired rate to thereby produce the silicon single crystal. A silicon single crystal produced in accordance with the above method, characterized in that a density of LSTD before subjecting to heat treatment is 500 number/cm2 or more and the average defect size is 70 nm or less.Type: GrantFiled: April 26, 2001Date of Patent: April 8, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Makoto Iida, Masanori Kimura, Hiroshi Takeno, Yoshinori Hayamizu
-
Patent number: 6358313Abstract: A method of manufacturing a crystalline silicon base semiconductor thin film on a substrate, includes the steps of forming a thin film primarily made of silicon on the substrate by forming plasma of a film material gas containing at least a silicon base gas at the vicinity of the substrate; and crystallizing the silicon in the thin film primarily made of the silicon by emitting excited particles produced from an excited particle material gas to the substrate. At least one of the film material gas and the excited particle material gas contains an impurity gas for forming the silicon semiconductor, and thereby the crystalline silicon base semiconductor thin film is formed on the substrate.Type: GrantFiled: December 22, 1999Date of Patent: March 19, 2002Assignees: Sharp Kabushiki Kaisha, Nissin Electric Co., Ltd.Inventors: Shuhei Tsuchimoto, Hirohisa Tanaka, Kiyoshi Ogata, Hiroya Kirimura
-
Patent number: 6350314Abstract: A process for producing nitrogen-doped semiconductor wafers has the nitrogen being derived from a dopant gas which contains NH3. The process includes pulling a single crystal from a melt of molten semiconductor material, feeding the dopant gas to the semiconductor material, and cutting the nitrogen-doped semiconductor wafers off the pulled single crystal. The dopant gas is fed to the semiconductor material at most until pulling begins for that part of the single crystal from which the semiconductor wafers are cut.Type: GrantFiled: August 31, 2000Date of Patent: February 26, 2002Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AGInventors: Wilfried Von Ammon, Herbert Weidner, Dirk Zemke, Christoph Frey
-
Patent number: 6340393Abstract: In synthesizing a diamond by a vapor-phase growth method, a sputtering method, or a high-pressure and high-temperature synthesis method, N, P or As as an n-type dopant, and H as a p-type dopant are simultaneously doped in a crystal to form a donor-acceptor pair in the crystal, to thereby synthesize a transparent n-type diamond having low resistance.Type: GrantFiled: March 7, 2000Date of Patent: January 22, 2002Assignee: Japan Science and Technology CorporationInventor: Hiroshi Yoshida
-
Patent number: 6284384Abstract: This invention is directed to a novel a single crystal silicon wafer. The wafer comprises: (a) two major generally parallel surfaces (ie., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.Type: GrantFiled: February 16, 1999Date of Patent: September 4, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Gregory M. Wilson, Jon A. Rossi, Charles C. Yang
-
Patent number: 6217647Abstract: To produce monocrystalline layers of conducting or semiconducting materials on porous monocrystalline layers of the same material in a reproducible and time-saving manner, a method is provided which involves applying an amorphous layer of the same material to the porous material and converting the amorphous layer to a monocrystalline layer by tempering.Type: GrantFiled: January 21, 1999Date of Patent: April 17, 2001Assignee: Robert Bosch GmbHInventors: Franz Laermer, Wilhelm Frey
-
Patent number: 6180220Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.Type: GrantFiled: February 25, 1998Date of Patent: January 30, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Robert Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
-
Patent number: 6080236Abstract: The invention provides a method of manufacturing a large-area electronic device, for example a flat panel display, comprising thin-film circuit elements, and also laser apparatus for crystallizing a portion of a semiconductor thin-film (1) with a beam (11) of set energy. The energy of the beam (11) is set in accordance with the output from a light detector (22) to regulate the crystallization of a device portion (3,4 and/or 5) of a semiconductor thin film (1) at which the beam (11) is subsequently directed with its set energy. The light detector (22) monitors the surface quality of a previously crystallized portion (2). In accordance with the present invention, the light detector (22) is located at a position outside the specular reflection path (25) of the light returned by the surface area of the crystallized portion (2) and detects a threshold increase (D) in intensity (I.sub.s) of the light (26) being scattered by the surface area of the crystallized portion.Type: GrantFiled: November 20, 1997Date of Patent: June 27, 2000Assignee: U.S. Philips CorporationInventors: David J. McCulloch, Stanley D. Brotherton
-
Patent number: 5935320Abstract: A process for producing silicon wafers with low defect density is one wherein a) a silicon single crystal having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 is produced by molten material being solidified to form a single crystal and is then cooled, and the holding time of the single crystal during cooling in the temperature range of from 850.degree. C. to 1100.degree. C. is less than 80 minutes; b) the single crystal is processed to form silicon wafers; and c) the silicon wafers are annealed at a temperature of at least 1000.degree. C. for at least one hour. Also, it is possible to prepare a silicon single crystal based upon having an oxygen doping concentration of at least 4*10.sup.17 /cm.sup.3 and a nitrogen doping concentration of at least 1*10.sup.14 /cm.sup.3 for (a) above.Type: GrantFiled: August 26, 1997Date of Patent: August 10, 1999Assignee: Wacker Siltronic Gesellschaft fur Halbleitermaterialien AGInventors: Dieter Graef, Wilfried Von Ammon, Reinhold Wahlich, Peter Krottenthaler, Ulrich Lambert
-
Patent number: 5879447Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.Type: GrantFiled: June 7, 1995Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
-
Patent number: 5843225Abstract: A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400.degree. to 650.degree. C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.Type: GrantFiled: June 7, 1995Date of Patent: December 1, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Yasuhiko Takemura, Hongyong Zhang, Shunpei Yamazaki
-
Patent number: 5803965Abstract: A method and system for manufacturing a semiconductor device having a semiconductor layer using a pulsed laser includes the steps of generating a laser beam using a solid laser source, generating a multi-harmonic wave from the laser beam using a multi-harmonic oscillator, filtering the multi-harmonic wave, and irradiating the filtered wave onto the semiconductor layer.Type: GrantFiled: August 13, 1996Date of Patent: September 8, 1998Assignee: LG Electronics, Inc.Inventor: Jung Kee Yoon
-
Patent number: 5735949Abstract: A buried amorphous layer on a crystalline substrate with a monocrystalline surface layer, which is transformed into a mixed-crystal or chemical compound, avoids the formation of lattice defects at the interface even where the lattice parameters of the substrate and the monocrystalline layer are not matched.Type: GrantFiled: September 13, 1991Date of Patent: April 7, 1998Assignee: Forschungszentrum Julich GmbHInventors: Siegfried Mantl, Bernd Hollander, Rainer Butz
-
Patent number: 5639698Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.Type: GrantFiled: February 15, 1994Date of Patent: June 17, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Hongyong Zhang, Toru Takayama, Hideki Uochi
-
Patent number: 5593494Abstract: Process for controlling the density of oxygen precipitate nucleation centers in single crystal silicon. In the process, the single crystal silicon is annealed at a temperature of at least about 350.degree. C. to cause the formation of oxygen precipitate nucleation centers in the single crystal silicon. During the annealing step, the single crystal silicon is heated (or cooled) to achieve a first temperature, T.sub.1, which is between about 350.degree. C. and about 500.degree. C. The temperature is then increased from T.sub.1 to a second temperature, T.sub.2, which is between about 500.degree. C. and about 750.degree. C. with the average rate of temperature increase from T.sub.1 to T.sub.2 being less than about 25.degree. C. per minute. The annealing is terminated at a point in time when the oxygen precipitate nucleation centers are capable of being dissolved by heat-treating the silicon at a temperature not in excess of about 1150.degree. C.Type: GrantFiled: March 14, 1995Date of Patent: January 14, 1997Assignee: MEMC Electronic Materials, Inc.Inventor: Robert Falster
-
Patent number: 5582640Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.Type: GrantFiled: April 30, 1993Date of Patent: December 10, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
-
Patent number: 5495824Abstract: A method of forming a semiconductor thin film by crystallizing a thin film crystal from an amorphous thin film. A plurality of small regions which are preferentially made nuclei generation points are formed at predetermined positions in the amorphous thin film. Solid phase growth from single nuclei formed in the small regions is preferentially effected by heating to form a crystalline semiconductor thin film in which the grain boundary positions are adjusted to the desired positions. This crystalline semiconductor thin film is subjected to a heat treatment to reduce defects in crystal grains.Type: GrantFiled: December 1, 1994Date of Patent: March 5, 1996Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Yoshiyuki Osada
-
Patent number: 5495823Abstract: Disclosed is a semiconductor apparatus in which a single-crystalline thin film can be formed on a semiconductor substrate at a low temperature not higher than 800.degree. C. and a method of manufacturing such a semiconductor apparatus. In this semiconductor apparatus and the manufacturing method thereof, a silane gas is supplied onto a single-crystalline silicon substrate under condition of a temperature not higher than approximately 540.degree. C. and an amorphous silicon thin film is formed on a surface of the silicon substrate. At the same time, the amorphous silicon thin film is single-crystallized to form a single crystal silicon thin film, and single crystal silicon thin films are successively epitaxially grown. This enables those single crystal silicon thin films to be formed directly on the surface of the single-crystalline silicon substrate at a temperature lower than or equal to 800.degree. C.Type: GrantFiled: July 14, 1994Date of Patent: March 5, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kiyoteru Kobayashi
-
Patent number: 5385115Abstract: A semiconductor wafer heat treatment method for improving the yield of devices which are end products by sampling sliced single-crystal silicon wafers made by CZ method to previously calculate the thermal donor concentration of each portion on the wafers and providing them with the IG heat treatment process which causes oxygen precipitation nucleus under the heat treatment condition determined according to the thermal donor concentration so that the change value (delta Oi) of the initial oxygen concentration (initial Oi) before the IG heat treatment to the oxygen concentration after the heat treatment will be kept within a predetermined range.Type: GrantFiled: May 13, 1993Date of Patent: January 31, 1995Assignee: Komatsu Electronic Metals Co., Ltd.Inventors: Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
-
Patent number: 5373803Abstract: A method of epitaxially growing semiconductor crystal by which a single crystal region which is superior in quality can be selectively formed at a high throughput without employing the lithography technique. A shield mask is formed on an upper face of an amorphous semiconductor layer formed on substrate, and excimer laser light is irradiated upon the amorphous semiconductor layer using the shield mask to produce, in the amorphous semiconductor layer, a core from which crystal is to be grown. After the shield mask is removed, low temperature solid phase annealing processing for the amorphous semiconductor layer is performed to grow crystal from the core to form a single crystal region in the amorphous semiconductor layer. Alternatively, the silicon core is formed by irradiating an energy beam, which is capable of being converged into a thin beam and being used to directly draw a picture, at a predetermined position of the amorphous silicon film.Type: GrantFiled: September 30, 1992Date of Patent: December 20, 1994Assignee: Sony CorporationInventors: Takashi Noguchi, Toshiharu Suzuki