Silicon From Vapor Or Gaseous State {c30b 29/06} Patents (Class 117/935)
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Patent number: 6406539Abstract: A process for producing a silicon carbide single crystal and a production apparatus therefor which enable, under stable conditions, continuous production of a silicon carbide single crystal which has a reduced density and dispersion of crystal defects in a growth direction, no lattice distortion, a large diameter, and constant quality. A melted or vaporized silicon material is introduced from the outside of a reaction system into a carbon material heated to a temperature equal to or higher than a temperature at which the silicon material vaporizes; and a reaction gas containing silicon gas and silicon carbide gas generated by a reaction between the carbon material and the silicon material is caused to reach a silicon carbide seed crystal substrate 5 which is held at a temperature lower than that of the carbon material, so that a silicon carbide single crystal grows on the silicon carbide seed crystal substrate.Type: GrantFiled: April 28, 2000Date of Patent: June 18, 2002Assignee: Showa Denko K.K,Inventors: Masashi Shigeto, Kotaro Yano, Nobuyuki Nagato
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Patent number: 6344403Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). The growth of the nanoclusters (19) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer (502) overlying the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20).Type: GrantFiled: June 16, 2000Date of Patent: February 5, 2002Assignee: Motorola, Inc.Inventors: Sucharita Madhukar, Ramachandran Muralidhar, David L. O'Meara, Kristen C. Smith, Bich-Yen Nguyen
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Patent number: 6325848Abstract: A single-crystal silicon substrate is provided, which makes it possible to accurately control the concentration and profile of an introduced impurity. This silicon substrate is comprised of a single-crystal Si base layer and a single-crystal Si low oxygen-concentration layer formed on the base layer. The base layer has a first oxygen concentration and the low oxygen-concentration layer has a second oxygen concentration lower than the first oxygen concentration. This silicon substrate is fabricated by (a) growing a single-crystal Si epitaxial layer on the main surface of a single-crystal Si base material in such a way that the epitaxial layer has a second oxygen concentration lower than of the first oxygen concentration, or (b) heat-treating a single-crystal Si base material to cause outward diffusion of oxygen existing in the base material through the main surface thereof, thereby forming a low oxygen-concentration layer extending along the main surface of the base material in the base material.Type: GrantFiled: November 12, 1998Date of Patent: December 4, 2001Assignee: NEC CorporationInventor: Masahito Watanabe
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Patent number: 6315826Abstract: Disclosed are a structure of a semiconductor substrate and a method of manufacturing the semiconductor substrate preventing a reduction of gettering capability due to a high-temperature heat treatment. In a semiconductor substrate containing a highly concentrated impurity having a polysilicon layer to be a gettering site on a rear surface side and an epitaxial layer 6 on a front surface side, an impurity concentration is lower near the rear and front surfaces and higher at the center in a cross section of the semiconductor substrate. The method of manufacturing the semiconductor substrate comprises the steps of: performing the heat treatment of a silicon substrate at a temperature of 1100° C. or more and a melting temperature or less of the silicon substrate before forming the polysilicon layer 4 and the epitaxial layer 6; forming the polysilicon layer 4 on the rear surface side of the silicon substrate; and forming the epitaxial layer 6 on the front surface side of the silicon substrate.Type: GrantFiled: June 22, 2000Date of Patent: November 13, 2001Assignee: NEC CorporationInventor: Satoru Muramatsu
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Patent number: 6306213Abstract: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips.Type: GrantFiled: October 31, 1997Date of Patent: October 23, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6267817Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.Type: GrantFiled: April 12, 2000Date of Patent: July 31, 2001Assignee: Micron Technology, Inc.Inventor: Fernando Gonzalez
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Patent number: 6228166Abstract: In order to reduce boron concentration between a silicon substrate and an Si or Si1-xGex layer which is epitaxially grown in a CVD (chemical vapor deposition) apparatus, the silicon substrate is pretreated, before being loaded into the CVD apparatus, such as to prevent the substrate from being contaminated by boron in a clean room. Further, in accordance with one embodiment, a CVD growth chamber itself is cleaned, before the substrate is loaded into the growth chamber, using an F2 gas at a predetermined temperature of the substrate, thereby to remove boron residues in the growth chamber.Type: GrantFiled: November 20, 1997Date of Patent: May 8, 2001Assignee: NEC CorporationInventors: Tatsuya Suzuki, Tohru Aoyama
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Patent number: 6210479Abstract: A process for cheaply fabricating a substantially single crystal or a polycrystalline semiconductor structure on a host substrate. The process begins by depositing a layer of wide band gap nitride material 10, such as gallium nitride, aluminum nitride and/or indium nitride, on a sapphire substrate 11. The semiconductor structure 14 is then grown on the nitride layer. Next, the host substrate 15 is attached with a bonding agent to an exposed surface area of the semiconductor structure 14. The sapphire substrate is lifted off by irradiation in which nitrogen is dissociated from the nitride layer.Type: GrantFiled: February 26, 1999Date of Patent: April 3, 2001Assignee: International Business Machines CorporationInventors: Nestor A. Bojarczuk, Supratik Guha, Arunava Gupta
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Patent number: 6165265Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate 11 , so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window 13 on the substrate; creating inside the window interstitial defects 14 with an atomic proportion lower than one for one hundred; and performing a silicon deposition 15 in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 750.degree. C.Type: GrantFiled: January 26, 1999Date of Patent: December 26, 2000Assignee: STMicroelectronics S.A.Inventors: Yvon Gris, Germaine Troillard, Jocelyne Mourier
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Patent number: 6124209Abstract: The surface of a silicon single crystal substrate 2 is exposed to a mixed gas of hydrogen fluoride gas and hydrogen gas at 0.degree. C.-100.degree. C. to remove a natural oxide film 3 formed on the surface of silicon single crystal substrate 2. The method, as a pre-treatment to the formation of a silicon single crystal thin film, gives a smooth surface with a low temperature treatment and without causing the out-diffusion of the dopants or the auto-doping phenomenon.Type: GrantFiled: December 10, 1997Date of Patent: September 26, 2000Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Hitoshi Habuka, Toru Otsuka
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Patent number: 6110278Abstract: A template for seeding growth of a desired single-crystal material (e.g., Si, GaAs) is created by passing through a monocrystalline channelizing mask, in a channelizing direction thereof, at least one of a nucleation-friendly species (e.g., Si, Ga) and a knock-off species (e.g., Ar, F) for respective implant of a nucleation-friendly species within or removal of a nucleation-unfriendly material (e.g., SiO.sub.2) of a supplied substrate. The desired single-crystal material is then grown in epitaxial-like manner from the thus-formed seeding-template. In one embodiment, silicon ions are projected through a monocrystalline silicon mask of a selected crystal orientation ((100), or (111)) in its channelizing direction so as to implant the silicon ions in a silicon dioxide layer of a supplied substrate according to the selected crystal orientation of the channelizing mask. Monocrystalline silicon is then epitaxially grown on top of the silicon dioxide layer with the same crystal orientation.Type: GrantFiled: August 10, 1998Date of Patent: August 29, 2000Inventor: Arjun N. Saxena
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Patent number: 6103019Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.Type: GrantFiled: February 18, 1998Date of Patent: August 15, 2000Inventor: Arjun Saxena
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Patent number: 6090666Abstract: There are provided a method for fabricating semiconductor nanocrystals which are highly controllable and less variable in density and size, as well as a semiconductor memory device which, with the use of the semiconductor nanocrystals, allows thickness of a insulating film between nanocrystals and channel region to be easily controlled and involves less variations in characteristics such as threshold and programming performance, and which is fast reprogrammable and has nonvolatility. Under a low pressure below atmospheric pressure, an amorphous silicon thin film 3 is deposited on a tunnel insulating film 2 formed on a silicon substrate 1.Type: GrantFiled: September 30, 1998Date of Patent: July 18, 2000Assignee: Sharp Kabushiki KaishaInventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima
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Patent number: 6080239Abstract: A semiconductor film deposited on a substrate has regions of different thermal conductivity. A pulsed laser radiation is applied to the semiconductor film to melt the semiconductor film. When the melted semiconductor film is cooled and solidified, localized low-temperature regions are developed in the respective regions of different thermal conductivity. Crystal nuclei are produced in the respective localized low-temperature regions and grown into a single semiconductor crystal. The regions of different thermal conductivity are formed in the semiconductor film by high-thermal-conductivity members deposited on the semiconductor film in thermally coupled relationship thereto. A semiconductor device is fabricated using the semiconductor film and has channels disposed in the vicinity of the crystal nuclei.Type: GrantFiled: February 4, 1997Date of Patent: June 27, 2000Assignee: Sony CorporationInventor: Takashi Noguchi
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Patent number: 6074478Abstract: A flat selective silicon epitaxial thin film in which facet formation and loading effect are suppressed is grown by using a conventional LPCVD system which does not require an ultrahigh vacuum environment. Raw material gases for film formation and atomic hydrogen formed in an atomic hydrogen formation chamber 2 installed separately from a reaction chamber is introduced into the reaction chamber, at a growth temperature in the range of 750-900.degree. C. and under a reaction chamber pressure in the range of 1-30 Torr.Type: GrantFiled: January 14, 1998Date of Patent: June 13, 2000Assignee: NEC CorporationInventor: Shizuo Oguro
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Patent number: 6059879Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.Type: GrantFiled: August 22, 1997Date of Patent: May 9, 2000Assignee: Micron Technology, Inc.Inventor: Fernando Gonzalez
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Patent number: 6045613Abstract: Bulk, low impurity silicon carbide single crystals are grown by deposition of vapor species containing silicon and vapor species containing carbon on a crystal growth interface. The silicon source vapor is provided by vaporizing liquid silicon and transporting the silicon vapor to a crystal growth crucible. The carbon vapor species are provided by either a carbon containing source gas (for example, CN) or by flowing the silicon source vapor over or through a solid carbon source, for example flowing the silicon vapor through porous graphite or a bed of graphite particles.Type: GrantFiled: October 9, 1998Date of Patent: April 4, 2000Assignee: Cree, Inc.Inventor: Charles Eric Hunter
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Patent number: 6007624Abstract: A method for controlling the autodoping during epitaxial silicon deposition. First, the substrate (10) is cleaned to remove any native oxide. After being cleaned, the substrate (10) is transferred to the deposition chamber in an inert or vacuum atmosphere to inhibit the growth of a native oxide on the surface of the wafers. A lower temperature (i.e., 500-850.degree. C.) capping layer (14) is deposited to prevent autodoping. Then, the temperature is increased to the desired deposition temperature and the remainder of the epitaxial layer (18) is deposited.Type: GrantFiled: August 30, 1996Date of Patent: December 28, 1999Assignee: Texas Instruments IncorporatedInventor: Rick L. Wise
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Patent number: 5964944Abstract: An easy and low-cost method of producing a large-size and high-purity silicon carbide (SiC) single crystal includes reacting silicon vapor directly with a carbon-containing compound gas under a heated atmosphere (growth space 14) to grow a silicon carbide single crystal (15) on a silicon carbide seed crystal (12), in which the silicon vapor generated from molten silicon (13) is used as a silicon vapor source, and a hydrocarbon gas (9) (e.g., propane gas) is used as the carbon-containing compound gas.Type: GrantFiled: March 21, 1997Date of Patent: October 12, 1999Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Naohiro Sugiyama, Atsuto Okamoto, Toshihiko Tani, Nobuo Kamiya
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Patent number: 5961713Abstract: A semiconductor silicon wafer (10) useful as a calibration standard for measurement of a thickness (18) of a microdefect-free layer (16) is formed by depositing an epitaxial layer onto a substrate (12) having an interstitial oxygen concentration suitable for precipitating oxide. Large, uniform oxide microdefects (14) are formed in the substrate by maintaining the semiconductor silicon wafer at between 600.degree. C. and 900.degree. C. to nucleate oxide precipitates that are then grown at between 800.degree. C. and 1,200.degree. C. Because the epitaxial layer contains no oxide precipitate nuclei to form microdefects, the epitaxial layer remains a microdefect-free layer and has a relatively sharp, easily detectable boundary with the substrate. The epitaxial layer can be polished to a reduced thickness, if desired.Type: GrantFiled: March 12, 1997Date of Patent: October 5, 1999Assignee: SEH America, Inc.Inventor: Witawat Wijaranakula
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Patent number: 5948162Abstract: An epitaxially grown layer having a large area and an uniform thickness is formed on an insulating layer. The surface of a silicon substrate (2) is oxidized to form a silicon dioxide layer (4) acting as insulating layer. The silicon dioxide layer (4) is then provided with an opening (10) by etching with the aid of resist (6). After removing the resist (6), a silicon seed crystal layer (11) is selectively grown in the opening (10). Next, the silicon dioxide layer (4) is subjected to etchback using hydrofluoric acid, so that the side face (14) of the seed crystal layer (11) is emerged. The following epitaxial growth on the basis of the seed crystal layer (11) is allowed sufficient growth in the lateral direction. As a result, an epitaxially grown layer having (16) a large area and an uniform thickness is realized.Type: GrantFiled: October 16, 1996Date of Patent: September 7, 1999Assignee: Rohm Co., Ltd.Inventor: Tomofumi Nakamura
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Patent number: 5938839Abstract: A method for forming a semiconductor device is disclosed. The method comprises the step of irradiating a laser light to a surface of a semiconductor through a mask provided on said surface in an atmosphere comprising an impurity of one conductivity type to diffuse said impurity into a region of said semiconductor.Type: GrantFiled: September 6, 1994Date of Patent: August 17, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hongyong Zhang
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Patent number: 5906680Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree. C., and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of about 10.sup.-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.Type: GrantFiled: December 24, 1996Date of Patent: May 25, 1999Assignee: International Business Machines CorporationInventor: Bernard Steele Meyerson
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Patent number: 5904767Abstract: A working recipe for NTD CZ and MCZ silicon wafer production is provided. It teaches that a neutron-enhanced S-curve can be constructed by noting that a silicon interstitial (Si.sub.I), emitted due to volume change during the traditional oxygen precipitation, can join a neutron-created vacancy in facilitating further oxygen loss via precipitation. The former relation is: 2Si+2O.sub.I .fwdarw.SiO.sub.2 +Si.sub.i the latter is: vacancy+Si .sub.I +2O.sub.I .fwdarw.SiO ..sub.2 The total loss of oxygen interstitials is:?O.sub.I !=Max(?O .sub.I !.sub.0 ?O .sub.I !.sub.s +min{2(?Si .sub.I !.sub.s +?Si .sub.I !.sub.0). ?vacancy!}),with subscripts 0 and s standing for initial state and S-curve prediction, respectively; ?Si.sub.I !.sub.s equal to 0.5?O .sub.I !.sub.s, and ?vacancy! readily obtainable by computer simulation. ?vacancy! is a function of the cadmium ratio (CR), silicon sample thickness, and total neutron fluence. The final oxygen interstitial content is: ?0.sub.I !.sub.f =max{?O.sub.I !.sub.0 -?O.sub.Type: GrantFiled: August 29, 1996Date of Patent: May 18, 1999Assignee: Industrial Technology Research InstituteInventor: Chungpin Liao
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Patent number: 5902394Abstract: A method is provided for stabilizing Czochralski (CZ) silicon melt by controlled oscillation of the crucible rotation during the stabilization period of the silicon melt to reduce the gas bubbles and unmelted polysilicon particles contained therein and thereby increase the yield and productivity of CZ silicon crystal production. The crucible rotation is controlled to follow an Oscillating Crucible Rotation (OCR) pattern or a saw tooth rotation pattern, which include rapid oscillations between a high rate of rotation and a low rate of rotation of the crucible during a period prior to the growth of the CZ crystal ingot.Type: GrantFiled: March 31, 1997Date of Patent: May 11, 1999Assignee: SEH America, Inc.Inventors: Charles Curtis Burkhart, Bruce Laurence Colburn
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Patent number: 5897705Abstract: A process for the production of an epitaxially coated semiconductor wafer, composed of a substrate wafer of monocrystalline silicon having a front side and a rear side, has at least one layer of semiconductor material which is epitaxially deposited on the front side of the substrate wafer and which is obtained by production of a heavily doped silicon monocrystal by crucible-free zone pulling, production of a substrate wafer having polished front side from the monocrystal and deposition of at least one epitaxial layer of semiconductor material on the front side of the substrate wafer.Type: GrantFiled: April 2, 1996Date of Patent: April 27, 1999Assignee: Wacker Siltronic Gesellschaft fur Halbeitermaterialien mbHInventors: Wolfgang Siebert, Erwin-Peter Mayer
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Patent number: 5849077Abstract: A method of growing epitaxial regions comprising the steps of providing a silicon substrate, forming a patterned oxide layer having a planar upper surface on the substrate, the oxide layer having an aperture therein extending to the substrate, forming a layer of silicon in the aperture extending above the surface of the oxide layer and removing the portion of the layer of silicon extending above the surface of the oxide layer. The sidewalls of the oxide layer defining the aperture are outwardly sloped in the direction of the upper surface. The layer of silicon is formed by a procedure which forms crystalline silicon in the aperture and forms no silicon over the oxide layer. The portion of the layer of silicon extending above the surface of the oxide layer is removed by a chemical-mechanical polishing operation. In addition, to provide auto-alignment, the layer of oxide is selectively etched relative to the layer of silicon to provide a step at the interface of the layer of oxide and the layer of silicon.Type: GrantFiled: June 14, 1996Date of Patent: December 15, 1998Assignee: Texas Instruments IncorporatedInventor: Danny J. Kenney
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Patent number: 5811030Abstract: Silicon thin films of superior resistivity useful for, e.g., semiconductor elements in solar cells, are formed by coating and drying silicon vaporized in the presence of hydrogen alone or hydrogen and an inert gas, followed by contacting the thus produced silicon particles with solvent to form a silicon colloid. Preferably, the silicon colloid is produced by a process which comprises vaporizing silicon in an atmosphere consisting essentially of hydrogen and up to 10 mol of an inert gas per mol of hydrogen; condensing silicon vaporized in the first step to form fine silicon particles; bringing the silicon particles into contact with a solvent to cover the silicon particles with solvent, and collecting the solvent covered silicon particles to obtain the silicon colloid.Type: GrantFiled: October 13, 1994Date of Patent: September 22, 1998Inventor: Nobuo Aoki
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Patent number: 5753555Abstract: A method is provided for forming an epitaxial silicon layer on a diffused region of a silicon substrate having an anisotropic ratio of more than 3:1 between the growth rate in the direction perpendicular to the substrate surface and the growth rate in the direction parallel to the substrate surface. The epitaxial silicon layer serves as a contact plug which does not contact an adjacent contact plug formed by the same process in order to obtain a reliable semiconductor memory device with a high throughput, which is free from short circuit failure.Type: GrantFiled: October 24, 1996Date of Patent: May 19, 1998Assignee: NEC CorporationInventor: Hiromitsu Hada
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Patent number: 5690736Abstract: A crystal is formed by applying crystal forming treatment to a substrate, the surface of the substrate being divided into nonnucleation surface exhibiting a small nucleation density and nucleation surface having a sufficeintly small area to allow crystal growth from a single nucleus and exhibiting a larger nucleation density than the nonnucleation surface and the nonnucleation surface being constituted of the surface of a buffer layer to alleviate generation of stress in the crystal formed.Type: GrantFiled: January 31, 1996Date of Patent: November 25, 1997Assignee: Canon Kabushiki KaishaInventor: Hiroyuki Tokunaga
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Patent number: 5656079Abstract: The present invention is an apparatus for the synthesis and growth of single crystals of phosphorus compounds starting with the elemental materials in a single furnace without external exposure. The apparatus of the present invention is a crystal growth furnace heated by RF coils. Inside the furnace is a susceptor heated by a lower coil device for holding a crucible. Above the crucible is selectively positioned a phosphorus improved injector. The improved injector is further surrounded by a susceptor which is heated by an upper coil device. The non-phosphorus materials are placed in the crucible and melted to a desired temperature. The phosphorus material previously placed within the injector is heated by the radiant heat from both crucible and the upper susceptor to drive the phosphorus vapor into the melt through a tube. This is closely controlled by noting the temperature within the injector and adjusting the height of the injector above the melt to control the temperature within the phosphorus material.Type: GrantFiled: March 13, 1995Date of Patent: August 12, 1997Assignee: The United States of America as represented by the Air ForceInventors: David Bliss, George Bryant, David Gabbe
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Patent number: 5653802Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.Type: GrantFiled: May 30, 1995Date of Patent: August 5, 1997Assignee: Canon Kabushiki KaishaInventor: Kenji Yamagata
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Patent number: 5593497Abstract: A method for forming a deposited film comprises the step of introducing a starting material (A) which is either one of a gaseous starting material for formation of a deposited film and a gaseous halogenic oxidizing agent having the property of oxidative action on said starting material into a film forming space in which a substrate having a material which becomes crystal neclei for a deposited film to be formed or a material capable of forming crystal nuclei selectively scatteringly on its surface is previously arranged to have said starting material (A) adsorbed onto the surface of said substrate to form an adsorbed layer (I) and the step of introducing a starting material (B) which is the other one into said film forming space, thereby causing surface reaction on said adsorption layer (I) to form a crystalline deposited film (I).Type: GrantFiled: April 3, 1995Date of Patent: January 14, 1997Assignee: Canon Kabushiki KaishaInventors: Jinsho Matsuyama, Yutaka Hirai, Masao Ueki, Akira Sakai
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Patent number: 5565029Abstract: A semiconductor device produced by forming an epitaxial layer insulated from a silicon substrate, and forming a device in the epitaxial layer. According to the process a silicon dioxide layer is formed on a semiconductor substrate. Then the silicon dioxide layer is provided with openings therein. Silicon is made to grow until it protrudes from the openings to thereby form a silicon seed crystal layer. Next, a silicon nitride layer is formed on the surface of the silicon seed crystal and thereafter is oxidized. A field oxide layer is thereby bonded at the lower portion of the openings so that the silicon seed crystal layer is insulated from the silicon substrate. Thereafter, epitaxial growth is effected from the silicon seed crystal layer. The growth is stopped just before silicon growth layers connect to one another, thus obtaining epitaxial grown layer having regions which are separated from one another. The device is formed in the epitaxially grown layer.Type: GrantFiled: March 31, 1995Date of Patent: October 15, 1996Assignee: Rohm Co., Ltd.Inventor: Hidemi Takasu
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Patent number: 5565031Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.Type: GrantFiled: February 17, 1995Date of Patent: October 15, 1996Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
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Patent number: 5562771Abstract: The present invention discloses an apparatus and method for producing microcrystal particles by irradiating pulse laser beam on raw material gas and causing the raw material gas to generate dielectric gas breakdown. The apparatus includes a laser oscillator for generating the pulsed laser beam, a reactor in which the raw material gas is activated and dissociated by irradiating the pulsed laser beam, and cohered to the microcrystal particles by generating luminescence, and a control device for controlling the laser oscillator to establish a pulse spacing of the pulse laser beam larger than a duration defined as a time during which the activated and dissociated raw material gas completes cohesion and turns into the microcrystal particles in the reactor.Type: GrantFiled: March 10, 1995Date of Patent: October 8, 1996Assignee: Victor Company of Japan, Ltd.Inventor: Toshihiko Kawaguchi
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Patent number: 5556463Abstract: A method of forming a crystallographically oriented silicon layer over a glassy layer of, for example, SiO.sub.2. A templating layer of a layered perovskite, preferably Bi.sub.4 Ti.sub.3 O.sub.12, is deposited on the glassy layer under conditions favoring its crystallographic growth with its long c-axis perpendicular to the film. The silicon is then grown over the templating layer under conditions usually favoring monocrystalline growth. Thereby, it grows crystallographically aligned with the underlaying templating layer.Type: GrantFiled: June 5, 1995Date of Patent: September 17, 1996Inventor: Charles S. Guenzer
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Patent number: 5525536Abstract: A SOI substrate has a first insulating film formed on a semiconductor substrate. A first opening is formed thereon and a dummy layer is formed on the first opening and the first insulating film. A second opening is formed in the dummy layer and a second insulating film is formed and the dummy layer is removed by etching through the third opening to form a cavity. A semiconductor crystal layer is epitaxially grown within the cavity with use of the semiconductor substrate as a seed. The second insulating film is then removed from the semiconductor crystal layer.Type: GrantFiled: April 13, 1994Date of Patent: June 11, 1996Assignee: Rohm Co., Ltd.Inventor: Sigeyuki Ueda
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Patent number: 5495823Abstract: Disclosed is a semiconductor apparatus in which a single-crystalline thin film can be formed on a semiconductor substrate at a low temperature not higher than 800.degree. C. and a method of manufacturing such a semiconductor apparatus. In this semiconductor apparatus and the manufacturing method thereof, a silane gas is supplied onto a single-crystalline silicon substrate under condition of a temperature not higher than approximately 540.degree. C. and an amorphous silicon thin film is formed on a surface of the silicon substrate. At the same time, the amorphous silicon thin film is single-crystallized to form a single crystal silicon thin film, and single crystal silicon thin films are successively epitaxially grown. This enables those single crystal silicon thin films to be formed directly on the surface of the single-crystalline silicon substrate at a temperature lower than or equal to 800.degree. C.Type: GrantFiled: July 14, 1994Date of Patent: March 5, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kiyoteru Kobayashi
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Patent number: 5465680Abstract: A method of forming crystalline silicon carbide films is disclosed. The method comprises a chemical vapor deposition process in which a substrate is heated to a temperature above about 600.degree. C. in the presence of trimethylsilane gas.Type: GrantFiled: July 1, 1993Date of Patent: November 14, 1995Assignee: Dow Corning CorporationInventor: Mark J. Loboda
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Patent number: 5441012Abstract: A thin film deposition method consists of placing a wafer or substrate whose surface contains at least two kinds of materials inside a vacuum chamber or vessel, supplying a reactant gas into the vacuum chamber or vessel, the reactant gas containing molecules having a low sticking coefficient relative to at least one of the at least two kinds of materials, and allowing an epitaxial growth to occur on the other kinds of materials contained in the wafer or substrate.The method further includes setting the pressure inside the vacuum chamber or vessel filled with the reactant gas equal to a pressure range in which the mean free path (d) of the reactant gas molecules is longer than the shortest distance (L) between the wafer or substrate placed inside the vacuum chamber or vessel and the vacuum side-exposed wall of the vacuum chamber or vessel, i.e., d>L.Type: GrantFiled: January 26, 1994Date of Patent: August 15, 1995Assignees: ANELVA Corporation, NEC CorporationInventors: Ken-ichi Aketagawa, Junro Sakai, Toru Tatsumi
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Patent number: 5439844Abstract: A process for forming a deposited film comprises the steps:(a) arranging a substrate having crystal orientability uniformly on its surface in a film forming space for formation of a deposited film;(b) introducing into said film forming space an activated species (A) formed by decomposition of a compound (SX) containing silicon and a halogen and an activated species (B) formed from a chemical substance (B) for film formation which is chemically mutually reactive with said activated species (A) separately from each other, thus permitting both the species to react chemically with each other thereby to form a deposited film on the above substrate; and(c) introducing into said film forming space a gaseous substance (E) having etching action on said deposited film to be formed or a gaseous substance (E2) forming said gaseous substance (E) during the above film formation step (b), thus exposing the surface for deposited film growth to said gaseous substance (E) and thereby effecting an etching action to conduct crysType: GrantFiled: May 12, 1993Date of Patent: August 8, 1995Assignee: Canon Kabushiki KaishaInventor: Akira Sakai
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Patent number: 5422306Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.Type: GrantFiled: December 15, 1992Date of Patent: June 6, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
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Patent number: 5406906Abstract: A crystalline silicon carbide film is grown on a heated crystalline silicon substrate by laser ablation of a pure carbon target. For substrate temperatures during deposition above 1000.degree. C. and single crystal silicon substrates the resulting SiC film is expitaxially oriented with respect to the substrate. Films of stoichiometric SiC are grown up to thicknesses of about 4000.ANG.. These films grow on top of the silicon substrate and whereas the source of carbon for the film is from the ablation plume of the carbon target the source of the silicon is from the substrate. By using a method of alternate ablation of a pure carbon and a pure silicon target, similar epitaxial films can be grown to thicknesses in excess of 1 .mu.m with part of the silicon being supplied by the ablation plume of the silicon target.Type: GrantFiled: January 18, 1994Date of Patent: April 18, 1995Assignee: Ford Motor CompanyInventors: Lajos Rimai, Richard M. Ager, Willes H. Weber
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Patent number: 5405803Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, after As and C are introduced to a semiconductor substrate, a semiconductor layer is formed on the semiconductor substrate. When first and second semiconductor layers are to be sequentially formed on a semiconductor substrate, an impurity concentration of As or Sb serving as an impurity of the first semiconductor layer is 10 times or more an impurity concentration of the second semiconductor layer, and the second semiconductor layer has a thickness of 4 to 10 .mu.m.Type: GrantFiled: September 21, 1993Date of Patent: April 11, 1995Assignee: Sony CorporationInventor: Takahisa Kusaka
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Patent number: 5390626Abstract: In a process for the formation of SiC films by a low pressure CVD method using a hot-wall type, a dichlorosilane gas and an acetylene gas are used as a source gas, the flow velocity of the source gases in a reactor is set at not less than 70 cm/second, and the temperature for heating the reactor is set at not more than 1,000.degree. C., whereby SiC films having excellent uniformity in the film thickness and film properties on the surface of one substrate and among different substrates can be produced at a high mass productivity without causing any damage to the reactor from heat during the film formation.Type: GrantFiled: March 26, 1993Date of Patent: February 21, 1995Assignee: Hoya CorporationInventors: Hiroyuki Nagasawa, Minoru Sugawara, Kazuhide Yamashiro, Masato Kobayashi, Yohichi Yamaguchi
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Patent number: 5381753Abstract: A fabrication method provides fine structures which have few carrier trap centers and light absorption levels and find applications in quantum wires and quantum boxes having arbitrary configurations at least within a two-dimensional plane. The fabrication method comprises the steps of having a sharp tip held in close proximity to the surface of a substrate 1 and having a metal constituting the tip evaporated from the top. Alternatively, a metal contained in ambient vapor or a solution decomposed by a tunnel current or the like is provided. The metal is deposited locally on the substrate surface. A finely structured crystal is grown on the locally deposited region by a vapor phase-liquid phase-solid phase reaction.Type: GrantFiled: April 30, 1993Date of Patent: January 17, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michio Okajima, Osamu Kusumoto, Takao Tohda, Kazuo Yokoyama, Motoshi Shibata
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Patent number: 5362682Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: March 15, 1993Date of Patent: November 8, 1994Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C.C. Fan, Robert W. McClelland
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Patent number: 5355831Abstract: For the production of high-quality electronic components based on semiconductors, semiconductor wafers are needed which have a substantially lower oxygen concentration in the wafer region near the surface in which the components are integrated than in the other wafer region. This region, known as "denuded zone," was hitherto obtained by prolonged heat treatment of the wafers in a batch reactor as a consequence of partial diffusion of the oxygen out from the substrate. In the process according to the invention, the low-oxygen region is produced by the epitaxial deposition of two differently doped semiconductor layers on the wafer surface in a single-wafer reactor.Type: GrantFiled: May 6, 1992Date of Patent: October 18, 1994Assignee: Wacker-Chemitronic Gesellschaft fur Elektronik-Grundstoffe mbHInventor: Reinhard Schauer
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Patent number: 5342805Abstract: This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislocations is superior to any amount of Au and to some specific placements of the misfit dislocations in the device structure.Type: GrantFiled: July 1, 1993Date of Patent: August 30, 1994Assignee: G.I. CorporationInventors: Joseph Y. Chan, Larry Laterza, Dennis Garbis, William G. Einthoven