Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
Type:
Grant
Filed:
October 14, 2021
Date of Patent:
May 28, 2024
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method for forming a line of an LCD device includes sequentially depositing first and second metal layers on a glass substrate, forming a mask pattern on the second metal layer, performing a first wet-etch process using a mixed acid solution as an etchant on the first and second metal layers with the mask pattern, and performing a second wet-etch process using the mask pattern.
Abstract: A redundant electricity-conducting structure, and a method for making it, for use in a liquid crystal display ("LCD"). The LCD has a first layer and a second layer covering a portion of the first layer such that an edge is formed where the second layer starts. The redundant structure includes: a first conductor partially covering each of an area over the first layer and the second layer such that the first conductor must undergo a large change in surface direction where the conductor follows the edge contour of the second layer; and a redundant second conductor connected to and partially covering the first conductor at least in an area extending outside of an area under which is located the large change in surface direction.