Lift-off Masking Patents (Class 148/DIG100)
  • Patent number: 6093586
    Abstract: To enable radiating an optimum energy beam depending upon the structure of a substrate (whether a metallic film is formed or not) when an amorphous semiconductor film is crystallized and uniformly crystallizing the overall film, first, a photoresist film and the area of an N.sup.+ doped amorphous silicon film on the photoresist film are selectively removed by a lift-off method. Hereby, the amorphous silicon film is thicker in an area except an area over a metallic film (a gate electrode) than in the area over the metallic film. In this state, a laser beam is radiated. The N.sup.+ doped amorphous silicon film and an amorphous silicon film are melted by radiating a laser beam and afterward, melted areas are crystallized by cooling them to room temperature.
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: July 25, 2000
    Assignee: Sony Corporation
    Inventors: Dharam Pal Gosain, Jonathan Westwater, Miyako Nakagoe, Setsuo Usui
  • Patent number: 5994194
    Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: November 30, 1999
    Assignee: TRW Inc.
    Inventor: Michael D. Lammert
  • Patent number: 5918130
    Abstract: The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: June 29, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fred N. Hause, Mark I. Gardner, H. Jim Fulford, Jr.
  • Patent number: 5869390
    Abstract: Disclosed is a method of forming electrodes on diamond comprising the steps of: forming a mask pattern on diamond or diamond film; performing a treatment of the diamond surface by a plasma of inert gases; forming an electrode film on the whole surface of the specimen; and removing the mask, thereby forming a specified pattern of the electrodes. By this method, it is possible to form electrodes having high adhesion to diamond and diamond film for electronic devices.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: February 9, 1999
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Kozo Nishimura, Koji Kobashi, Shigeaki Miyauchi, Rie Kato, Hisashi Koyama, Kimitsugu Saito
  • Patent number: 5856232
    Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: January 5, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeon-Wook Yang, Eung-Gee Oh, Byung-Sun Park, Chul-Sun Park, Kwang-Eui Pyun
  • Patent number: 5854097
    Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: December 29, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tadahiro Ohmi, Mamoru Miyawaki
  • Patent number: 5770467
    Abstract: Disclosed is a method of forming electrodes on diamond comprising the steps of: forming a mask pattern on diamond or diamond film; performing a treatment of the diamond surface by a plasma of inert gases; forming an electrode film on the whole surface of the specimen; and removing the mask, thereby forming a specified pattern of the electrodes. By this method, it is possible to form electrodes having high adhesion to diamond and diamond film for electronic devices.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 23, 1998
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Kozo Nishimura, Koji Kobashi, Shigeaki Miyauchi, Rie Kato, Hisashi Koyama, Kimitsugu Saito
  • Patent number: 5736417
    Abstract: A heterejunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: April 7, 1998
    Assignee: TRW Inc.
    Inventors: Aaron K. Oki, Donald K. Umemoto, Liem T. Tran, Dwight C. Streit
  • Patent number: 5693548
    Abstract: A method for making a T-shaped gate of a field effect transistor is disclosed. The method includes the steps of sequentially depositing first and second photoresist layers on a semiconductor substrate and performing an exposure using electron beams having different energy, one of the electron beams having a first energy to lightly expose only the second photoresist layer and the other of the electron beams having a second energy to lightly expose all of the first and second layers. The invention reduces gate resistance and parasitic capacitance of the T-shaped gate.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: December 2, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jin-Hee Lee, Sang-Soo Choi, Hyung-Sup Youn, Chul-Soon Park, Hyung-Jun Yoo, Hyung-Moo Park
  • Patent number: 5686325
    Abstract: A compound semiconductor transistor has a structure in which a first insulating film is formed only under a overhang of a gate electrode an upper part of which is formed widely, and a second insulating film for threshold voltage adjustment is formed on the side of a gate electrode and the first insulating film.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: November 11, 1997
    Assignee: Fujitsu Limited
    Inventors: Toshiaki Moriuchi, Teruo Yokoyama
  • Patent number: 5679608
    Abstract: The interconnects in a semiconductor device contacting metal lines includes a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist includes a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 21, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robin W. Cheung, Mark S. Chang
  • Patent number: 5614438
    Abstract: A method for making an improved LSCO stack in the generation of platinum features on the surface of a substrate. The method provides an inexpensive means for depositing and etching LSCO material in the construction of small platinum features. The method comprises sputtering of the LSCO material and utilizing a photoresist mask to pattern the LSCO in accordance with the platinum features. The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: March 25, 1997
    Assignee: Radiant Technologies, Inc.
    Inventors: Joseph T. Evans, Jr., Leonard Boyer
  • Patent number: 5605845
    Abstract: In the manufacture of active-matrix liquid-crystal displays or other large area electronic devices, self-aligned photolithographic process steps (FIGS. 2 and 5) are used to define first and second gates (1 and 2) of a TFT from first and second conductive layers (21 and 22). In the first self-aligned step a positive photoresist (26) is selectively exposed by illumination (31) through the substrate (10) while using opaque areas (3 and 4) of the TFT source and drain as a photomask; after developing this selectively-exposed positive photoresist (26) and depositing the first conductive layer (21), a lift-off process is used to leave a first area (21a and 21b) of the first conductive layer where the first and second gates (1 and 2) are to be provided. Then a part (21b) of this first area is removed to leave a smaller, second area (21a) of the first conductive layer (21) for forming the first gate (21).
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: February 25, 1997
    Assignee: U.S. Philips Corporation
    Inventor: Nigel D. Young
  • Patent number: 5587328
    Abstract: A semiconductor device manufacturing method with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a short process. The method includes the steps of: depositing a first mask layer on a semiconductor substrate; forming an opening in the first mask layer; causing the first mask layer to flow by heat-treating the semiconductor substrate; depositing a second mask layer on the first mask layer; forming in the second mask layer an opening larger than the opening in the first mask layer and exposing the opening in the first mask layer; and forming a gate electrode in the opening in the second mask layer.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: December 24, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kazuhiro Yoshida
  • Patent number: 5583063
    Abstract: A method of forming a T-shaped, cross-sectional pattern that enables upper and lower parts of the T-shaped patten using in first and second resist films layers independent of an existence of a mixing layer. A first resist film that is not sensitive to UV light is formed on or over a substrate and a first window is formed on or over a substrate and a first window is formed in the first resist film. The first window corresponds to the lower part of the T-shaped pattern. Next, a second resist film is formed on the first resist film to cover the first window. The second resist film is exposed to UV light to form a given image in the second resist film and is developed to form a second window in the second resist film. The second window corresponds to the upper part of the pattern.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: December 10, 1996
    Assignee: NEC Corporation
    Inventor: Norihiko Samoto
  • Patent number: 5550065
    Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.
    Type: Grant
    Filed: November 25, 1994
    Date of Patent: August 27, 1996
    Assignee: Motorola
    Inventors: Majid M. Hashemi, Saied N. Tehrani, Patricia A. Norton
  • Patent number: 5541128
    Abstract: In the fabrication of thin-film field-effect transistors, a dielectric island is first formed over a gate and between locations where source and drain contacts are to be deposited. A dielectric cap with an overhanging brim is formed on the island. A layer of SD metal which will form the source-drain contacts is next deposited. Because of the overhang, the SD metal does not coat the entire cap, but leaves part of the cap remaining exposed and attackable by an etchant. Application of an etchant etches away the island and the cap, thereby lifting off the SD metal coated on the cap, leaving the fully-formed source and drain contacts in place, separated by the extent of the island.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: July 30, 1996
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin
  • Patent number: 5527726
    Abstract: A thin-film field-effect transistor is fabricated by forming an electrically insulative island between the source and the drain. A cap is formed on the island with a brim that overhangs the island. A layer of source-drain metal, which will subsequently constitute the source and drain contacts, is then deposited upon the source, the drain, and the cap, but the overhang creates an exposed region which can be attacked by an etchant. When the etchant is applied, it etches away the cap, thereby lifting off the source-drain metal which coated the cap, leaving the fully formed source and drain contacts separated by the island.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: June 18, 1996
    Assignee: General Electric Company
    Inventors: George E. Possin, Robert F. Kwasnick
  • Patent number: 5500381
    Abstract: A fabrication method of a FET that enables to realize a shorter length between a source-side edge of a recess and an opposing edge of a gate electrode at a higher accuracy than the accuracy limit of the present lithography technique, i.e., about .+-.0.1 .mu.m. After channel, carrier-supply, and contact layers are epitaxially grown on a semiconductor substrate in this order, a patterned insulator layer is formed on the contact layer. Using the insulator layer as a mask, the contact layer is isotropically etched to form a symmetrical recess on the underlying carrier-supply layer. One of the ends of the contact layer facing the symmetrical recess is etched again to make it asymmetric. During the etching processes, the underlying carrier-supply layer is almost never etched due to large etch rate differences for the contact layer and the carrier-supply layer. A patterned conductor layer is formed on the patterned insulator layer to form the gate electrode in Schottky contact with the carrier-supply layer.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: March 19, 1996
    Assignee: NEC Corporation
    Inventors: Takayoshi Yoshida, Yasunobu Nashimoto
  • Patent number: 5498572
    Abstract: A method for manufacturing a semiconductor device including forming an electrode on a part of a semiconductor substrate, depositing an insulating film on the semiconductor substrate and on the electrode, and forming a contact hole penetrating through the insulating film to expose a part of the electrode; forming a barrier metal layer on the electrode in the contact hole, on the internal side surface of the contact hole, and on the surface of the insulating film; and depositing a metal layer on the barrier metal layer and patterning the metal layer and the barrier metal layer to form a wiring layer wherein the barrier metal layer comprises a metal that does not form an intermetallic material by solid state diffusion with either of the electrode and the metal layer even at elevated temperatures.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: March 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiko Shiga, Ryo Hattori, Tomoki Oku
  • Patent number: 5451175
    Abstract: An electronic device including a plurality of field emission devices exhibiting dis-similar electron emission characteristics wherein an aperture radius associated with each of the plurality of field emission devices determines the electron emission characteristic.
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: September 19, 1995
    Assignee: Motorola, Inc.
    Inventors: Robert T. Smith, Robert C. Kane
  • Patent number: 5445979
    Abstract: A semiconductor device comprises an active layer formed of a compound semiconductor for allowing carriers travel therethrough for exhibiting a function of the device, a protection layer including a non-doped compound semiconductor layer formed on the active layer, a pair of contact holes formed in the protection layer to expose the active layer, and an electrode filling the contact holes and covering the exposed active layer and extending on the protection layer. Generation of notch can be prevented even upon formation of a contact hole in the non-doped compound semiconductor layer and depositing electrode layer thereon.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 29, 1995
    Assignee: Fujitsu Limited
    Inventor: Hidenori Hirano
  • Patent number: 5391507
    Abstract: A method of fabricating a self-aligned thin film transistor (TFT) with a lift-off technique includes the steps of forming a multi-tier island on a semiconductive layer such that the island structure is disposed in a desired alignment over the gate electrode. The island structure includes a base layer portion, an intermediate body portion, and an upper cap portion, which overhangs the intermediate body portion by an amount between about 0.5 .mu.m and 1.5 .mu.m. Source and drain electrodes are formed such that the source/drain material is disposed over the semiconductive material up to the sidewalls of the base portion of the island structure, which base portion is patterned such that the source and drain electrodes are self-aligned with and extend a selected overlap distance over the gate to provide desired TFT performance characteristics. The upper cap layer is removed in a lift-off technique and the intermediate body portion of the island is removed to complete fabrication oft the TFT.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: February 21, 1995
    Assignee: General Electric Company
    Inventors: Robert F. Kwasnick, George E. Possin
  • Patent number: 5358885
    Abstract: A method of producing a field effect transistor includes depositing a first insulating film and a refractory metal on a semiconductor substrate, forming a first aperture penetrating the first insulating film and the refractory metal film to provide a gate electrode production region, depositing a second insulating film on the refractory metal film, etching the second insulating film in a direction perpendicular to the surface of the substrate leaving portions of the second insulating film on opposite side walls of the first aperture to form a second aperture, defining a gate length, depositing a gate metal, and patterning the gate metal layer, the first insulating film, and the refractory metal film in a prescribed width to form a T-shaped gate structure. During etching the second insulating film, since the refractory metal film serves as a etch stopping layer, the first insulating film is not etched and its thickness remains as deposited.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: October 25, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomoki Oku, Masayuki Sakai, Yasutaka Kohno
  • Patent number: 5288654
    Abstract: A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.
    Type: Grant
    Filed: February 8, 1993
    Date of Patent: February 22, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuyuki Kasai, Shinichi Sakamoto, Takuji Sonoda, Tetsuya Yagi
  • Patent number: 5286335
    Abstract: Novel processes permit integrating thin film semiconductor materials and devices using epitaxial lift off, alignment, and deposition onto a host substrate. One process involves the following steps. An epitaxial layer(s) is deposited on a sacrificial layer situated on a growth substrate. Device layers may be defined in the epitaxial layer. All exposed sides of the epitaxial layer is coated with a transparent carrier layer. The sacrificial layer is then etched away to release the combination of the epitaxial layer and the transparent carrier layer from the growth substrate. The epitaxial layer can then be aligned and selectively deposited onto a host substrate. Finally, the transparent carrier layer is removed, thereby leaving the epitaxial layer on the host substrate. An alternative process involves substantially the same methodology as the foregoing process except that the growth substrate is etched away before the sacrificial layer.
    Type: Grant
    Filed: April 8, 1992
    Date of Patent: February 15, 1994
    Assignee: Georgia Tech Research Corporation
    Inventors: Timothy J. Drabik, Nan M. Jokerst, Mark G. Allen, Martin A. Brooke
  • Patent number: 5273918
    Abstract: The invention relates to a process for producing a junction field effect transistor in which the surface layer provided for conducting the current has a reduced cross-section in the channel area. The gist of the invention is that a photoresist mask is applied to the surface layer of the first conductivity type which is initially of uniform thickness. The surface layer is removed to a residual thickness through an opening in the photoresist mask. Impurities are then implanted into the surface layer through the same opening in the aforesaid mask to produce a zone of the second or opposite conductivity type. Finally, the aforementioned mask is used as a contacting mask for the manufacture of the gate electrode.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: December 28, 1993
    Assignee: Temic Telefunken microelectronic GmbH
    Inventor: Heinz Beneking
  • Patent number: 5266526
    Abstract: A method of forming a trench buried wiring on a semiconductor device. The method includes the steps of: forming a trench in a first insulating film formed on a semiconductor substrate, by using as a mask a photoresist layer, the trench having substantially an upright step; depositing a first electrode material on the surface of the photoresist layer and on the bottom of the trench, while leaving the photoresist layer; removing the photoresist layer and the first electrode material on the photoresist layer while leaving the first electrode material only on the bottom of the trench; and filling a second electrode material in the trench to form a composite electrode with the second electrode material being superposed on the first electrode material.
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: November 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaharu Aoyama, Masahiro Abe
  • Patent number: 5250451
    Abstract: Process for the local passivation of a substrate by a hydrogenated amorphous carbon layer and process for producing thin film transistors on said passivated substrate. The local passivation process consists of producing photosensitive resin patterns (3) on the substrate (1), subjecting the structure obtained to a radio-frequency plasma essentially constituted by a hydrocarbon for thus depositing a hydrogenated amorphous carbon layer (6) on the structure and dissolving the resin patterns (3) in order to eliminate the amorphous carbon deposited on the resin, the amorphous carbon deposited on the substrate constituting the said passivation.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: October 5, 1993
    Assignee: France Telecom Etablissement Autonome de Droit Public
    Inventor: Yannick Chouan
  • Patent number: 5240878
    Abstract: A method of forming patterned films on a semiconductor substrate 10 includes the steps of depositing a hardened photo resist underlay 30 onto the substrate, then depositing a polyether sulfone release layer 32, then depositing a photo sensitive resist layer 34 and exposing an etching a metallization pattern 36, 38 to the substrate 10. The structure is then blanket deposited with a conductive layer 40 to thereby create a conductive contact stud 42. The film layer 40 and resist layer 34 are removed by dissolving the polyether sulfone layer 32 in an NMP solution and the photo resist underlayer 30 is then removed using a selective photo resist stripper composition.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: August 31, 1993
    Assignee: International Business Machines Corporation
    Inventors: John A. Fitzsimmons, Janos Havas, Margaret J. Lawson, Edward J. Leonard, Bryan N. Rhoads
  • Patent number: 5223454
    Abstract: A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 29, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Tasuku Tanaka, Yoshiaki Emoto, Shigeo Kuroda
  • Patent number: 5215939
    Abstract: In a method of manufacturing a planar buried heterojunction laser, after etching to delimit a laser stripe in relief on a substrate, lateral layers to surround the stripe are formed by a non-selective growth method not only at the sides of the stripe but also above it to create a parasitic projection. This projection is then removed after separation from the substrate by selective attack of a lift-off stripe which was deposited for this purpose above the stripe prior to this etching. Passages are formed for the attack medium used for this purpose. The invention can be applied in particular to the manufacture of fiber optic transmission systems.
    Type: Grant
    Filed: February 6, 1992
    Date of Patent: June 1, 1993
    Assignee: Alcatel N.V.
    Inventors: Leon Goldstein, Dominique Bonnevie, Francois Brillouet, Francis Poingt, Jean-Louis Lievin
  • Patent number: 5212117
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a first insulating layer on a semiconductor substrate, forming a resist film sensitive to electron beams on the first insulating layer, applying electron beams onto a predetermined region of the resist film, removing unnecessary portions of the resist film by using a developer, thereby forming a remaining pattern resist film, forming a second insulating layer on the entire region of the first insulating layer and the remaining pattern resist film, simultaneously removing the remaining pattern resist film and the second insulating layer which is formed thereon, thereby forming an opening of a predetermined pattern on the second insulating layer, and etching the first insulating layer through the opening, using the second insulation layer as a mask, thereby causing a predetermined region of the semiconductor substrate to be exposed.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Tsuji
  • Patent number: 5202286
    Abstract: A method of producing a three-dimensional feature on a substrate and adjacent electrically insulating films comprising producing a resist on a portion of a surface of a substrate; etching the substrate to remove portions of the substrate not covered by the resist, leaving an etched surface on part of the substrate, and producing a three-dimensional feature having side walls intersecting the etched surface of the substrate underlying and undercutting the resist so that the resist includes overhanging portions spaced from the etched surface of the substrate, the three-dimensional feature having a height between the resist and the etched surface of the substrate; depositing, in a chemical vapor deposition process at a relatively low temperature, a discontinuous electrically insulating film to a thickness no greater than the height of the three-dimensional feature in a first segment on the resist and in a second segment, discontinuous from the first segment, on the etched surface of the substrate adjacent the thr
    Type: Grant
    Filed: August 14, 1991
    Date of Patent: April 13, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Mitsunori Nakatani
  • Patent number: 5190892
    Abstract: A method is for forming a pattern from a film which is deposited with a low directivity. A resist pattern is formed on a substrate. A first film is deposited with low directivity, and then a second film is deposited with high directivity. The first film is etched selectively using the second film as an etching mask. Then, the resist pattern is dissolved.
    Type: Grant
    Filed: December 3, 1991
    Date of Patent: March 2, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshiaki Sano
  • Patent number: 5185277
    Abstract: Disclosed is a method for making a mushroom gate for a microwave transistor. Three masking layers are deposited on the semiconductor body of a transistor. At least two of these masking layers are different and have selective solvents. After the opening of the external layer, the intermediate layer is dissolved with sub-etching with respect to the external layer, then the base of the gate is etched in the internal layer. The edges of the sub-etching prevent the metal deposited on the mask from adhering to the gate, thus facilitating the lift-off of the mask. Application to microwave transistors with symmetrical or disymmetrical mushroom gate.
    Type: Grant
    Filed: June 12, 1991
    Date of Patent: February 9, 1993
    Assignee: Thomson Composants Microondes
    Inventors: Pham N. Tung, Martine Chapuis
  • Patent number: 5182218
    Abstract: The present invention relates to a method of making a compound semiconductor device having a high performance self-aligned LDD structure which has stable characteristics, and is suitable for high integration and high yield, in which after forming a channel layer beneath the substrate surface, using a high performed self-aligned technology, a gate electrode, lightly doped layers and heavily doped layers are formed in predetermined positions by a photolithography for the gate portion. This process of a photolithography is performed only once, therefore, each pattern can be formed with excellent accuracy and reproducibility.
    Type: Grant
    Filed: February 20, 1992
    Date of Patent: January 26, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Mitsuaki Fujihira
  • Patent number: 5171718
    Abstract: A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.
    Type: Grant
    Filed: January 9, 1991
    Date of Patent: December 15, 1992
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Yoshifumi Mori, Kenji Funato
  • Patent number: 5171711
    Abstract: A method of manufacturing IC devices is applied in forming bumps on an electrode pads to be an input/output terminal of the ICs with a conductive metal layer interposed therebetween. Firstly, a first resist having a prescribed opening is formed over a semiconductor substrate having the electrode pads formed thereon. Thereafter, the metal layer is formed over the semiconductor substrate, and furthermore, a second resist is formed over it by making an opening in a region almost the same as the opening of the first resist. Then, the second resist is removed after forming the bumps within the opening of the second resist. Thereafter, the first resist is removed after removing an exposed portion of the metal layer. According to the processes, overetching of and generation of an etching residue of the metal layer are prevented.
    Type: Grant
    Filed: October 17, 1991
    Date of Patent: December 15, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Tobimatsu
  • Patent number: 5149671
    Abstract: A method for forming multilayer bump contacts for use in flip-chip bump bonding and the like. The method comprises applying a base layer to a substrate and then applying a malleable conductive layer to the base layer. In a first embodiment, individual bump contacts are formed by removing portions of the base layer and malleable layer such that a plurality of bump contacts are formed. In a second embodiment a photoresist and etching process is used. The need to precisely align a mark to define the position of the malleable layer relative to the base layer is eliminated since the positions of the malleable layer and the base layer are defined simultaneously in both embodiments. Thus, the number of process steps is reduced, yield is increased, and alignment accuracy is improved.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: September 22, 1992
    Assignee: Grumman Aerospace Corporation
    Inventors: Wei Koh, Wayne D. Kuipers
  • Patent number: 5124275
    Abstract: A method of manufacturing by autoalignment an integrated semiconductor device is set forth comprising the realization on respective semiconductor layers of a first encapsulated electrode contact E provided with spacers and of a second autoaligned electrode contact B on the first contact thus equipped, which process comprises at least: a.sub.0) the formation of a first and a second semiconductor layer for receiving the first and the second electrode contact, respectively; b.sub.0) the formation by a so-called image reversal method of an opening B.sub.o with overhanging sides in a photoresist layer deposited on the first semiconductor layer; c.sub.0) the deposition of a first metal layer forming the first electrode contact E in this opening, which contact has sides F.sub.2 of a lower height than those F.sub.1 of the photoresist layer, these sides F.sub.2 having upper edges which are situated laterally at a small distance from the overhanging sides F.sub.
    Type: Grant
    Filed: February 5, 1991
    Date of Patent: June 23, 1992
    Assignee: U.S. Philips Corporation
    Inventors: Daniel Selle, Dominique Carisetti
  • Patent number: 5114871
    Abstract: The invention provides a process for manufacturing an electronic device on a semiconducting substrate which is transparent to light of a particular wavelength. The process includes the steps of treating the substrate to form at least one region having a different electrical property to the substrate, and defining a conducting contact for the region by selective photolithographic masking and chemical etching. A layer of photoresist material deposited on one side of the substrate is subjected to light transmitted through the substrate from a light source on the other side of the substrate. The process can be used to produce a field effect transistor on a diamond substrate.
    Type: Grant
    Filed: May 24, 1989
    Date of Patent: May 19, 1992
    Inventor: Barbara L. Jones
  • Patent number: 5112763
    Abstract: Provided is a process for precisely forming a Schottky barrier gate on GaAs. In the process, a layer of polyimide is spun onto a doped GaAs substrate having a passivating layer thereon. A resist layer is then spun onto the polyimide, and either deep ultraviolet lithography in conjunction with a clear field mask, or direct electron beam exposure, is used to define a gate region. After exposure, the resist is developed, leaving the unexposed portion of the resist in place on the polyimide layer. A metal transfer layer is then deposited over the structure, and the remaining resist is dissolved leaving a hole in the metal transfer layer. The polyimide and the passivating layer are etched down to the surface of the substrate through the passivating layer. The substrate is then dry etched, and then wet chemical etched to form a recess for the Schottky gate. The Schottky gate metal is deposited onto the surface of the structure and through the hole onto the substrate.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: May 12, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Thomas W. Taylor, Donald C. D'Avanzo
  • Patent number: 5096846
    Abstract: A method for forming a quantum effect switching device is disclosed which comprises the step of forming a heterostructure substrate 10. A silicon nitride layer 22 is formed on an outer surface of the substrate 10. An aluminum mask body 30 is formed using a lift-off procedure. Aluminum mask body 30 is then used to form a silicon nitride mask body 32 from the silicon nitride layer 22 using a CF.sub.4 /O.sub.2 reactive ion etch process. A boron trichloride etch process is then used to form a dual column structure 34 while removing the aluminum mask body 30. A buffered HF wet etch process removes the silicon nitride mask body 32. Separate metal contacts can then be made to electrically separate points on the outer surface of the dual column structure 34.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: March 17, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: John N. Randall
  • Patent number: 5094980
    Abstract: By means of conventional deposition and lift-off processes, a metal contact plate is simultaneoulsy placed over transistor junction surfaces and over the surrounding field oxide boundary. After this process step, a dielectric layer, insulating the metal interconnect from the gate interconnect, is deposited and contact openings are plasma etched down to the metal contact plate, which acts to prevent erosion of the junction surface and the field oxide layer. When a diffusion barrier metal is used, the thermal stability of the contact resistance and the electromigration susceptibility are improved. While maintaining minimum transistor design dimensions and required alignment tolerances, the contacting metal plate allows for an increase in the contact opening area.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: March 10, 1992
    Assignee: Digital Equipment Corporation
    Inventor: Adam Shepela
  • Patent number: 5093280
    Abstract: A process for forming refractory metal ohmic contacts comprises masking a group III-V semiconductor substrate and opening windows thereon. Metal ions are implanted through the window to a sufficient concentration to connect to electronic features in the substrate. Following implantation, a refractory metal ohmic contact is deposited in the same windows and is passivated. Next, the implanted ions are activated by annealing so the refractory metal ohmic contacts are electrically connected to the electrical features in the substrate.
    Type: Grant
    Filed: July 25, 1989
    Date of Patent: March 3, 1992
    Assignee: Northrop Corporation
    Inventor: John W. Tully
  • Patent number: 5091342
    Abstract: A multilevel resist process for fine line e-beam lithography, or, alternatively, deep ultraviolet (DUV) optical lithography with a clear field mask involving the use of a plated transfer layer for image reversal. The process preferably uses a high brightness, quarter-micron diameter electron beam and a high speed negative resist to fabricate microwave MESFETs, MODFETs, and integrated circuits with gate lengths of 0.25 micron and below. This is achieved by producing a line of negative resist which can be developed to 0.25 micron or below. A plated transfer layer is then applied which provides image reversal, converting the line of resist into an opening suitable for conventional gate recess etching, gate metal deposition, and lift-off. A positive resist can be substituted for the negative e-beam resist and exposed with DUV through a clear field mask instead of an electron beam for the fabrication of MESFETs.
    Type: Grant
    Filed: February 24, 1989
    Date of Patent: February 25, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Lawrence G. Studebaker, Edward H. Wong
  • Patent number: 5084409
    Abstract: Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: January 28, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Edward A. Beam, III, Yung-Chung Kao
  • Patent number: 5068207
    Abstract: A planar surface is produced in integrated circuit processing by patterning a bilevel structure of a conductor and a sacrificial layer followed by directional deposition of a dielectric and lift off of the sacrificial layer. An additional dielectric layer may now be deposited if desired.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: November 26, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Ajit S. Manocha, Chen-Hua D. Yu
  • Patent number: 5059552
    Abstract: A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.
    Type: Grant
    Filed: March 15, 1991
    Date of Patent: October 22, 1991
    Assignee: International Business Machines Corporation
    Inventors: Christoph S. Harder, Wilhelm Heuberger, Peter D. Hoh, David J. Webb