Abstract: A method of manufacturing a nonvolatile memory device having a self-aligned structure includes the steps of forming a gate insulating film on a semiconductor substrate of a first conductivity type. A semiconductor layer is formed on the gate insulating film and etched to form floating gates and a semiconductor pattern between the floating gates. Impurity ions of a second conductivity type are implanted into the same side of the substrate as the floating gate is formed, to form a drain region. A planarizing film is deposited on the substrate and etched until the upper surfaces of the floating gates and the semiconductor pattern are exposed. The semiconductor pattern is removed and impurity ions of the second conductivity type are implanted into the substrate, to form a source region. The planarizing film is removed to expose the floating gate, and a dielectric film is formed thereon. Finally, a control gate is formed on the substrate.

Abstract: A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

Abstract: Hybrid circuit structures and methods of fabrication particularly suitable for the fabrication of high density multi-layer interconnects utilizing silicon substrates are disclosed. In accordance with the method, a layer of alumina is put down over the silicon substrate, typically having an oxide layer thereover, which layer of alumina acts as a blocking barrier to any subsequent plasma etching process for etching polymer layers thereover during the subsequent high density multilayer interconnect fabrication steps. Various representative high density multi-layer interconnect structures on silicon substrates and methods of forming the same are disclosed, including the inclusion of an adhesion enhancement layer over the layer of alumina to enhance the adhesion of a polymer which would not otherwise adhere well directly to the layer of alumina.

Abstract: Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type.

Abstract: A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.

Abstract: An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask.

Abstract: There is disclosed a method of manufacturing an integrated circuit, comprising: the first step of growing a first epitaxial crystal on a compound semiconductor substrate, removing an unnecessary region of the first epitaxial crystal to form a residual portion, and covering the residual portion with a selective growth mask, the second step of growing a second epitaxial crystal on an exposed substrate portion, removing an unnecessary portion of the second epitaxial crystal to form a residual portion of the second epitaxial crystal, and covering the residual portion of the second epitaxial crystal with a selective growth mask, and third step of growing a third epitaxial crystal on an exposed substrate portion and removing an unnecessary region of the third epitaxial crystal, wherein the first to third epitaxial crystal form any one of a pin photodiode crystal, a heterojunction bipolar transistor crystal, and a high electron mobility transistor crystal, and are different from each other.

Abstract: A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.

Abstract: The process calls for determination of the contact areas occupied by the collector, emitter and base implantations by selective removal of a layer of oxidation resistant material only from said contact areas and not from the separating zones between said areas.

Abstract: An improved method for making a self-aligned vertical field effect transistor is provided wherein a nitride sidewall spacer is formed around a polysilicon gate, and an oxide sidewall spacer, which may be heavily doped with an n-type dopant, is formed covering the silicon nitride sidewall spacer. The silicon nitride sidewall spacer allows the oxide sidewall spacer of a conventional self-aligned vertical field effect transistor process to be removed partially or completely before making ohmic contact to the source thus increasing the contact area between the source and the source electrode and eliminating reliability problems related to n-type doped oxide in contact with aluminum electrodes.

Abstract: A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

Abstract: A method is disclosed for making twin tub devices with trench isolation. The trench mask is obtained in a self-aligned manner employing tub masks that define an overlapping region at the trench. In one embodiment, the N-tub mask is defined by patterning resist (4) and polysilicon (3) overlying silicon oxide (2). The P-tub mask is defined by patterning resist (9). The oxide at the overlapping region between the tubs is removed, resulting in trench mask (2', 2") for forming trench (15). In another embodiment, the N-tub mask is defined by patterning resist (23) and silicon nitride (22). The P-tub mask is then defined by patterning resist (27) and nitride (22'). Self-aligned oxide regions (31) formed around nitride (22')serve as a trench mask for forming trench (32).

Abstract: For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.

Abstract: The present invention is to provide a method for manufacturing a semiconductor device of high efficiency and high integration density. The method for manufacturing a semiconductor device comprises the steps of forming semiconductive layers (30), (31) and (31') having on the surface thereof a concave portion, forming a nitride layer (35) within the concave portions forming with the nitride layer (35) as a mask an oxide layer (39) on the surface of the semiconductive layer (30), removing said nitride layer (35) and introducing an impurity into the semiconductive layers (31) and (31') with the oxide layer (39) as a mask. In accordance therewith, the elements can be made finer and hence the method of this invention is suitable for manufacturing an IC device high in efficiency and high in integration density.

Abstract: A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO.sub.2 layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO.sub.2 layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO.sub.2 layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO.sub.2 layer. A semiconductor device with a high density and a high speed is realized.