Mask, Movable Patents (Class 148/DIG104)
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Patent number: 5622787Abstract: A mask for transferring a pattern in which durability can be improved and a very fine circuit pattern of a light-shielding film can be formed, and a manufacturing method thereof are obtained. In the mask for transferring a pattern, a silicon monocrystalline film 2, an aluminum monocrystalline film 3 and an aluminum oxide film 4 are formed on a mask substrate 1 so as to have a prescribed pattern feature. Silicon monocrystalline film 2 and aluminum monocrystalline film 3 serve as the light-shielding film. Aluminum oxide film 4 serves as an anti reflection and protection film.Type: GrantFiled: September 26, 1994Date of Patent: April 22, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor Systems Engineering CorporationInventors: Hirofumi Sakata, Tadashi Nishioka
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Patent number: 5420067Abstract: A non-optical method for the formation of sub-half micron holes, vias, or trenches within a substrate. For example, a substrate having at least two buttresses or a trench having a interbuttress distance or a width of 1.0 to 0.5 microns, respectively, is conformally or non-conformally lined with a layer material. Thereafter, the layer material from horizontal surfaces is removed to expose the substrate underneath while leaving the layer material attached to the essentially vertical walls of the buttresses or the trenches essentially intact, thereby, narrowing the interbuttress distance or the trench width, respectively, to sub-half micron dimensions. The exposed substrate surface is then subjected to anisotropic etching to form sub-half micron trenches, holes or vias in the substrate. Finally, the buttresses and layer material are removed from the substrate.Type: GrantFiled: September 20, 1993Date of Patent: May 30, 1995Assignee: The United States of America as represented by the Secretary of the NavyInventor: David S. Y. Hsu
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Patent number: 5413956Abstract: A method for producing a semiconductor laser device includes the steps of: forming window layers on either one of a top surface of an internal structure or a reverse surface of a substrate and on light-emitting end facets of the internal structure; forming a reflection film on the light-emitting end facets; removing the window layer formed on either one of the top surface or the reverse surface by using an etchant which hardly etches the reflection film; and forming electrodes on the surface from which the window layer is removed by etching and on the other surface. Another method for producing a semiconductor laser device includes the steps of: forming window layers on light-emitting end facets of the bars; inserting the bars into an apparatus having openings for forming electrodes and a supporting portion for preventing a positional shift between the bars and the openings, and forming the electrodes on the top surfaces and the reverse surfaces of the bars; and cutting the bars into the chips.Type: GrantFiled: December 22, 1992Date of Patent: May 9, 1995Assignee: Sharp Kabushiki KaishaInventors: Masanori Watanabe, Ken Ohbayashi, Kazuaki Sasaki, Osamu Yamamoto, Mitsuhiro Matsumoto
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Patent number: 5306665Abstract: As a stack of a patterned film and an overlying conductor film, a conductor pattern is manufactured on an isolation layer of a semiconductor device by forming a two-film layer of a first conductor film and a semiconductor film, patterning the two-film layer in compliance with the conductor pattern into a patterned layer consisting of the patterned film and a semiconductor pattern and having a layer side surface, forming an insulator side wall on the side surface, etching away the semiconductor pattern, and selectively forming a second conductor film as the overlying conductor film. The side wall is used in preventing, when the second conductor film is selectively grown, undesirable lateral growth. Typically, the first and the second conductor films are made of aluminium to thicknesses of 200 and 400 nm and the semiconductor film, of polysilicon to a thickness of 400 nm.Type: GrantFiled: October 6, 1993Date of Patent: April 26, 1994Assignee: NEC CorporationInventor: Kazutaka Manabe
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Patent number: 5294565Abstract: An epitaxial growth method of a single crystal of III-V compound semiconductor on the surface of a semiconductor substrate by supplying a molecular beam of a group III source material and a molecular beam of a group V source material onto the surface of the substrate in a chamber held in vacuum. With this method, the molecular beams comprises a molecular beam of a first group III source material composed of an organic metal compound of a group III element not having a halogen, a molecular beam of a second group III source material having a halogen chemically bonded to atoms of the group III element, and a molecular beam of a group V source material making a compound semiconductor with the group III element of the first group III material. By setting a substrate temperature at, for example, about 500.degree. C. a single crystal of III-V compound semiconductor can be satisfactorily selectively grown.Type: GrantFiled: July 22, 1992Date of Patent: March 15, 1994Assignee: NEC CorporationInventor: Yasushi Shiraishi
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Patent number: 5213992Abstract: A new method to produce a microminiturized capacitor having a regular microscopic ripple surface electrode is achieved by depositing a first polysilicon layer over a suitable insulating base. A resist layer is formed over the first polysilicon layer. The resist layer is exposed through a mask having a pattern of regular spaced openings in the areas of the planned capacitor to radiant energy in sufficient quantity to under expose, out of focus expose or a combination of under expose and out of focus expose the resist layer. The mask is shifted a fixed and short distance. The resist layer is exposed through the shifted mask to radiant energy in sufficient quantity to under expose or out of focus expose, or a combination of under expose or out of focus expose the resist layer again and in a different location. The shifting of the mask and exposing resist steps are repeated until a pattern of the regular microscopic ripple has been formed in the resist layer.Type: GrantFiled: October 2, 1991Date of Patent: May 25, 1993Assignee: Industrial Technology Research InstituteInventor: Chih-Yuan Lu
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Patent number: 4929571Abstract: A semiconductor laser includes a semiconductor substrate on which a longitudinal groove is provided in the resonator direction, a first semiconductor layer disposed on a region of the semiconductor substrate where the groove is not provided and forming a rectifying junction therewith, a first cladding layer provided on the semiconductor substrate in the groove, an active layer provided on the first cladding layer in the groove, and a second cladding layer provided directly on the active layer and opposite the first semiconductor layer with an interposed insulating layer, such as a gap void of solid material or a gap and current blocking material having only negligible parasitic capacitance.Type: GrantFiled: March 10, 1989Date of Patent: May 29, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Etsuji Omura, Hirofumi Namizaki
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Patent number: 4883770Abstract: A molecular beam epitaxy (MBE) process in which some portions of the substrate are shadowed by a shadow mask from receiving at least one of the molecular beams used in the MBE process. This process is capable of producing NIPI superlattices that have selective contacts that are far superior to those which can be produced at present. This technique can also produce a wide variety of NIPI devices as well as other types of IC structures.Type: GrantFiled: January 17, 1989Date of Patent: November 28, 1989Assignee: Hewlett-Packard CompanyInventors: Gottfried H. Dohler, Ghulam Hasnain, Jeffrey N. Miller
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Patent number: 4880754Abstract: A method for providing engineering changes to LSI PLAs. One or more additional input lines, output lines, and/or product terms are provided in the overall mask set, however, logically unconnected to the rest of the PLA, which is designed to provide the desired PLA function. The additional lines and terms are provided so as to be able to be connected to the PLA, and provide additional personalization by changes to the contact mask and masks for subsequent process steps to contact. The invention may be incorporated in an existing PLA macro assembler system. By simply redefining certain cells the additional devices may be incorporated through those redefined individual cells. Thus, the invention is relatively easy to retrofit to existing PLA macro assembler systems.Type: GrantFiled: July 6, 1987Date of Patent: November 14, 1989Assignee: International Business Machines Corp.Inventor: Anthony Correale
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Patent number: 4771017Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.Type: GrantFiled: June 23, 1987Date of Patent: September 13, 1988Assignee: Spire CorporationInventors: Stephen P. Tobin, Mark B. Spitzer
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Patent number: 4675981Abstract: A method of manufacturing an MOS transistor comprises the steps of forming a silicon nitride film on a central portion of a P-type silicon substrate, forming a first resist pattern on the semiconductor substrate and the film using a mask member having a central opening, ion-implanting a first impurity of P-type into the substrate using the first resist pattern and the film as masks, removing the first resist pattern from the semiconductor substrate, forming a second resist pattern on the substrate using the mask member, and ion-implanting a second impurity of P-type into the substrate at a low acceleration voltage using the second resist pattern as a mask. Then, a gate electrode is formed on the substrate and an impurity of n-type is implanted into the substrate to form source and drain regions of n-type.Type: GrantFiled: November 25, 1985Date of Patent: June 30, 1987Assignee: Kabushiki Kaisha ToshibaInventor: Kiyomi Naruke