Abstract: A method is disclosed for integrating one or more microelectromechanical (MEM) devices with electronic circuitry on a common substrate. The MEM device can be fabricated within a substrate cavity and encapsulated with a sacrificial material. This allows the MEM device to be annealed and the substrate planarized prior to forming electronic circuitry on the substrate using a series of standard processing steps. After fabrication of the electronic circuitry, the electronic circuitry can be protected by a two-ply protection layer of titanium nitride (TiN) and tungsten (W) during an etch release process whereby the MEM device is released for operation by etching away a portion of a sacrificial material (e.g. silicon dioxide or a silicate glass) that encapsulates the MEM device. The etch release process is preferably performed using a mixture of hydrofluoric acid (HF) and hydrochloric acid (HCI) which reduces the time for releasing the MEM device compared to use of a buffered oxide etchant.

Abstract: A method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.

Abstract: A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.

Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.

Abstract: A process for fabricating a MOS device having a recessed gate on a silicon substrate. Source/drain regions are formed by implanting impurities of a first conductivity type into a silicon substrate. A trench is formed in the silicon substrate, the trench being separated from the source/drain regions by side wall spacers on side walls of the trench. The source/drain regions extend to areas underlying the sidewall spacers. An anti-punchthrough region is formed by implanting impurities of a second conductivity type into a portion of the silicon substrate underlying the trench. A gate layer is formed within the trench, the gate layer being separated from the anti-punchthrough region by a gate oxide layer.

Abstract: A thin-film field-effect transistor is fabricated by forming an electrically insulative island between the source and the drain. A cap is formed on the island with a brim that overhangs the island. A layer of source-drain metal, which will subsequently constitute the source and drain contacts, is then deposited upon the source, the drain, and the cap, but the overhang creates an exposed region which can be attacked by an etchant. When the etchant is applied, it etches away the cap, thereby lifting off the source-drain metal which coated the cap, leaving the fully formed source and drain contacts separated by the island.

Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening.

Abstract: A process for formation of a thin film transistor liquid crystal display is disclosed, in which an etch-back type 3-mask process or an etch stopper type 4-mask process is applied, so that the semiconductor layer of the thin film transistor can be isolated from the data line. Consequently, the optical leakage current which aggravates the performance of the transistor is inhibited. Further, the data line is composed of a material which has a low chemical reactivity with ITO, so that a corrosion due to a chemical reaction between the data line and ITO can be eliminated.

Abstract: The present invention provides a method for manufacturing a capacitor in a semiconductor device which increases a capacitance of the memory cell and improves a step coverage of a conducting material. The present invention provides a method for manufacturing a capacitor in a semiconductor device, comprising steps of: forming a first conducting layer 2, an oxide layer 3 and an A--B alloy 4a on an insulation layer 1 sequentially; settling a superfluous B material 4c dissolved in a A material 4b on the oxide layer 3 by a heat treatment so that the B material is separated from the A material; only etching the A material 4b by an echant and etching an exposed oxide layer 3 by using a settled B material 4c as an etch barrier; and etching an exposed first conducting layer 2 up to an intended depth by using the separated B material 4c and a residual oxide layer 3 as an etch barrier.

Abstract: The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.

Abstract: The process for making a matrix of thin layer transistors with memory capacitors includes forming a first conductive layer on a substrate, and in a first mask step, etching it to form row conductors of the matrix, gate contacts of the thin layer transistors and ground electrodes of the memory capacitors; forming a gate-insulating layer for the thin layer transistors; forming a semiconductor layer, especially an a-Si:H semiconductor layer; applying a p- or n-doped semiconductor layer to provide drain and source contacts; forming and etching a second conductive layer for the column conductors of the matrix of the thin layer transistors, the drain and source contacts of the thin layer transistors and the counter electrodes of the memory capacitors in a second mask step; plasma etching of the doped semiconductor layer with the second conductor layer acting as mask and determining an end of the etching process by observing the optical emission of an etching plasma used for the plasma etching; etching the undoped s

Abstract: Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

Abstract: An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

Abstract: A thin-film transistor panel is constituted by forming, on an insulating substrate, a plurality of thin-film transistors, a plurality of gate lines for each connecting gate electrodes of the thin-film transistors, and a plurality of pixel electrodes formed of a transparent conductive film connected to the thin-film transistors, then forming a low-resistance metal film of an Al or Al alloy for a data line and a surface metal film of Cr with a high density, forming a photoresist film of a predetermined pattern on the surface metal film, and etching the data line metal film and surface metal film. Then, the surface metal film remaining on the data line metal film is eliminated.

Abstract: A thin-layer metallization structure in which the final gold layer is deposited by evaporation with the surface onto which it is evaporated maintained at an elevated temperature. By evaporating the uppermost gold layer of the structure at an elevated substrate temperature, the gold atoms have a higher mobility, causing the deposited gold to spread over the edge of the structure and cover the otherwise exposed edges, including the edge at the copper interface.

Abstract: A method of forming a metal via on a semiconductor substrate having a metal layer and a dielectric layer on the metal layer, which uses an intermediate mask layer as a mask in forming the metal via instead of using a photoresist as a mask. Therefore, the spin-on glass (SOG) layer in the dielectric layer is not exposed to plasma or solvent, thereby preventing the formation of polymers which cause poor step coverage and sometimes even contact failure in the metal via.

Abstract: A method of manufacturing a semiconductor device which comprises steps of forming a diffusion region to a semiconductor substrate; forming silicon compound film on the diffusion region; forming a metal film on the silicon compound film to form a metal silicide film and, further forming an interlayer film; forming a barrier metal material film on the interlayer film; then patterning the barrier metal material film to obtain a barrier metal layer, subsequently; patterning the interlayer film to form a contact hole and burying a wiring material into the contact hole thereby forming a wiring.

Abstract: A semiconductor device is manufactured using the electron beam exposure method. A resist is applied on an interlayer dielectric film through a thin metal film, and a contact hole is formed in the interlayer dielectric film. The thin metal film is utilized as a part of a second metal wiring pattern after removing its surface oxides.

Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.

Abstract: A method of fabricating a semiconductor device in which first an aluminum film is etched using a photoresist pattern as a mask, and then the patterned aluminum film is used as a mask for plating to form a pattern of gold plating film. In so doing, if a wiring is formed using a plating process, the problems of deformity of the gold plating film due to degradation of a plating solution, short-circuits between the patterns due to cracks in the plating mask, and re-adhering of etched material when etching the electrical current paths used during the electroplating process, and the problem of sideways etching can be solved.

Abstract: A semiconductor device with air-bridge interconnection comprises: a substrate; a plurality of mesas with distance therebetween smaller than a predetermined value; and a metal layer supported by the plurality of mesas, the metal layer having a narrow portion at the intermediate portion thereof and both ends having larger width than the narrow portion. The air-bridge interconnection is obtained by side-etching controlled during dry-etching using interconnection metal layer as an etching-mask to remove a mass of semiconductor material under the interconnection metal layer.

Abstract: A method of making a thin film transistor exhibiting a high channel conductance includes the steps of forming, on an insulating transparent substrate, a gate electrode, an insulating layer, a semiconductor layer, a photoresist, in this order and performing a back substrate exposure at the insulating transparent substrate using the gate electrode as a photo mask, to form a photoresist pattern. The photoresist pattern is then baked to make it flow outward to a desired bottom width. The semiconductor layer is etched using the photoresist pattern as an etch mask to form a semiconductor layer pattern. On the resultant entire exposed surface are formed an ohm contact layer and a metal layer. The metal layer is then subjected to photoing and etching processes, to remove its portion disposed above the semiconductor pattern and its opposite side edge portions, thereby forming a metal layer pattern for source and drain electrodes.

Abstract: On an insulating film (12) covering the surface of a semiconductor substrate (10), a gate electrode layer (14), a gate insulating film (16), and a semiconductor layer (18) such as silicon are sequentially deposited to form an under-gated MOS transistor. A flat coating film such as resist is formed covering the semiconductor layer (18). The coating film is then etched back to expose the surface of the semiconductor layer (18) at the area above the gate electrode layer (14). The left coating film is used as the mask for the selective growth of a mask material layer (24) such as tungsten on the exposed surface of the semiconductor layer (18) with a side-projection. After removing the left coating film, impurity ions such as BF2 are selectively injected in the semiconductor layer (18) using the mask material layer (24) as the mask to form a source region (18S) and a drain region (18D).

Abstract: A method is disclosed for alloying a sputtered metal film by forming a sputtered metal film of first metal atoms over a semiconductor substrate through a first mask and implanting a first impurity of second metal atoms into the sputtered film. Then a second mask having at least one window is formed on the sputtered film by removing said first mask and a second impurity of third metal atoms is then implanted. The substrate and film are then heat treated to form a first alloy area in which the first metal atoms and the second metal atoms are mixed and a second alloy area in which the first metal atoms and the third metal atoms are mixed.

Abstract: An epitaxial growth method of a single crystal of III-V compound semiconductor on the surface of a semiconductor substrate by supplying a molecular beam of a group III source material and a molecular beam of a group V source material onto the surface of the substrate in a chamber held in vacuum. With this method, the molecular beams comprises a molecular beam of a first group III source material composed of an organic metal compound of a group III element not having a halogen, a molecular beam of a second group III source material having a halogen chemically bonded to atoms of the group III element, and a molecular beam of a group V source material making a compound semiconductor with the group III element of the first group III material. By setting a substrate temperature at, for example, about 500.degree. C. a single crystal of III-V compound semiconductor can be satisfactorily selectively grown.

Abstract: The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

Abstract: A method of manufacturing a semiconductor device having a photoconductive semiconductor layer formed on a substrate and a pair of electrodes formed on the semiconductor layer with an ohmic contact layer interposed therebetween, wherein the ohmic contact layer is removed after the etching process of the semiconductor layer.

Abstract: A method is described for forming patterns in deposited overlayers on GaAs and for aligning the formed patterns with etch features produced through dry processing. The deposited overlayers on GaAs are protected during pattern formation and subsequent processing by a durable, process integrable mask of hydrogenated amorphous carbon.

Abstract: An improved field implant process is disclosed wherein the field implant is performed after the field oxide isolation structure is fabricated by masking the active surface regions of the substrate with tungsten. The tungsten may be selectively deposited or blanket deposited. The energy of the field implant is controlled and adjusted to produce a maximum number of ions contiguous to a thinnest portion of field oxide with other portions being self-regulating.

Abstract: A GaAs epitaxial layer is formed on a semi-insulative GaAs substrate by use of a crystal growth technique which allows control on the order of atomic layer level. A metal film is formed on the GaAs epitaxial layer by use of the same crystal growth technique. Ions are implanted in source and drain high-concentration layer-forming regions, through the metal film, and are activated.

Abstract: An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Abstract: The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.

Abstract: Provided is a process for precisely forming a Schottky barrier gate on GaAs. In the process, a layer of polyimide is spun onto a doped GaAs substrate having a passivating layer thereon. A resist layer is then spun onto the polyimide, and either deep ultraviolet lithography in conjunction with a clear field mask, or direct electron beam exposure, is used to define a gate region. After exposure, the resist is developed, leaving the unexposed portion of the resist in place on the polyimide layer. A metal transfer layer is then deposited over the structure, and the remaining resist is dissolved leaving a hole in the metal transfer layer. The polyimide and the passivating layer are etched down to the surface of the substrate through the passivating layer. The substrate is then dry etched, and then wet chemical etched to form a recess for the Schottky gate. The Schottky gate metal is deposited onto the surface of the structure and through the hole onto the substrate.

Abstract: Nanometer thick vertical metallic structures are fabricated on a substrate by depositing a metallic layer on a substrate surface on which one or more buttresses are formed, etching the metallic layer to expose the horizontal surfaces of the substrate and the buttresses, and etching the substrate to remove the buttresses, thereby producing vertical structures on the substrate. The metallic layer is formed by thermal decomposition of a volatile metal-containing precursor gas in the presence of a carrier gas at low pressure, unlike that in conventional CVD reactors. The metallic layer thus formed has a grain size which is fraction of the thickness of the vertical structure.

Abstract: A process for forming refractory metal ohmic contacts comprises masking a group III-V semiconductor substrate and opening windows thereon. Metal ions are implanted through the window to a sufficient concentration to connect to electronic features in the substrate. Following implantation, a refractory metal ohmic contact is deposited in the same windows and is passivated. Next, the implanted ions are activated by annealing so the refractory metal ohmic contacts are electrically connected to the electrical features in the substrate.

Abstract: A multilevel resist process for fine line e-beam lithography, or, alternatively, deep ultraviolet (DUV) optical lithography with a clear field mask involving the use of a plated transfer layer for image reversal. The process preferably uses a high brightness, quarter-micron diameter electron beam and a high speed negative resist to fabricate microwave MESFETs, MODFETs, and integrated circuits with gate lengths of 0.25 micron and below. This is achieved by producing a line of negative resist which can be developed to 0.25 micron or below. A plated transfer layer is then applied which provides image reversal, converting the line of resist into an opening suitable for conventional gate recess etching, gate metal deposition, and lift-off. A positive resist can be substituted for the negative e-beam resist and exposed with DUV through a clear field mask instead of an electron beam for the fabrication of MESFETs.

Abstract: A method for manufacturing an amorphous silicon thin film transistor in which a gate insulating layer is provided over a gate on a substrate. An amorphous silicon layer is formed on the gate insulating layer, and a protective insulating layer is formed on the amorphous silicon layer. A pattern conforming to the gate is applied to the protective layer, and the amorphous layer is exposed in regions outside of the pattern. A doped silicon layer is then added, and source and drain electrodes formed to partly overlap the remaining protective insulating layer.

Abstract: A method of making a pattern of tungsten interconnection comprising the step of: forming a polysilicon film (18) over a first insulating film (12) on a semiconductor substrate (11) and doping impurities; forming a high doped oxide film (19) over the polysilicon film and subsequently forming a metal interconnect pattern; growing selectively tungsten (15) on an exposed portion of the polysilicon film; stripping the high doped oxide film by wet etching and etching a residual (20) of the tungsten formed on the oxide film; and dry etching the polysilicon by using the tungsten on the polysilicon as a etching mask leaving only the polysilicon underneath the tungsten. The method can solve the troubles produced when the tungsten is used as metal interconnect material and improve the operation speed of the semiconductor devices with the interconnection of the tungsten metal, offering a reliability of the device for a long time operation.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used as an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used to mask for a second ion implantation.

Abstract: A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.

Abstract: A textured substrate is disclosed which is amenable to deposition thereon of epitaxial single crystal films of materials such as diamond, cubic boron nitride, boron phosphide, beta-silicon carbide, and gallium nitride. The textured substrate comprises a base having a generally planar main top surface from which upwardly extends a regular array of posts, the base being formed of single crystal material which is crystallographically compatible with epitaxial single crystal materials to be deposited thereon. The single crystal epitaxial layers are formed on top surfaces of the posts which preferably have a quardrilateral cross-section, e.g., a square cross-section whose sides are from about 0.5 to about 20 micrometers in length, to accommodate the formation of substantially defect-free, single crystal epitaxial layers thereon. The single crystal epitaxial layer may be selectively doped to provide for p-type and p.sup.

Abstract: An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lightly-doped region and the resultant degradation in the characteristic are eliminated.

Abstract: The invention provides a method for patterning a submicron opening in a layer of semiconductor material. The method comprises use of conventional photolithography to position a sidewall spacer in a predetermined location on a semiconductor device. A layer of cobalt is selectively reacted with an underlying layer to form an image reversal layer which functions as a hard mask. The submicron features are then transferred into the underlying layer of semiconducting material by etching.

Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.

Abstract: A method for fabricating an active matrix substrate is disclosed which includes the following steps: forming an island region of a first semiconductor film on a prescribed insulating substrate; forming a first insulating film and a second semiconductor film on said first insulating film; forming a second insulating film on said second semiconductor film and thereafter forming a prescribed pattern of the second insulating film; depositing prescribed metal on the pattern and thereafter forming a compound of the second semiconductor film and the metal; removing unreacted portion of the metal; and etching said second semiconductor film and said first insulating film using said compound as a mask.

Abstract: A process for creating a metal etch mask from either cobalt, nickel, palladium, iron or copper which may be utilized for halogen-plasma excavation of deep trenches. The process begins by creating a thin isolation layer of either silicon nitride or silicon dioxide on top of the layer to be trenched. A thin layer of one of the metals selected from the aforementioned list of five is then created on top of the isolation layer. A layer of polysilicon is then blanket deposited on top of the refractory metal layer. Photoresist masking is then performed as though the photoresist were the actual pattern for the trench etch. Exposed portions of the polysilicon layer are then etched away with an anisotropic etch. Following a photoresist strip, the substrate and overlying layers are subjected to an elevated temperature step, which causes the polysilicon to react with the underlying metal layer to form metal silicide. In substrate regions where no polysilicon overlies the metal layer, no silicide is formed.

Abstract: A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members.

Abstract: A process for fabricating a vertical DMOS transistor is set forth. The starting material is a heavily doped silicon wafer which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on.

Abstract: A method of manufacturing a semiconductor device, in which a first pattern of conductors (20), an isolating layer (21) and a second pattern of conductors (22) are successively provided on a surface (2) of a semiconductor body (1) adjoined by a number of isolation regions (4, 10) and a number of semiconductor regions (3). Mutual contacts are established between the two patterns (20, 22) and these contacts are located both above a semiconductor region (3) and above an adjoining isolation region (4, 10) by forming conductive pillars (44) in the first pattern (20), exposing a tip (51) of the pillars (44) after an isolating layer (50) has been provided and providing the second pattern (22) over the tip (51) of the pillars (44). Thus, a large amount is saved on the surface (2).