Memory Devices Patents (Class 148/DIG109)
  • Patent number: 5702959
    Abstract: A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N+ type buried layer impurity (18) is introduced into a surface region of the first lightly doped layer (12) that will underlie and define an island in which the vertical transistor will be constructed. A second lightly doped P- layer (16) is epitaxially grown on the first lightly doped layer (12) and the buried layer impurity (18). An N+ type isolation impurity is diffused into the second layer to form wells to laterally enclose an island (22) of the second layer (16) above the buried layer impurity (18). An N type base impurity (28) is diffused into the island (22) region of the second layer (16), and a P type emitter impurity (30) is diffused into the base region (28).
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: December 30, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Louis N. Hutter, Jeffrey P. Smith
  • Patent number: 5668034
    Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: September 16, 1997
    Assignee: Intel Corporation
    Inventors: George E. Sery, Jan A. Smudski
  • Patent number: 5510278
    Abstract: An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: April 23, 1996
    Assignee: Motorola Inc.
    Inventors: Bich-Yen Nguyen, Thomas F. McNelly, Philip J. Tobin, James D. Hayden
  • Patent number: 5427968
    Abstract: An electronically erasable and reprogrammable memory integrated circuit device having split-gate memory cell with separated tunneling regions and its process of fabrication are disclosed. A silicon substrate having field oxide layers isolating component regions are processed to construct a memory cell in each of the isolated component region. Each of the memory cells includes a drain and source region formed in the silicon substrate, with a channel formed between the drain and source regions. Ring-shaped floating gate surrounds and covers the periphery of the channel and is isolated with the drain and source regions respectively by two thin tunneling oxide layers that are separated from each other. The two separated tunneling oxide layers constitute two separated tunneling regions. A control gate layer covers the ring-shaped floating gate and the portion of the channel that is not covered by the floating gate layer, and is separated from the floating gate by an isolation layer.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: June 27, 1995
    Assignee: United Microelectronics Corp.
    Inventor: Gary Hong
  • Patent number: 5234853
    Abstract: A high voltage MOS transistor includes a semiconductor substrate (1) of a first semiconductor type, a gate electrode (14) formed on the semiconductor substrate via a gate oxide layer (13), first and second diffusion regions (15, 16) formed in the semiconductor substrate on both sides of the gate electrode and being of a second semiconductor type opposite to the first semiconductor type, and an electrode (38) which is directly connected to the first diffusion region (15) and is made up of a conductor layer (49) including polysilicon. An impurity concentration of the conductor layer (49) including the polysilicon is higher than an impurity concentration of the first diffusion region (15).
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: August 10, 1993
    Assignee: Fujitsu Limited
    Inventor: Shinichirou Ikemasu
  • Patent number: 5232868
    Abstract: A method for forming a thin semiconductor film comprises the steps of supplying on a surface of a heated substrate a first material gas composed of germanium halide or germanium hydro-fluoride obtained by partially substituting fluorine of the germanium fluoride together with a second material gas composed of silicon hydride or silicon fluoro-hydride obtained by partially substituting hydrogen of the silicon hydride with fluorine and causing a chemical reaction between the first and second material gases, thereby growing a thin film containing germanium over the surface of the substrate. By controlling the substrate temperature or flow rate ratio of the first material gas to the second material gas, an optical gap of the thin film grown can be controlled.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: August 3, 1993
    Assignee: Agency of Industrial Science and Technology
    Inventors: Yutaka Hayashi, Mitsuyuki Yamanaka
  • Patent number: 5213990
    Abstract: A method for connecting different conducting layers of a microelectronic device is disclosed.
    Type: Grant
    Filed: April 1, 1992
    Date of Patent: May 25, 1993
    Assignee: Texas Instruments, Incorporated
    Inventor: Mark S. Rodder
  • Patent number: 5156987
    Abstract: The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: October 20, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Pierre Fazan
  • Patent number: 5156990
    Abstract: A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implant of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: October 20, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Allan T. Mitchell
  • Patent number: 5147813
    Abstract: A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 .ANG. thickness. The second layer is a silicon dioxide layer of approximately 20-30 .ANG.. The third layer is polysilicon of approximately 1000-1500 .ANG. thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: September 15, 1992
    Assignee: Intel Corporation
    Inventor: Been-Jon Woo
  • Patent number: 5118640
    Abstract: A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulatin
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: June 2, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Taku Fujii, Narakazu Shimomura
  • Patent number: 5100822
    Abstract: Disclosed is a semiconductor device having grooves extending from the semiconductor substrate surface into the interior of the substrate, the grooves having an insulating layer, such as an oxide layer, on the surfaces thereof, with the insulating layer being covered with a conductive layer. The corners of the grooves are rounded-off, whereby the electrostatic destruction voltage of the insulating film is increased as compared with using grooves without having rounded-off corners. Also disclosed is a method of making such device, including steps of forming an initial insulating film on the surfaces of the grooves and removing such initial insulating film to expose surfaces of the grooves, the grooves thereby being provided with rounded-off corners, and then sequentially forming an insulating layer and then a conductive layer on the surfaces of the grooves.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: March 31, 1992
    Assignee: Hitachi, Ltd.
    Inventor: Shinichiro Mitani
  • Patent number: 5100828
    Abstract: A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulatin
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: March 31, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Taku Fujii, Narakazu Shimomura
  • Patent number: 5081057
    Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect to the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to and from the floating gate through an original self-aligned process, which allows limiting the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.
    Type: Grant
    Filed: June 1, 1990
    Date of Patent: January 14, 1992
    Assignee: SGS-Thomson Microelectronics
    Inventor: Giuseppe Corda
  • Patent number: 4981807
    Abstract: A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of the vertical NPN transistor. The collector region of the vertical PNP transistor merges with the base region of the vertical NPN transistor. The emitter of the vertical PNP transistor is at the top, and the emitter of the vertical NPN transistor is at the bottom in relation to the emitter of the vertical PNP transistor. This structure leads to improvements in memory density, performance and wireability of a memory array comprising many such cells. A novel yet simple process for making such compact CTS memory cells is also disclosed.
    Type: Grant
    Filed: October 31, 1988
    Date of Patent: January 1, 1991
    Assignee: International Business Machines Corporation
    Inventor: Chakrapani G. Jambotkar
  • Patent number: 4892841
    Abstract: A semiconductor memory device is formed of a polycrystalline silicon electrode terminal layer, which is formed on a MOS transistor except over the gate region and is connected to the drain region of the MOS transistor, and metal wire layer, which is formed on the MOS transistor except over the gate region and is connected to the electrode terminal layer to transmit output signals. Data is written into the semiconductor memory device by ion implantation of the gate of the MOS transistor after the metal wire layer is formed.
    Type: Grant
    Filed: October 11, 1988
    Date of Patent: January 9, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Iwase, Shoji Ariizumi, Fujio Masuoka
  • Patent number: 4694561
    Abstract: A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.
    Type: Grant
    Filed: November 30, 1984
    Date of Patent: September 22, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Joseph Lebowitz, William T. Lynch
  • Patent number: 4612212
    Abstract: An erase gate is formed for erasing data from a floating gate in a semiconductor memory device having the floating gate and a control gate.Furthermore, in order to achieve electrical insulation between the erase gate and the control gate, an insulating film formed between the erase gate and the control gate is made thicker than an insulating film formed between the floating gate and the erase gate.
    Type: Grant
    Filed: April 9, 1985
    Date of Patent: September 16, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Fujio Masuoka, Hisakazu Iizuka