Abstract: A method for the fabrication of semiconductor devices, particularly bipolar silicon devices, having ultra-shallow but relatively large junctions. The process is characterized by the use of relatively low temperatures for critical oxidations steps and for ion-implantation steps. The region implantations are performed at low temperature and the necessary annealing steps are deferred until all of the regions are in place. Then a single pulse-annealing step is employed, to minimize further movement of the region junctions. Processing-induced defects are thereby reduced to a minimum, and the process can be used to produce ultra-shallow junctions in a reliable and repeatable manner.

Abstract: A method of producing a bipolar transistor which includes forming a base region, forming a high-melting-point metal layer of a base electrode on the base region, forming a first insulating layer on the metal layer, and selectively etching the first insulating layer and the metal layer to form an opening. The method further includes forming a second insulating layer on the sides of the first insulating layer and the metal layer within the opening, the second insulating layer defining an emitter-providing region. Impurities are introduced into the base region by using the second insulating layer as a mask to form an emitter region. An emitter electrode and the base electrode are arranged in a similar multilayer structure.

Abstract: A process for making high performance NPN bipolar transistors functioning in a current switch logic circuit. A bipolar transistor is formed within an isolated region of a monocrystalline silicon body. The transistor includes an N+ subcollector, and N+ collector reach-through which connects the subcollector to a major surface of the silicon body, a P base region above the subcollector and adjacent to the reach-through an N+ emitter region within the base region and extending from the major surface. The base region includes an intrinsic base region located below the emitter region and an extrinsic region extending from the major surface and adjacent to the emitter region. The extrinsic base completely surrounds the emitter region. A mask is formed above the major surface having openings only above major portions of the extrinsic base regions.

Abstract: A means and method is described for forming closely spaced contacts to adjacent semiconductor regions, such as the base and emitter of a bipolar transistor, so that the lateral voltage drops between the contacts and an intervening junction are minimized. The emitter and base and the contacts thereto are self-aligned. This is accomplished by a structure utilizing two poly-layers separated by one or more intermediate dielectric layers. The upper of the two poly-layers serves as a selective etching mask for defining the contact geometry and separation. The lower of the two poly-layers has one portion which becomes a poly-contact and diffusion source for the base region and a second portion which becomes a poly-contact and diffusion source for the emitter region. A single mask is used in connection with ion bombardment to alter the etch rate of portions of the poly-layers. This mask together with subsequent etch steps, defines the emitter width and location and the base-emitter contact separation.

Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: A method of manufacturing a semiconductor device is set forth to provide a high-frequency bipolar transistor with very fine emitter-base geometry. The method comprises the steps of forming a base region, forming an insulating layer on the base region, and implanting emitter zones and base contact zones in windows in the insulating layer. Only emitter windows are first formed, then the emitter zones are implanted and a masking layer is provided on the insulating layer and in the emitter windows so that the base contact windows can be etched through apertures in the masking layer. The base contact zones are then implanted to the base contact windows.

Abstract: A method for manufacturing a semiconductor device which comprises the steps of forming a first groove in that portion of a semiconductor substrate where an isolation is to be formed; selectively forming a second groove narrower than the first groove in that surface region of the semiconductor substrate which is surrounded by said first groove; depositing a masking material over the whole surface of the semiconductor substrate with a thickness less than half the width of the first groove and greater than half the width of the second groove; aniotropically etching the deposited masking material to eliminate substantially its thickness, thus leaving the masking material on the side walls of the first groove and entirely in the second groove; introducing an impurity into the bottom of the first groove to form an impurity region; filling the first groove with an isolating material; and forming a semiconductor element in that section of the semiconductor substrate which is surrounded by an isolation consisting of t

Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region.