Metal-organic Cvd (ruehrwein Type) Patents (Class 148/DIG110)
  • Patent number: 5789273
    Abstract: After a compound semiconductor layer including InP is formed on a semiconductor substrate, a compound semiconductor layer including As is epitaxially grown by metal organic chemical vapor deposition method using an organic As as the material for feeding the As.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: August 4, 1998
    Assignee: Sony Corporation
    Inventor: Tadashi Yamamoto
  • Patent number: 5369044
    Abstract: A method for producing a field effect transistor including a layer in which a two-dimensional electron gas is formed includes forming source and drain electrodes spaced from each other on a substrate structure including the layer in which a two-dimensional electron gas is formed. First and second resist films are sequentially applied to the structure and a stripe-shaped first opening is formed in the second resist film between the source and drain electrodes and extending in a longitudinal direction, perpendicular to a line connecting the source and drain electrodes. A plurality of second openings narrower than the first opening are formed within the first resist film in the first opening. The second openings are arranged at intervals along the longitudinal direction of the first opening. The second openings may be used as an etching mask to form recesses in the substrate structure not reaching the layer in which the two-dimensional electron gas is formed.
    Type: Grant
    Filed: July 20, 1993
    Date of Patent: November 29, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Teruyuki Shimura
  • Patent number: 5298445
    Abstract: In a method for fabricating a FET of the present invention, first and second side walls are formed on a side surface of a gate electrode, and two n-GaAs layers are formed on an active layer by selective growth using the side walls as a mask. After that, the side walls are removed, whereby double recesses are formed around the gate electrode.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: March 29, 1994
    Assignee: NEC Corporation
    Inventor: Kazunori Asano
  • Patent number: 5288657
    Abstract: Expedient fabrication of fine-featured integrated circuits entails aperture pattern delineation to produce a masking layer atop a semiconductor body followed by insertion within a controlled atmosphere chamber within which device-functional layered material is epitaxially grown within apertures. Critical, device-consequential properties of epitaxial material is assured by removal of a thin surface layer of material revealed during delineation. Such removal, sufficient to eliminate meaningful contamination and/or crystalline damage introduced during delineation, is of sufficiently small quantity as to be accommodated within the chamber. Under most circumstances, the controlled atmosphere is at reduced pressure as required for e.g. MOMBE epitaxial growth.
    Type: Grant
    Filed: November 1, 1990
    Date of Patent: February 22, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Anatoly Feygenson, Henryk Temkin, Yuh-Lin Wang
  • Patent number: 5284791
    Abstract: In a method of making a tunable twin guide (TTG) type tunable semiconductor laser, over the surface of a semiconductor substrate of one conductivity type, an active layer, a central layer of the opposite conductivity type, and a tuning layer, each being stripe-shaped and overlying the top of the preceding one is provided. This method is characterized in that the processing of semiconductor elements for defining the current path/optical waveguide inside the laser is carried out not by etching but by using selective epitaxy method such as metal organic vapor phase epitaxy (MOVPE). The use of selective MOVPE permits to form stripe-shaped layers at high precision and good uniformity, with consequent effects of minimizing scattering of laser light, increasing the efficiency of the drive power to laser light output conversion and enhancing the coupling efficiency with optical fibers. Besides thinner central layer that can be formed can contributes to enlarging the tunable bandwidth of laser light.
    Type: Grant
    Filed: August 6, 1992
    Date of Patent: February 8, 1994
    Assignee: NEC Corporation
    Inventors: Yasutaka Sakata, Masayuki Yamaguchi, Tatsuya Sasaki
  • Patent number: 5275966
    Abstract: Tri-isopropylantimony is used as a source of antimony in chemical vapor deposition production of semiconductor materials. The process can be used to introduce antimony as a dopant into III/V and II/VI semiconductor materials.
    Type: Grant
    Filed: July 8, 1991
    Date of Patent: January 4, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Robert W. Gedridge, Jr.
  • Patent number: 5264389
    Abstract: A semiconductor laser device of an AlGaInP system includes a GaAs substrate and a surface of the substrate is inclined by 5.degree. or more from a {100} plane in a <011> direction.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: November 23, 1993
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroki Hamada, Shoji Honda, Masayuki Shono, Takao Yamaguchi
  • Patent number: 5256595
    Abstract: An organometallic precursor as for example trimethyl indium (TMI) is co-injected with HCl into a hot wall reactor to form volatile InCl, and PH.sub.3 is used as the phosphorus source. Layers of InP are grown at approximately 8 .mu.m/hr with excellent morphology and good electrical properties. Hall measurements at 77K show background n-type conductivity with n=7.times.10.sup.15 /cm.sup.3 and .mu..sup.S 34,000 cm.sub.2 /V-s. The method is capable of growing ternary and quaternary heterostructures with thin layers and abrupt junctions.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: October 26, 1993
    Assignee: The United States of America as represented by the Secretary of the Army.
    Inventors: Joseph R. Flemish, Kenneth A. Jones, Vladimir S. Ban
  • Patent number: 5244829
    Abstract: The use of trimethylarsine in place of tertiary butyl arsine for low pressure organometallic vapor phase epitaxy of GaAs:C to enhance the carbon doping efficiency of CCl.sub.4. The hole concentration is three times higher with trimethylarsine then with tertiary butyl arsine in the layer grown under similar conditions. As a result, higher growth temperatures can be used with trimethyl arsine, yielding more stable carbon doping. Annealing at 650.degree. C. for 5 minutes does not degrade the trimethyl arsine-grown layers while the tertiary butyl arsine-grown layer shows decreases in both hole concentration and mobility. Also a high level of hydrogen atoms is detected in tertiary butyl arsine-grown GaAs:C. The hydrogen level is about 30 times lower in the layers grown with trimethyl arsine. The reduced hydrogen concentration is an added advantage of using trimethyl arsine since hydrogen is known to neutralize acceptors in GaAs to reduce the carrier concentrations.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: September 14, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Tae S. Kim
  • Patent number: 5232873
    Abstract: A semiconductor device substrate has a major surface on which is located an insulating layer, such as silicon dioxide, having an aperture penetrating through it all the way down to the major surface. An impurity-doped plug, such as tungsten doped with zinc, is spatially selectively deposited in the aperture to a thickness such that the height of the plug is significantly less than the height of the aperture in the insulating layer, by means of a rapid-thermal-cycle low-pressure-metalorganic-chemical vapor deposition (RTC-LP-MOCVD) process. Then another plug, of (pure) conductive barrier metal such as tungsten, is deposited on at least the entire top surface of the impurity-doped plug and on the sidewalls of the insulating layer. The structure being fabricated can then be heated, in order to diffuse the impurity into the underlying semiconductor device substrate.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: August 3, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Michael Geva, Avishay Katz
  • Patent number: 5202283
    Abstract: Method for organic free radical, including aliphatic radical, transport of dopant species for precise, predetermined, and reproducible doping concentrations to control electrical properties for chemical vapor deposition grown materials.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: April 13, 1993
    Assignee: Rockwell International Corporation
    Inventors: Charles R. Younger, Kenneth L. Hess, Stuart J. C. Irvine, Edward R. Gertner, Shawn L. Johnston
  • Patent number: 5173445
    Abstract: A P-type compound semiconductor layer doped with carbon is formed on a semi-insulating substrate by placing the substrate in a reactor, and carrying out vapor-phase epitaxy by feeding and thermally decomposing vapors of an organic metal compound including a methyl radical, arsine, and an alkyl compound of arsenic substantially simultaneously into the reactor so that a C-doped P-type compound semiconductor is deposited on the substrate.
    Type: Grant
    Filed: March 20, 1991
    Date of Patent: December 22, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Ando, Tetsuya Yagi
  • Patent number: 5171704
    Abstract: High carrier concentration, as well as abrupt change in such concentration in GaAs-based devices, is the consequence of selection of tin dopant-containing precursor compounds as used during layer growth. Alkyl tin compounds, as used during MetalOrganic Molecular Beam Epitaxy, are of particular value in the growth of pnp heterojunction bipolar transistors, likely in conjunction with other devices in large scale integrated circuits.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: December 15, 1992
    Assignee: AT&T Bell Laboratories
    Inventors: Cammy R. Abernathy, Fan Ren
  • Patent number: 5168077
    Abstract: A p-type GaAs or AlGaAs thin film is formed by a MOCVD method. In the growing step of the thin film, the thin film is doped with a high concentration of carbon atoms forming an acceptor level such that the carrier concentration of the thin film falls within the range of between 1.times.10.sup.18 cm.sup.-3 and 1.times.10.sup.20 cm.sup.-3. At least one of trimethyl gallium and trimethyl aluminum is used as a raw material gaseous compound of III-group element, and arsine is used as a raw material gaseous compound of V-group element. The thin film is formed by an epitaxial growth under the molar ratio V/III of the V-group element supply rate to the III-group element supply rate, which is set at such a small value as 0.3 to 2.5, the temperature of 450 to 700.degree. and the pressure of 1 to 400 Torr. The thin film formed under these conditions exhibits a mirror-like smooth surface, and the film-growth rate is dependent on the supply rate of the V-group element.
    Type: Grant
    Filed: March 29, 1990
    Date of Patent: December 1, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ashizawa, Takao Noda, Mitsuhiro Kushibe, Masahisa Funemizu, Kazuhiro Eguchi, Yasuo Ohba, Yoshihiro Kokubun
  • Patent number: 5141569
    Abstract: `Unintentionally` doped P type GaAs is grown on silicon by a metal organic chemical vapor deposition process in which the molecular ratio of arsenic to gallium in the growth ambient is reduced to a value that is sufficiently low to cause the creation of donor (As) site vacancies in the grown GaAs layer, which become occupied by acceptor (carbon) atoms in the metal organic compound, thereby resulting in the formation of a buffer GaAs layer having a P type majority carrier characteristic. Preferably, the silicon substrate has its growth surface inclined from the [100] plane toward the [011] direction is initially subjected to an MOCVD process (e.g. trimethyl gallium, arsine chemical vapor deposition) at a reduced temperature (e.g. 425.degree. C.) and at atmospheric pressure, to form a thin (400 Angstroms) nucleation layer. During this growth step the Group V/Group III mole ratio (of arsenic to gallium) is maintained at an intermediate value. The temperature is then ramped to 630.degree. C.
    Type: Grant
    Filed: April 4, 1990
    Date of Patent: August 25, 1992
    Assignee: Ford Microelectronics
    Inventors: Chris R. Ito, David McIntyre, Robert Kaliski, Milton Feng
  • Patent number: 5128275
    Abstract: A method for fabricating a compound semiconductor device having a semi-insulating layer of a group III-V compound semiconductor material that contains arsenic as a group V element. The method includes a step of growing the semi-insulating layer from a source gas of the group V element that contains both arsine and an organic compound of arsenic, wherein arsine and the organic compound of arsenic are used simultaneously with a mixing ratio to achieve a desired high resistivity in the semi-insulating layer.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: July 7, 1992
    Assignee: Fujitsu Limited
    Inventors: Masahiko Takikawa, Tadao Okabe, Toshihide Kikkawa
  • Patent number: 5064778
    Abstract: A vapor-phase epitaxial growth method for producing a Groups III-V compound semiconductor containing arsenic by vapor-phase epitaxial growth using arsenic trihydride as an arsenic source is disclosed, wherein said arsenic trihydride has a volatile impurity concentration of not more than 1.5 molppb on a germanium tetrahydride conversion. The resulting epitaxial crystal has a low residual carrier concentration and is applicable to a field effect transistor.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: November 12, 1991
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Takayoshi Maeda, Masahiko Hata, Noboru Fukuhara, Tadeshi Watanabe
  • Patent number: 5045496
    Abstract: A process is described for growing at least one layer doped with a transition element of cobalt on a substrate by introducing a source of indium, such as tri ethyl indium, (C.sub.2 H.sub.5).sub.3 In or, a source of a group V element, a source of the transition element, such as cobalt nitrosyl tricarbonyl CO(NO)(CO).sub.3, and a source of phosphorus, to the substrate heated in an inert or reducing atmosphere at a pressure substantially between 1/100 atmosphere and one atmosphere to grow at least one semi-insulating semiconductor layer on the substrate.
    Type: Grant
    Filed: May 13, 1988
    Date of Patent: September 3, 1991
    Assignee: Rockwell International Corporation
    Inventors: Kenneth L. Hess, Stanley W. Zehr
  • Patent number: 5036022
    Abstract: This invention is directed to a method of epitaxial growth by metal organic vapor phase epitaxy (MOVPE) of Group III-V compound semiconductors in a hot wall reactor. Epitaxy is accomplished by use of precursors having a metal, an organic ligand, and an inorganic ligand. The system is operated at very low pressures to provide a high throughput of wafers and a highly uniform deposition growth. The invention is further directed to the use of the class of precursors to selectively grow III-V compounds on a masked substrate, wherein growth occurs epitaxially on the exposed areas of the substrate but not on the surrounding mask.
    Type: Grant
    Filed: November 1, 1990
    Date of Patent: July 30, 1991
    Assignee: International Business Machines Corporation
    Inventors: Thomas F. Kuech, Michael A. Tischler
  • Patent number: 5026661
    Abstract: A method of growing zinc chalcogenide in an atmosphere which contains the vapor of di-.pi.-cyclopentadienyl manganese or di-.pi.-alkyl cyclopentadienyl manganese that serves as a source of manganese. By growing zinc chalcogenide in the above atmosphere, there is obtained a manganese-doped zinc chalcogenide having a very high crystal quality, which is very suitable for the active layer in light emitting devices.
    Type: Grant
    Filed: October 13, 1989
    Date of Patent: June 25, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Migita, Osamu Kanehisa, Masatoshi Shiiki, Hajime Yamamoto
  • Patent number: 4994408
    Abstract: A method for growing high quality epitaxial films using low pressure MOCVD that includes providing a substrate that is misoriented from a singular plane, placing the substrate into an MOCVD reactor at a total pressure of less than 0.2 atmospheres and then growing an epitaxial film on the substrate. When providing a misoriented gallium arsenide substrate, the MOCVD reactor is set at a temperature in the range of 650 to 750 degrees centigrade to grow an aluminum gallium arsenide film. This temperature is substantially lower than that at which aluminum gallium arsenide epitaxial films are commonly grown and the resulting film has a smooth surface morphology and enhanced photoluminesence properties.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: February 19, 1991
    Assignee: Motorola Inc.
    Inventor: Eric S. Johnson
  • Patent number: 4965222
    Abstract: A method of manufacturing an epitaxial InP layer on a substrate surface by means of a MOVPE process at atmospheric pressure, cyclopentadienyl indium (I) or alkyl cyclopentadienyl indium (I) being used as the indium precursor, thereby precluding side reactions.
    Type: Grant
    Filed: October 2, 1989
    Date of Patent: October 23, 1990
    Assignee: U.S. Philips Corporation
    Inventor: Aemilianus G. J. Staring
  • Patent number: 4948753
    Abstract: A semiconductor laser and a method of producing the same wherein the semiconductor laser is produced by forming a stripe-shaped projection on the surface of a semiconductor substrate, and forming multilayered thin films with a double heterostructure including an active layer on said semiconductor substrate by using the metal organic chemical vapor phase epitaxial growth method or the molecular beam epitaxial growth method. Thus, a buried stripe-structure semiconductor laser can be produced by a sequence of crystal growth processes.
    Type: Grant
    Filed: October 29, 1987
    Date of Patent: August 14, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Yoshikawa, Takashi Sugino
  • Patent number: 4946802
    Abstract: A high-power AlGaAs/GaAs laser device comprises: a ridge formed on the top surface of a substrate from one end to the opposite end, thereof wherein the width of the ridge is made narrower in regions near both the ends and wider in a middle region; a depression is formed in the wider region of the ridge; a clad layer is grown epitaxially over the top surface of the substrate; and an active layer is grown epitaxially on the clad layer, wherein the thickness of the active layer is thinner in portions just above the narrower ridge regions and relatively thicker in a portion just above the wider ridge region.
    Type: Grant
    Filed: November 18, 1988
    Date of Patent: August 7, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akihiro Shima, Wataru Susaki
  • Patent number: 4935381
    Abstract: Disclosed is a novel method to use arsine plus an alkylarsenic co-reagent to grow GaAs by OMCVD that not only allows one to take advantage of the lower toxicity and ease of decomposition of the alkylarsenic compounds, but also reduces the carbon contamination normally found in epilayers grown exclusively from these alkylarsines, and decreases the amount of arsine needed for growth of reasonably good quality GaAs epilayers.
    Type: Grant
    Filed: December 9, 1988
    Date of Patent: June 19, 1990
    Assignee: The Aerospace Corporation
    Inventors: Donna M. Speckman, Jerry P. Wendt
  • Patent number: 4933299
    Abstract: MOVPE growth and photoetching are integrated into a unified sequence which is carried out without removing a workpiece from a MOVPE reactor. Growth may be carried out before, after or before and after the etching.To prevent pattern broadening by diffussion of the active species the substrate is preferably protected by a fugitive coating which is removed by the illumination. Native oxide coatings are particularly suitable for InGaAsP substrates. These are conveniently applied for exposing to substrate to 20.degree./o O.sub.2 +80.degree./oN.sub.2 for about 3 minutes at 450.degree. C.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: June 12, 1990
    Assignee: British Telecommunications public limited company
    Inventor: Kenneth Durose
  • Patent number: 4920068
    Abstract: A process to produce one or more Group II-VI epitazial layers over a crystalline substrate by directing flows of one or more Group II components and a Group VI metalorganic vapor to a heated substrate whereby the vapors thereby react to form the epitaxial layer(s), is improved in terms of lower reaction temperatures and higher product quality if, as the Group VI metalorganic vapor source, there is used a tellurium compound of the formula: ##STR1## wherein R.sup.1 and R.sup.2 are, independently, hydrogen or C.sub.1 -C.sub.4 alkyl, preferably, hydrogen.
    Type: Grant
    Filed: April 2, 1986
    Date of Patent: April 24, 1990
    Assignee: American Cyanamid Company
    Inventors: Donald Valentine, Jr., Duncan W. Brown
  • Patent number: 4916089
    Abstract: In order, in the epitaxial production of semiconductor products and of articles provided with a layer, to be able to make the junction between the layers applied to the substrates atomically sharp, it is important to be able to change the gas mixture, to be introduced into a pulsed reactor or MBE reactor, rapidly, accurately and without losses in respect of quantity and of composition. To this purpose, each of the gases to be introduced into the reactor is conveyed to a separate gas pipette and thereafter the content of the gas pipette is cyclically passed, by means of a pressure differential, into the pulse reactor, with the composition of the mixture being changed per one or more cycles.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: April 10, 1990
    Assignee: Stichting Katholieke Universiteit
    Inventors: Jaap Van Suchtelen, Lodevicus J. Giling, Josephus E. M. Hogenkamp
  • Patent number: 4910167
    Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: March 20, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough, Jack P. Salerno
  • Patent number: 4904616
    Abstract: The present invention addresses the use of at least partially fluorinated organometallic compounds in reactive deposition applications. More specifically, the present invention addresses the use of the fluoroorganometallic compounds M(CF.sub.3).sub.3, M(CF.sub.2 CF.sub.3).sub.3, or any M(C.sub.n F.sub.(2n+1)).sub.3-y H.sub.y compound where (y.ltoreq.2), M(CH.sub.2 CF.sub.3).sub.3 or any fluoroalkyl organometallics of the general formula M(C.sub.n H.sub.[(2n+1)-x] F.sub.x).sub.3-y H.sub.y, where y.ltoreq.2; x has a value 1.ltoreq.x.ltoreq.2n+1; and M=As, P, or Sb, in processes requiring deposition of the corresponding element. These uses include a number of different processes; the organometallic vapor phase epitaxy of compound semiconductor materials such as GaAs, InP, AlGaAs, InSb, etc.; doping of SiO.sub.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: February 27, 1990
    Assignee: Air Products and Chemicals, Inc.
    Inventors: David A. Bohling, Gregory T. Muhr, David A. Roberts
  • Patent number: 4902356
    Abstract: An epitaxial layer having a double-hetero structure is forming using an MOCVD process or an MBE process, and an epitaxial substrate is formed using an LPE process, thereby forming a substrate which exploits the distinguishing features of both processes. Since the MOCVD process or MBE process exhibits mixed-crystal ratio and film thickness controllability, excellent reproducibility and uniformity are obtained when forming the double-hetero structure on a compound semiconductor substrate. Since the growth process takes place under thermal non-equilibrium, the amount of impurity doping is raised to more than 10.sup.19 cm.sup.3. This is advantageous in terms of forming an electrode contact layer. With the LPE process, the material dissolved in the melt is grown epitaxially on the substrate by slow cooling, and the rate of growth is high. This process is suitable for forming the substrate after removal of the compound semiconductor substrate.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: February 20, 1990
    Assignees: Mitsubishi Monsanto Chemical Company, Mitsubishi Kasei Corporation
    Inventors: Masahiro Noguchi, Hideki Gotoh, Kenji Shimoyama
  • Patent number: 4859627
    Abstract: A method of producing n-type III-V compound semiconductor comprises growing a plurality of monolayers of III-V compound semiconductor molecules on a III-V compound substrate; growing a single layer of group VI element on the III-V monolayers so as to occupy the lattice points for group V element by means of Atomic Layer Epitaxy process; decreasing the number of group VI element by exposing the single layer to the gas of group V element; and growing a plurality of monolayers of III-V compound semiconductor molecules on the group VI element-doped layer by means of the Atomic Layer Epitaxy process.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: August 22, 1989
    Assignee: NEC Corporation
    Inventor: Haruo Sunakawa
  • Patent number: 4859625
    Abstract: A method for epitaxial growth of compound semiconductor containing three component elements, two component elements thereof being the same group elements, in which three kinds of compound gases each containing different one of the three component elements are cyclically introudced, under a predetermined pressure for a predetermined period respectively, onto a substrate enclosed in an evacuated crystal growth vessel so that a single crystal thin film of the compound semiconductor is formed on the substrate.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: August 22, 1989
    Assignee: Research Development Corporation of Japan, Junichi Nishizawa and Oki Electric Industry Co., Ltd.
    Inventor: Fumio Matsumoto
  • Patent number: 4855250
    Abstract: A method of manufacturing a semiconductor light emitting device by forming a compound semiconductor structure with homo- or heterojunction therein having a first p-type compound semiconductor crystal layer at the top of the structure, growing a second p-type compound semiconductor crystal layer on the structure in a reactor, wherein, before the beginning of the crystal growth step, a p-type dopant is caused to flow into the reactor in which the structure is placed. In some embodiments, the flow of the p-type dopant continues after the completion of the crystal growth.
    Type: Grant
    Filed: December 28, 1987
    Date of Patent: August 8, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motoyuki Yamamoto, Yasuhiko Tsuburai
  • Patent number: 4855249
    Abstract: In organometallic vapor phase hetero-epitaxial processes for growing Al.sub.x Ga.sub.1-x N films on a sapphire substrate, the substrate is subjected to a preheat treatment of brief duration, such as less than 2 minutes, at relatively low temperatures in an atmosphere comprising Al-containing organometallic compound, NH.sub.3 and H.sub.2 gases, prior to the hetero epitaxial growth of Al.sub.x Ga.sub.1-x N films. Thus, single crystalline Al.sub.x Ga.sub.1-x N layers of high uniformity and high quality having smooth, flat surfaces are provided. Multi-layers grown according to the process of the invention are free from cracks and have preferable UV or blue light emission properties.
    Type: Grant
    Filed: March 16, 1988
    Date of Patent: August 8, 1989
    Assignee: Nagoya University
    Inventors: Isamu Akasaki, Nobuhiko Sawaki
  • Patent number: 4835116
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 30, 1989
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Patent number: 4830982
    Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by a MOCVD process through the use of organic titanium-based compounds. Resistivities greater than 1.times.10.sup.7 ohm/cm have been achieved.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: May 16, 1989
    Assignees: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Andrew G. Dentai, Charles H. Joyner, Jr., Timothy W. Weidman, John L. Zilko
  • Patent number: 4829021
    Abstract: An injection block having a plurality of geometrically arranged injection sources for gaseous Group III metal organic compounds is oriented substantially perpendicular to the placement of at least one semiconductor wafer substrate within a vacuum reaction chamber. The injector sources are sized to provide disbursing flow of the compounds capable of depositing a layer of about 5% uniform thickness or less over substantially the entire semiconductor wafer. An injection source of Group V compounds is located centrally within the geometrically arranged injection sources for the Group III compounds. The Group V injection source is sized to supply an excess of the Group V compounds required to react with the Group III compounds in order to form Group III-V semiconductor layers on the substrate and partition the Group III sources into groups having substantially equal numbers of injection sources. An excess of Group V comounds is injected.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: May 9, 1989
    Assignee: Daido Sanso K.K.
    Inventors: Lewis M. Fraas, Paul S. McLeod, John A. Cape
  • Patent number: 4829020
    Abstract: During the growth of compound semiconductors by epitaxial processes, substrates are typically mounted to a support. In modular beam epitaxy, mounting is done using indium as a solder. This method has two drawbacks: the indium reacts with the substrate, and it is difficult to uniformly wet the back of a large diameter substrate. Both of these problems have been successfully overcome by sputter coating the back of the substrate with a thin layer of tungsten carbide or tungsten carbide and gold. In addition to being compatible with the growth of high quality semiconductor epilayers this coating is also inert in all standard substrate cleaning etchants used for compound semiconductors, and provides uniform distribution of energy in radiant heating.
    Type: Grant
    Filed: October 23, 1987
    Date of Patent: May 9, 1989
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Timothy J. Drummond, David S. Ginley, Thomas E. Zipperian
  • Patent number: 4826784
    Abstract: A method of OMCVD heteroepitaxy of III/V (GaAs) material on a patterned Si substrate is described wherein heteroepitaxy deposition occurs only on the exposed Si surfaces and nowhere else.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 2, 1989
    Assignee: Kopin Corporation
    Inventors: Jack P. Salerno, Jhang W. Lee, Richard E. McCullough
  • Patent number: 4824798
    Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 25, 1989
    Assignee: Xerox Corporation
    Inventors: Robert D. Burnham, Robert L. Thornton
  • Patent number: 4804638
    Abstract: A method for growing a Group II-IV epitaxial layer over a substrate is described. The method includes the steps of directing a plurality of vapor flows towards the substrate, including a Group II organic vapor, a Group VI organic vapor, and a Group II elemental mercury vapor. At least one of the Group II organic vapor and Group VI organic vapor has organic groups which sterically repulse the second one of the Group II and Group VI organic vapors or which provide electron transfer to the Group II atom or electron withdrawal from the Group VI atom. With the particular arrangements described, it is believed that substantially independent pyrolsis of the Group II organic vapor is provided over the growth region of the substrate, and accordingly, Group II depletions such as cadmium depletion in the epitaxial films provided over the substrate is substantially reduced.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: February 14, 1989
    Assignee: Raytheon Company
    Inventors: William E. Hoke, Lindley T. Specht
  • Patent number: 4793872
    Abstract: A component of semiconductor material deposited by epitaxial growth on a substrate having a predetermined and different lattice parameter consists of an alternate succession of layers of a first type and layers of a second type deposited on the substrate. The lattice parameter of the first type of layers is substantially matched with the lattice parameter of the substrate. In the case of the second type of layers, the lattice parameter is matched and even equal to that of the first type of layers. A component having a lattice parameter equal to that of the second type of layers is formed on the last layer of the second type. Moreover, the energy gaps of the two types of layers are different.
    Type: Grant
    Filed: March 4, 1987
    Date of Patent: December 27, 1988
    Assignee: Thomson-CSF
    Inventors: Paul L. Meunier, Manijeh Razeghi
  • Patent number: 4782034
    Abstract: Semi-insulating epitaxial layers of Group III-V based semiconductor compounds are produced by an MOCVD process through the use of bis arene titanium sources, such as cyclopentadienyl cycloheptatrienyl titanium and bis (benzene) titanium.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: November 1, 1988
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Andrew G. Dentai, Charles H. Joyner, Jr., Timothy W. Weidman, John L. Zilko
  • Patent number: 4748135
    Abstract: A method of manufacturing a semiconductor device including the step of depositing from the vapor layers on a substrate in the chamber of a reactor in which a vector gas and a reactant gas are introduced, characterized in that the vector gas and the reactant gas are introduced into the chamber of the reactor by means of a system of three coaxial tubes, the first of which (the inner tube) has a diameter smaller than that of the second tube (the intermediate tube), which in turn has a diameter smaller than that of the third tube (the outer tube), the first ends of these tube being independent, but the second ends thereof situated in the proximity of each other cooperating with each other so as to form a valve controlling the introduction of the reactant gas into the hot zone of the chamber of the reactor mixed with a vector gas, these tubes being disposed in such a manner that: the said second end of the inner tube merges into the intermediate tube, the said second end of the intermediate tube provided with a re
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: May 31, 1988
    Assignee: U.S. Philips Corp.
    Inventor: Peter M. Frijlink
  • Patent number: 4701998
    Abstract: A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 .ANG..+-.10%, e.g., 180 .ANG., is then formed on the thus exposed undamaged single crystal silicon.
    Type: Grant
    Filed: December 2, 1985
    Date of Patent: October 27, 1987
    Assignee: International Business Machines Corporation
    Inventors: David C. Ahlgren, Robert E. Bendernagel, Russell C. Lange, Martin Revitz
  • Patent number: 4636268
    Abstract: Epitaxial layers of semiconductor materials such as, e.g., III-V and II-VI materials are deposited on a substrate under high-vacuum conditions. Molecules of a compound of a constituent of such material travel essentially line-of-sight towards the substrate admixed to a carrier gas such as, e.g., hydrogen. For III-V layers the use of compounds, such as, e.g., trimethyl- and triethylgallium, trimethyl- and triethylindium, triethylphosphine, and trimethylarsine is advantageous and economical in the manufacture of electronic and opto-electronic devices.
    Type: Grant
    Filed: November 30, 1984
    Date of Patent: January 13, 1987
    Assignee: AT&T Bell Laboratories
    Inventor: Won-Tien Tsang
  • Patent number: 4632711
    Abstract: A zinc selenide or zinc selenide-sulphide epitaxial crystal is grown at a growth temperature of about 180.degree.-320.degree. C. by organometallic chemical vapor deposition by using zinc alkyl and hydrogen selenide and/or hydrogen sulphide. An as-grown crystal presented an n conductivity type low resistivity and exhibited a narrow near-band gap emission peak. Besides a crystal of the same material as the epitaxial layer, crystals of group III-V, group IV, and so forth having the same or similar crystal structure as the epitaxial layer can be used as an underlayer for the growth.
    Type: Grant
    Filed: March 1, 1985
    Date of Patent: December 30, 1986
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Shigeo Fujita, Yoshinobu Matsuda, Akio Sasaki
  • Patent number: 4622083
    Abstract: A molecular beam epitaxial growth process, for growth of III-V compounds, wherein a substrate is heated approximately to growth temperature before the group III cell is fully heated. That is, for example, to grow gallium arsenide, the arsenic cell would be heated, the arsenic cell's shutter opened, and the substrate heated up to growth temperature (e.g. 600 C), before the gallium cell is heated up. After the gallium cell is heated up, its shutter is opened, and epitaxial growth proceeds.
    Type: Grant
    Filed: March 11, 1985
    Date of Patent: November 11, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Hung-Dah Shih
  • Patent number: 4611388
    Abstract: A heterojunction bipolar transistor having an n- type epitaxial indium phosphide collector layer grown on a semi-insulating indium phosphide substrate with an n+ buried layer, a p- type indium phosphide base and an epitaxial, n- type boron phosphide wide gap emitter. The p- type base region is formed by ion implantation of magnesium ions into the collector layer. The transistor is applicable to millimeter wave applications due to the high electron mobility in the indium phosphide base. The wide gaps of both the boron phosphide (2.2 eV) and indium phosphide (1.34 eV) permit operation up to 350.degree. C. The transistor is easily processed using metal organic-chemical vapor deposition (MO-CVD) and standard microelectronic techniques.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: September 16, 1986
    Assignee: Allied Corporation
    Inventor: Krishna P. Pande