Nitridation, Direct, Of Silicon Patents (Class 148/DIG112)
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Patent number: 5780364Abstract: A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.Type: GrantFiled: November 27, 1996Date of Patent: July 14, 1998Assignee: Micron Technology, Inc.Inventor: Randhir P. S. Thakur
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Patent number: 5650344Abstract: A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.Type: GrantFiled: July 17, 1995Date of Patent: July 22, 1997Assignee: Harris CorporationInventors: Akira Ito, John T. Gasner
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Patent number: 5518946Abstract: A method for inhibiting generation of a native oxide film on the surface of a dielectric film in the process of fabricating a capacitor for a dynamic RAM is disclosed. A pure polysilicon layer inherently not liable to produce a native oxide film is formed as a lower electrode layer, and a thin thermal nitride film is formed b rapid thermal nitridation on the surface of the pure polysilicon layer. Impurities are then introduced via this thermal nitride layer into the lower electrode layer by ion implantation for rendering the lower electrode layer electrically conductive. Alternatively, an impurity-containing polysilicon layer having a native oxide film on its surface is processed by rapid thermal nitridation for causing a thermal nitride film to be grown at an interface between the native oxide film and the polysilicon layer, after which the surface native oxide film is removed.Type: GrantFiled: February 28, 1994Date of Patent: May 21, 1996Assignee: Sony CorporationInventor: Hideaki Kuroda
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Patent number: 5492854Abstract: A method of manufacturing a semiconductor device includes the step of forming a capacitor. The step includes the step of forming a lower electrode constituted by a polysilicon film which selectively covers a surface of a predetermined insulating film on a semiconductor substrate, and the step of performing heating in an atmosphere containing an SiH.sub.4 gas and removal of a native oxide film on a surface of the lower electrode, and then performing formation of a silicon nitride film without being exposed to an oxygen atmosphere.Type: GrantFiled: December 14, 1994Date of Patent: February 20, 1996Assignee: NEC CorporationInventor: Koichi Ando
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Patent number: 5397720Abstract: High quality ultrathin gate oxides having nitrogen atoms therein with a profile having a peak at the silicon oxide-silicon interface are formed by oxidizing a surface of a monocrystalline silicon body in an atmosphere of nitrous oxide (N.sub.2 O) at a temperature above 900.degree. C. preferably in the range of 900.degree.-1100.degree. C., and then heating the silicon body and oxidized surface in an atmosphere of anhydrous ammonia to introduce additional nitrogen atoms into the oxide and increase resistance to boron penetration without degrading the oxide by charge trapping. The resulting oxynitride has less degradation under channel hot electron stress and approximately one order of magnitude longer lifetime than that of conventional silicon oxide in MIS applications.Type: GrantFiled: January 7, 1994Date of Patent: March 14, 1995Assignee: The Regents of the University of Texas SystemInventors: Dim-Lee Kwong, Giwan Yoon, Jonghan Kim
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Patent number: 5278087Abstract: A single transistor electrically programmable and erasable memory cell has a substrate of a semiconductor material of a first-conductivity type. Within the substrate are defined source, drain, regions with a channel region therebetween. A first insulating layer is disposed over the substrate and over the source, channel and drain regions. An electrically conductive, re-crystallized floating gate is disposed over the first-insulating layer and extends over a portion of the channel region and over a portion of the drain region to maximize capacitive coupling therewith. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connected sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer.Type: GrantFiled: October 15, 1992Date of Patent: January 11, 1994Assignee: Silicon Storage Technology, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5264396Abstract: A method and system for fabricating semiconductor wafers is disclosed, wherein a rugged and/or smooth, atomically clean, semiconductor substrate is provided in a rapid thermal processing ("RTP") chamber. The substrate can be single crystal, polycrystalline or amorphous silicon. In one embodiment of the present invention, the substrate is cleaned by exposing it to at least one of CF.sub.4, C.sub.2 F.sub.2, C.sub.2 F.sub.6, C.sub.4 F.sub.8, CHF.sub.3, HF, NF.sub.6, and NF.sub.3 diluted with Ar-H.sub.2 at a temperature substantially within the range of 650.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds in the chamber. Subsequently, the clean substrate is exposed to a first gas and energy generating a first temperature substantially within the range of 650.degree. C. to 1150.degree. C. in situ under substantially high vacuum for approximately 5 seconds to 20 seconds. Simultaneous to exposing the substrate to the first gas, a second gas comprising fluorine as an oxidizing agent, preferably NF.Type: GrantFiled: January 14, 1993Date of Patent: November 23, 1993Assignee: Micron Semiconductor, Inc.Inventors: Randhir P. S. Thakur, Richard C. Hawthorne, Annette L. Martin, Gurtej S. Sandhu
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Patent number: 5258333Abstract: A high-quality, highly reliable, composite dielectric layer for a semiconductor device. The composite dielectric layer is formed by nitriding a silicon surface, forming an oxide layer on the nitrided silicon surface, and then annealing the nitrided-silicon surface and the oxide in an oxygen ambient.Type: GrantFiled: August 18, 1992Date of Patent: November 2, 1993Assignee: Intel CorporationInventors: Joseph Shappir, Ido Rahat
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Patent number: 5256563Abstract: A method of forming doped wells 24 and 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer 18 is then formed on the oxide layer 16 and is patterned and etched to define a first well region 24. The first well region 24 is then doped, for example with phosphorus or boron. A resist layer 26 is formed over the first well region 24 and over a portion of the nitride layer 18 after which a portion of the nitride layer 18 not beneath the resist layer 26 is removed to expose a second well region 30. The second well region 30 is then doped. After the remaining portion the resist layer 26 is removed, an oxide layer 32 is formed over the first 24 and second 30 well regions while the surface 38 over the region 36 separating the well regions is left bare. The semiconductor wafer 10 is then heated in a nitridizing environment (e.g.Type: GrantFiled: April 16, 1992Date of Patent: October 26, 1993Assignee: Texas Instruments IncorporatedInventors: Mehrdad M. Moslehi, John W. Kuehne
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Patent number: 5254489Abstract: According to this invention, there is provided a method of manufacturing a semiconductor device. An element region and an element isolation region are formed on a semiconductor substrate of a first conductivity type. A first oxide film prospectively serving as a gate insulating film is formed in the element region. Thermal oxidization is performed after annealing is performed in nitrogen or ammonia atmosphere to nitrify an entire surface of the first oxide film. A predetermined region of a nitrified first oxide film is removed, and a second oxide film prospectively serving as a gate insulating film is formed in the predetermined region using the nitrified first oxide film as a mask. A gate electrode constituted by a polysilicon film is formed on each of the nitrified first oxide film and the second oxide film.Type: GrantFiled: October 18, 1991Date of Patent: October 19, 1993Assignee: NEC CorporationInventor: Hidetoshi Nakata
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Patent number: 5236862Abstract: Defect-free field oxide isolation (34) is formed by oxidizing through a silicon nitride layer (30) which overlies the isolation regions (22) of the silicon substrate (12). Additionally, the silicon nitride layer (30) acts as a diffusion barrier during field growth, and thus inhibits the lateral diffusion of oxygen underneath the oxidation mask (18). Therefore, field oxide encroachment into the adjacent active regions is effectively reduced. Moreover, field oxide encroachment is also reproducibly controlled, and therefore integrated circuits with high device packing densities can be fabricated.Type: GrantFiled: December 3, 1992Date of Patent: August 17, 1993Assignee: Motorola, Inc.Inventors: James R. Pfiester, Prashant Kenkare
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Patent number: 5198392Abstract: In a method of forming an insulating film, a silicon dioxide film is formed on a silicon substrate by performing heat treatment in an oxidizing gas atmosphere which does not contain nitrogen, and then the silicon dioxide film is oxynitrided by performing heat treatment in an nitrous oxide atmosphere. Prior to the formation of the silicon dioxide film, the silicon substrate is cleaned by heating it in a reducing gas atmosphere, and then heating it in a reactive gas atmosphere.Type: GrantFiled: June 21, 1991Date of Patent: March 30, 1993Assignee: Oki Electric Industry Co., Ltd.Inventors: Hisashi Fukuda, Tomiyuki Arajawa
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Patent number: 4980307Abstract: An insulative film, such as SiO.sub.2, Si.sub.3 N.sub.4 and PSG films, for example, is commonly used the passivation film or gate electrode of MISFETs. Stability of the insulative films during the production or operation of the semiconductor devices is enhanced by providing an insulative film which is formed by nitridation, for example, in an NH.sub.3 gas, of an SiO.sub.2 film, preferably a directly thermally oxidized film of silicon. The insulative film according to the present invention is used for a gate insulation film in MISFETs, a capacitor or passivation film for semiconductor devices, and as a mask for selectively forming circuit elements of semiconductor devices. The process for forming the insulative film may comprise successive nitridation, oxidation and nitridation steps.Type: GrantFiled: August 30, 1989Date of Patent: December 25, 1990Assignee: Fujitsu LimitedInventors: Takashi Ito, Takao Nozaki
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Patent number: 4784973Abstract: A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) control layer. Titanium is thereafter deposited and in another thermal reaction the control layer retards the development of titanium silicide without retarding the development of titanium nitride so that the thickness of titanium silicide is kept small. A double titanium process can also be used.Type: GrantFiled: August 24, 1987Date of Patent: November 15, 1988Assignee: INMOS CorporationInventors: E. Henry Stevens, Paul J. McClure, Christopher W. Hill
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Patent number: 4740483Abstract: A process for selective deposition of a refractory metal such as tungsten at high temperatures and low pressure via chemical vapor deposition during semiconductor device manufacturing is provided. A dielectric layer is nitrided by chemical deposition of a nitrogen bearing gas prior to LPCVD deposition of tungsten for purposes such as contact metallization of current conducting electrodes and current controlling electrodes of transistors. Since nitridation of the dielectric is a surface chemical reaction and not an addition of material to the dielectric, no additional complexity is introduced into the LPCVD process. The refractory metal does not substantially deposit on the nitrided dielectric thereby providing selective metal deposition.Type: GrantFiled: March 2, 1987Date of Patent: April 26, 1988Assignee: Motorola, Inc.Inventor: Philip J. Tobin
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Patent number: 4575921Abstract: A method of forming a silicon nitride coating in situ on a silicon surface by ion milling. The ion milling and silicon nitride formation process are uniquely integrated in semiconductor manufacturing methods to provide several benefits, including contact areas being substantially registered with and self-aligned with functional regions.Type: GrantFiled: October 1, 1984Date of Patent: March 18, 1986Assignee: General Motors CorporationInventor: Jayant K. Bhagat