Nitrides Of Boron Or Aluminum Or Gallium Patents (Class 148/DIG113)
  • Patent number: 6123768
    Abstract: This invention relates to a method of preparing highly insulating GaN single crystal films in a molecular beam epitaxial growth chamber. A single crystal substrate is provided with the appropriate lattice match for the desired crystal structure of GaN. A molecular beam source of Ga and source of activated atomic and ionic nitrogen are provided within the growth chamber. The desired film is deposited by exposing the substrate to Ga and nitrogen sources in a two step growth process using a low temperature nucleation step and a high temperature growth step. The low temperature process is carried out at 100-400.degree. C. and the high temperature process is carried out at 600-900.degree. C. The preferred source of activated nitrogen is an electron cyclotron resonance microwave plasma.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: September 26, 2000
    Assignee: The Trustees of Boston University
    Inventor: Theodore D. Moustakas
  • Patent number: 5863811
    Abstract: A method for growing a single crystal III-V compound semiconductor layer, in which grown by vapor deposition on a first single crystal III-V compound semiconductor layer including at least Ga and N is a second single crystal III-V compound semiconductor layer different from the first layer and including at least Ga and N, comprises the steps of: growing a buffer layer other than single crystal and having substantially the same composition as that of the second layer by vapor deposition on the first layer; and growing the second layer on the buffer layer. A method for growing a single crystal AlGaN layer on a single crystal GaN layer by vapor deposition, comprises the steps of: growing a buffer layer of a III-V compound semiconductor including at least Ga and N on the single crystal GaN layer by vapor deposition; and growing the single crystal AlGaN layer on the buffer layer by vapor deposition.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: January 26, 1999
    Assignee: Sony Corporation
    Inventors: Hiroji Kawai, Tsunenori Asatsuma, Kenji Funato
  • Patent number: 5846844
    Abstract: A nitrogen-group III compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0, and a method for producing the same comprising the steps of forming a zinc oxide (ZnO) intermediate layer on a sapphire substrate, forming a nitrogen-group III semiconductor layer satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0 on the intermediate ZnO layer, and separating the intermediate ZnO layer by wet etching with an etching liquid only for the ZnO layer.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: December 8, 1998
    Assignees: Toyoda Gosei Co., Ltd., Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu
    Inventors: Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu, Theeradetch Detchprohm
  • Patent number: 5834325
    Abstract: A light emitting device having higher blue luminance is obtained. A gallium nitride compound layer is formed on a GaAs substrate, and thereafter the GaAs substrate is at least partially removed for forming the light emitting device. Due to the removal of the GaAs substrate, the quantity of light absorption is reduced as compared with the case of leaving the overall GaAs substrate. Thus, a light emitting device having high blue luminance is obtained.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: November 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Mitsuru Shimazu, Yoshiki Miura
  • Patent number: 5834326
    Abstract: A process for producing a semiconductor emitting device of group III nitride semiconductor having a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) includes; a step of forming at least one pn-junction or pin-junction and a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) to which a group II element is added; and a step of forming electrodes on the crystal layer. The process further includes an electric-field-assisted annealing treatment in which the pn-junction or pin-junction is heated to the predetermined temperature range while forming and maintaining an electric field across the pn-junction or pin-junction for at least partial time period of the predetermined temperature range via the electrodes.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: November 10, 1998
    Assignee: Pioneer Electronic Corporation
    Inventors: Mamoru Miyachi, Toshiyuki Tanaka, Yoshinori Kimura, Hirokazu Takahashi, Hitoshi Sato, Atsushi Watanabe, Hiroyuki Ota, Isamu Akasaki, Hiroshi Amano
  • Patent number: 5650361
    Abstract: Thin films of aluminum nitride are deposited at 350 K on silicon, GaAs, fused quartz, and KBr substrates using gas-phase 193 nm excimer laser photolysis of trimethylamine alane and ammonia precursors without a thermally induced or a spontaneous reaction between them, resulting in AlN thin films that are amorphous, smooth and featureless having a band gap of 5.8 eV, a refractive index of 2.0, a breakdown electric field breakdown of 10.sup.8 V/m, a low-frequency dielectric constant of 6.0-6.9, high-frequency dielectric constant of 3.9-4.0, well suited for many thin film applications.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: July 22, 1997
    Assignee: The Aerospace Corporation
    Inventor: Gouri Radhakrishnan
  • Patent number: 5614447
    Abstract: A method for heat-treating a semiconductor body comprising steps of: (a) disposing a susceptor on one surface of the semiconductor body, and disposing a protection plate in such a manner that the other surface of the semiconductor faces to a surface the protection plate, (b) heat-treating the semiconductor body, wherein the susceptor and the protection plate comprises at least one member selected from the group consisting of gallium nitride, aluminum nitride and boron nitride, and at least one of the susceptor and the protection plate has an absorber of infrared ray.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: March 25, 1997
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Shigeki Yamaga, Chikao Kimura
  • Patent number: 5536360
    Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky
  • Patent number: 5527735
    Abstract: N-type c-BN is a heat-resistant material with a wide band gap. Ohmic electrodes are indispensable for making semiconductor devices utilizing n-type c-BN. The electrodes proposed so far are likely to deteriorate in an atmosphere of high temperature. The degradation of electrodes hinders the production of semiconductor devices utilizing c-BN. A heat-resistant ohmic electrode is produced by forming a low contact resistance layer of a boride or a nitride of Ti, Zr or Hf on a heated c-BN and by covering the low resistance layer by an Au layer. Otherwise an ohmic electrode is produced by forming a low contact resistance layer of one of Ti, Zr, Hf, etc. on c-BN, making a diffusion barrier layer of W, Mo, Ta or Pt and depositing an Au layer on the diffusion barrier layer.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: June 18, 1996
    Assignees: Sumitomo Electric Industries, Ltd., Research Institute of Innovative Technology for the Earth
    Inventors: Tadashi Tomikawa, Yoshiki Nishibayashi, Shin-ichi Shikata
  • Patent number: 5525542
    Abstract: An anti-reflective coating (ARC) (20) is formed over a reflective, conductive layer (18), such as polysilicon or aluminum, in a semiconductor device (10). The ARC is an aluminum nitride layer. During photolithography, the ARC absorbs radiation waves (30), particularly absorbing wavelengths under 300 nanometers, such as deep ultraviolet (DUV) radiation at 248 nanometers. Being absorbed by the ARC, the radiation waves are prevented from reflecting off the underlying conductive layer. Thus, resist mask (34) is patterned and developed true to the pattern on lithography mask (24), resulting in accurate replication into appropriate layers of the device.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: June 11, 1996
    Assignee: Motorola, Inc.
    Inventors: Papu D. Maniar, Robert W. Fiordalice, Kevin G. Kemp, Bernard J. Roman
  • Patent number: 5494861
    Abstract: A method for heat-treating a compound semiconductor comprising a step of heat-treating a susceptor in a manner as to be disposed on a surface of the compound semiconductor with oposing each other, the susceptor comprising a compound of nitrogen and a group III element such as aluminum nitride.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: February 27, 1996
    Assignee: New Japan Radio Co., Ltd.
    Inventors: Shigeki Yamaga, Chikao Kimura
  • Patent number: 5484740
    Abstract: A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: January 16, 1996
    Assignee: Motorola, Inc.
    Inventor: Jaeshin Cho
  • Patent number: 5444017
    Abstract: An ohmic electrode is formed on a cBN crystal to form a cBN semiconductor device which is used as a solid electronic element. The cBN semiconductor device may be of an n-type, a p-type or a pn junction type wherein molybdenum is deposited onto an n-type doped region of the cBN crystal or platinum is deposited onto a p-type doped region to thereby form an electrode with ohmic characteristic. The deposition of the molybdenum or the platinum is conducted by using a vapor deposition method followed by heating the attached substance at a temperature of 300.degree. C.-1100.degree. C. in an inactive gas atmosphere. The cBN semiconductor device can be used as a solid electronic element or an optoelectronic element for rectifiers, transistors, light emitting diodes and so on and integrated elements thereof.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: August 22, 1995
    Assignee: National Institute for Research in Inorganic Materials
    Inventors: Koh Era, Yoshiyuki Suda, Satoshi Agawa, Osamu Mishima
  • Patent number: 5389571
    Abstract: Disclosed are a gallium nitride type semiconductor device that has a single crystal of (Ga.sub.1-x Al.sub.x).sub.1-y In.sub.y N, which suppresses the occurrence of crystal defects and thus has very high crystallization and considerably excellent flatness, and a method of fabricating the same. The gallium nitride type semiconductor device comprises a silicon substrate, an intermediate layer consisting of a compound containing at least aluminum and nitrogen and formed on the silicon substrate, and a crystal layer of (Ga.sub.1-x Al.sub.x).sub.1-y In.sub.y N (0.ltoreq.x.gtoreq.1, 0.ltoreq.y.ltoreq.1, excluding the case of x=1 and y=0). According to the method of fabricating a gallium nitride base semiconductor device, a silicon single crystal substrate is kept at a temperature of 400.degree. to 1300.degree. C.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: February 14, 1995
    Assignees: Hiroshi Amano, Isamu Akasaki, Pioneer Electronic Corporation, Toyoda Gosei Co., Ltd.
    Inventors: Tetsuya Takeuchi, Hiroshi Amano, Isamu Akasaki, Atsushi Watanabe, Katsuhide Manabe
  • Patent number: 5385862
    Abstract: This invention relates to a method of preparing highly insulating GaN single crystal films in a molecular beam epitaxial growth chamber. A single crystal substrate is provided with the appropriate lattice match for the desired crystal structure of GaN. A molecular beam source of Ga and source of activated atomic and ionic nitrogen are provided within the growth chamber. The desired film is deposited by exposing the substrate to Ga and nitrogen sources in a two step growth process using a low temperature nucleation step and a high temperature growth step. The low temperature process is carried out at 100.degree.-400.degree. C. and the high temperature process is carried out at 600.degree.-900.degree. C. The preferred source of activated nitrogen is an electron cyclotron resonance microwave plasma.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 31, 1995
    Assignee: Trustees of Boston University
    Inventor: Theodore D. Moustakas
  • Patent number: 5384285
    Abstract: A transition-metal silicide process includes the formation of a boron nitride capping layer overlying a transition-metal layer. In one embodiment, a transition-metal layer (30) is deposited onto a silicon surface (22), and onto a polysilicon gate electrode (12). A capping layer (32), which can be either boron nitride or boron oxynitride is deposited onto the transition-metal layer (30), and an annealing process is carried out to form a transition-metal/silicon alloy layer (34, 36, 38) at the silicon surface (22), and on the gate electrode (12). The capping layer (32) overlies the transition-metal layer (30) during the annealing process and prevents the formation of an oxide layer at the silicon surfaces (22, 12). After the annealing process is complete, the capping layer (13) is removed by a selective wet etch process, and a second annealing step is carried out to form a transition-metal silicide layer (40, 42, 44).
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: January 24, 1995
    Assignee: Motorola, Inc.
    Inventors: Arkalgud Sitaram, Papu D. Maniar, Jeffrey T. Wetzel
  • Patent number: 5324690
    Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: June 28, 1994
    Assignee: Motorola Inc.
    Inventors: Avgerinos V. Gelatos, Stephen S. Poon
  • Patent number: 5296395
    Abstract: A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al.sub.x Ga.sub.1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is approximately 620 cm.sup.2 per volt second at room temperature as compared to 56 cm.sup.2 per volt second for bulk GaN of the same thickness deposited under identical conditions. The mobility of the bulk sample peaked at 62 cm.sup.2 per volt second at 180.degree. K. and decreased to 19 cm.sup.2 per volt second at 77.degree. K. The mobility for the heterostructure, however, increased to a value of 1,600 cm.sup.2 per volt second at 77.degree. K. and saturated at 4.degree. K.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: March 22, 1994
    Assignee: APA Optics, Inc.
    Inventors: Muhammad A. Khan, James M. VanHove, Jon N. Kuznia, Donald T. Olson
  • Patent number: 5272108
    Abstract: A gallium nitride semiconductor light-emitting device comprising: a substrate of semiconductor or insulator; an N layer of n-type gallium nitride semiconductor (Al.times.Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); an I layer of semiinsulating gallium nitride semiconductor (Al.sub.x Ga.sub.1-x N:0.ltoreq..times..ltoreq.1); a first electrode formed on the I layer; a low-resistance region extending from the first electrode through the I layer at least to the N layer and formed by diffusion of the material of the first electrode; and a second electrode formed on the I layer isolatedly from the first electrode.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: December 21, 1993
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyoda Gosei Co., Ltd.
    Inventor: Takahiro Kozawa
  • Patent number: 5270234
    Abstract: A deep submicron transistor fabrication method that employs only optical lithography involves the formation of a relatively wide aperture using optical techniques; the formation of composite sidewalls having differential etch resistance in the aperture to define a final aperture width less than that available with conventional optical techniques; the etching of the final aperture to expose a controlled channel length; the implantation of the channel through the aperture; and the implantation of source and drain with the sidewalls protecting previously doped LDD regions in the active area.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: December 14, 1993
    Assignee: International Business Machines Corporation
    Inventors: Daniel L. Huang, Louis L. Hsu, Wen-Yuan Wang
  • Patent number: 5227318
    Abstract: A bipolar transistor is formed from epitaxial cubic boron nitride grown on a silicon substrate which is a three to two commensurate layer deposited by pulsed laser evaporation techniques. The thin film, cubic boron nitride bipolar transistor is in epitaxial registry with an underlying single crystal silicon substrate. The bipolar transistor is particularly suitable for high temperature applications.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: July 13, 1993
    Assignee: General Motors Corporation
    Inventors: Gary L. Doll, Larry E. Henneman, Jr.
  • Patent number: 5210051
    Abstract: The invention is a method of growing intrinsic, substantially undoped single crystal gallium nitride with a donor concentration of 7.times.10.sup.17 cm.sup.-3 or less. The method comprises introducing a source of nitrogen into a reaction chamber containing a growth surface while introducing a source of gallium into the same reaction chamber and while directing nitrogen atoms and gallium atoms to a growth surface upon which gallium nitride will grow.
    Type: Grant
    Filed: June 5, 1991
    Date of Patent: May 11, 1993
    Assignee: Cree Research, Inc.
    Inventor: Calvin H. Carter, Jr.
  • Patent number: 5192409
    Abstract: A material for high-vacuum vessels characterized by depositing a mixture film of stainless steel and boron nitride on the surface of a metal or an alloy through the sputtering process, and heating and precipitating hexagonal boron nitride onto the surface thereof.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: March 9, 1993
    Assignee: National Research Institute For Metals
    Inventors: Masahiro Tosa, Kazuhiro Yoshihara
  • Patent number: 5081053
    Abstract: A method for forming a transistor which may be suitable for high temperature application is provided. A single crystal silicon substrate has an overlaying layer of epitaxially grown cubic boron nitride in crystallographic registry with the silicon substrate. The cubic boron nitride is epitaxially grown using laser ablation techniques and provides an electrically resistive and thermally conductive barrier. An active layer of epitaxial silicon is then grown from the layer of cubic boron nitride, such that the overlaying layer of epitaxial silicon is in crystallographic registry with the layer of boron nitride which is in crystallographic registry with the underlying silicon substrate. Appropriately doped source and drain regions and a gate electrode are provided to form the transistor.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: January 14, 1992
    Assignee: General Motors Corporation
    Inventors: Joseph P. Heremans, Gary L. Doll, Jeffrey A. Sell
  • Patent number: 5076860
    Abstract: A compound semiconductor material includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) containing B and P and having a zinc blend type crystal structure. A compound semiconductor element includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer having a zinc blend type crystal structure. A method of manufacturing a compound semiconductor element includes the step of sequentially forming a BP layer and a Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer on a substrate so as to form a heterojunction by using a metal organic chemical vapor deposition apparatus having a plurality of reaction regions, and moving the substrate between the plurality of reaction regions.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: December 31, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Toshihide Izumiya, Ako Hatano
  • Patent number: 5057454
    Abstract: A process for producing an ohmic electrode for p-type cBN is disclosed, which process comprises the steps of: providing a thin alloy film composed of Au and Be, the weight ratio of Be being from 0.1 to 15% by weight, on p-type cBN; providing a thin film of a metal selected from Ni, Cr, Mo, and Pt on the thin alloy film; and subjecting the p-type cBN having the films thus provided to a heat-treatment in an inert gas or in vacuo at a temperature of from 350.degree. C. to 600.degree. C.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: October 15, 1991
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsuhito Yoshida, Kazuwo Tsuji
  • Patent number: 5043219
    Abstract: A composite material useful as a diode capable of operating at a high temperature, i.e., 500.degree. to 600.degree. C. or a semiconductor optical device capable of emitting ultraviolet rays is provided which comprises an electrically insulating single crystal diamond substrate and single crystal cubic boron nitride directly formed on one surface of the single crystal diamond in such a manner that the single crystal cubic boron nitride has the same plane index as the substrate.
    Type: Grant
    Filed: January 19, 1990
    Date of Patent: August 27, 1991
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsuhito Yoshida, Kazuwo Tsuji
  • Patent number: 4931411
    Abstract: Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.
    Type: Grant
    Filed: December 20, 1988
    Date of Patent: June 5, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Howard L. Tigelaar, Roger A. Haken, Thomas C. Holloway, Robert Groover, III
  • Patent number: 4920073
    Abstract: The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.
    Type: Grant
    Filed: May 11, 1989
    Date of Patent: April 24, 1990
    Assignee: Texas Instruments, Incorporated
    Inventors: Che-Chia Wei, Thomas E. Tang, James G. Bohlman, Monte A. Douglas
  • Patent number: 4900526
    Abstract: The specification discloses a polycrystalline boron nitride of high purity and high density consisting essentially of rhombohedral crystals in which the three-fold rotation axes, parallel to the c-axis in the notation of hexagonal crystal system, of the crystals have a preferred orientation. The polycrystalline rhombohedral boron nitride can be obtained as bulk or thin film articles with desired shapes by chemical vapor deposition including the steps of introducing a source gas of boron and a source gas into a reactor containing a heated substrate and depositing boron nitride onto the heated substrate, wherein a diffusion layer of the source gas of nitrogen and/or the carrier gas is formed around the substrate. The polycrystalline rhombohedral boron nitride such obtained is very useful in applications such as crucibles for melting semiconductors, various jigs for high temperature services, high-frequency insulator, microwave transmission window and source material of boron for semiconductor.
    Type: Grant
    Filed: July 3, 1986
    Date of Patent: February 13, 1990
    Assignees: Research Development Corporation of Japan, Japan Metals & Chemicals Co., Ltd., The Furukawa Electric Company, Ltd., Toshio Hirai
    Inventors: Toshitsugu Matsuda, Hiroyuki Nakae, Toshio Hirai
  • Patent number: 4875967
    Abstract: A method for growing a single crystal of cubic boron nitride semiconductor in a growing container sealed under high pressure and high temperature conditions, which comprises dissolving in a dopant-containing boron nitride solvent a boron nitride starting material placed at a high temperature zone in the growing container, and providing a temperature gradient to the solvent so that the temperature dependence of the solubility is utilized to let the single crystal form and grow at a low temperature zone in the growing container.
    Type: Grant
    Filed: March 7, 1988
    Date of Patent: October 24, 1989
    Assignee: National Institute for Research in Inorganic Materials
    Inventors: Osamu Mishima, Shinobu Yamaoka, Osamu Fukunaga, Junzo Tanaka, Koh Era
  • Patent number: 4855249
    Abstract: In organometallic vapor phase hetero-epitaxial processes for growing Al.sub.x Ga.sub.1-x N films on a sapphire substrate, the substrate is subjected to a preheat treatment of brief duration, such as less than 2 minutes, at relatively low temperatures in an atmosphere comprising Al-containing organometallic compound, NH.sub.3 and H.sub.2 gases, prior to the hetero epitaxial growth of Al.sub.x Ga.sub.1-x N films. Thus, single crystalline Al.sub.x Ga.sub.1-x N layers of high uniformity and high quality having smooth, flat surfaces are provided. Multi-layers grown according to the process of the invention are free from cracks and have preferable UV or blue light emission properties.
    Type: Grant
    Filed: March 16, 1988
    Date of Patent: August 8, 1989
    Assignee: Nagoya University
    Inventors: Isamu Akasaki, Nobuhiko Sawaki
  • Patent number: 4761345
    Abstract: There is disclosed an aluminum nitride substrate which comprises a substrate composed of an aluminum nitride sintered product; an electroconductive metallized layer composed of titanium nitride and at least one selected from the group consisting of molybdenum, tungsten, tantalum, an element in group III of the periodic table, an element in group IVa of the same, a rare earth element, an actinide element and a compound containing these elements; and an electroconductive protective layer laminated in this order on the aluminum nitride sintered product.
    Type: Grant
    Filed: February 20, 1987
    Date of Patent: August 2, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Sato, Nobuyuki Mizunoya, Mitsuhiro Nagata
  • Patent number: 4570328
    Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.
    Type: Grant
    Filed: March 7, 1983
    Date of Patent: February 18, 1986
    Assignee: Motorola, Inc.
    Inventors: J. B. Price, Philip J. Tobin, Fabio Pintchovski, Christian A. Seelbach