Abstract: On a TEOS (tetraethyl ortho silicate) film and a surface of an aluminum wiring formed on a P-type silicon substrate, there is formed a low hydrogen content plasma SiN film on which a high hydrogen content plasma SiN film is laminated. The low hydrogen content plasma SiN film is lower in content of hydrogen than the high hydrogen content plasma SiN film. Accordingly, even when hydrogen is about to go toward and into the P-type silicon substrate side from the high hydrogen content plasma SiN film, the entry of hydrogen is blocked by the low hydrogen content plasma SiN film in which amount of Si--H bonds is reduced.

Abstract: A gate insulating film covering active layers of a insulated gate field effect semiconductor device utilizing a thin film silicon semiconductor comprises a thin film having the chemical formula SiO.sub.x N.sub.y. By making the concentration of N (nitrogen) high at the interface between the gate insulating film and the gate electrodes, it is possible to prevent the material composing the gate electrodes from being diffused in the gate insulating film. By making the concentration of N (nitrogen) high at the interface between the gate insulating film and the active layers, it is possible to prevent hydrogen ions and other ions from diffusing into the gate insulating film from the active layer.

Abstract: On TEOS (tetraethyl ortho silicate) film and a surface of an aluminum wiring formed on a P-type silicon substrate, there is formed a low hydrogen content plasma SiN film on which a high hydrogen content plasma SiN film is laminated. The low hydrogen content plasma SiN film is lower in content of hydrogen than the high hydrogen content plasma SiN film. Accordingly, even when hydrogen is about to go toward and into the P-type silicon substrate side from the high hydrogen content plasma SiN film, the entry of hydrogen is blocked by the low hydrogen content plasma SiN film in which amount of Si-H bonds is reduced.

Abstract: A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.

Abstract: A non-volatile memory device with a multi-layered gate electrode structure is fabricated by forming a floating gate electrode and a thermally oxidized silicon film on surfaces inclusive of a surface of the multi-layered gate electrode structure having a control gate electrode, and then forming, by a thermal nitrifying treatment, a thermally nitrified oxidized silicon film at an interface between the thermally oxidized silicon film and the multi-layered gate electrode structure. Diffusion of impurity into a multi-layered gate electrode structure of the memory is prevented and also leakage current due to mismatching at the film interface is reduced.

Abstract: A charge-coupled device (CCD) is provided having improved charge transfer efficiency. This CCD is a portion of an image sensor and manufactured by first laminating a first oxidation film and a first nitride film one after the other on a semiconductor substrate and then forming a plurality of first gate electrodes on the first nitride film at predetermined intervals apart. A second oxidation film is formed only on an upper surface and along side walls of each of the first gate electrodes. The first nitride film exposed between the first gate electrodes is removed and a second nitride film is formed on the exposed first oxidation film and the second oxidation film. A second gate electrode is then formed on the second nitride film between adjacent first gate electrodes. An image sensor is obtained in which leakage current density between the gate electrodes is reduced and the dielectric characteristic of a gate dielectric film is improved.

Abstract: The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.

Abstract: The method comprising the steps of: depositing a semiconductor layer serving as an active layer, a first gate insulation film and an second gate insulation film on an insulation-transparent substrate, in this order; patterning the second gate insulation film using a mask for the patterning of an active region so that it is remained merely at the active region; oxidizing the semiconductor layer except for the active region using the patterned second gate insulation film as an oxidization mask, to isolate the active region from the other portion; forming a gate electrode on the second gate insulation film corresponding to the upper side of the defined active region; implanting impurity-ions in the semiconductor layer using the gate electrode as an ion-implantation mask to form a source region and a drain region; forming a protection film on the whole exposed surface of the resultant structure; forming contact holes in the protection layer so that the source region and the drain region are exposed; and forming a

Abstract: A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.

Abstract: A new method of obtaining a consistent controllable tunnel oxide near the source/drain edge of a contactless memory cell is described. A thick gate oxide layer is grown on a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxide layer. A silicon nitride layer followed by a silicon oxide layer are deposited overlying the first polysilicon layer. The silicon oxide, silicon nitride, and first polysilicon layers are patterned and etched. Arsenic ions are implanted through the gate oxide layer into the substrate to form buried source and drain bit lines within the substrate. A second layer of silicon nitride is deposited over the patterned layers and anisotropically etched to form sidewall spacers. SATO (self-aligned thick oxide) oxidation is performed over the N+ area. The nitride spacers are etched away whereby a portion of the gate oxide underlying the spacers is exposed. The silicon oxide layer is removed along with the exposed gate oxide.

Abstract: A high density, high frequency, plasma-enhanced chemical vapor deposition (PECVD) process for depositing a passivation layer on a semiconductor integrated circuit wafer. The wafer rests on a grounded electrode while a second electrode disperses gases over the wafer. The second electrode disperses the gases in the same manner as a showerhead. An radio-frequency (RF) potential applied to the showerhead electrode causes the gases to react under specific temperature, pressure, and electrode spacing conditions. Furthermore, the present invention is a low particulate process. The process forms a film of high UV transparency. The chamber is cleaned after removal of the wafer, and gas lines are evacuated. This results in a low particle process.

Abstract: A semiconductor device is disclosed which comprises a semiconductor substrate and an insulating film disposed on the substrate. The insulating film is a oxynitride film prepared by nitriding a thermal oxide film, which has been formed on the substrate, in an atmosphere of nitriding gas. The nitriding is conducted for a nitridation time of 10.sup.6.6-T N.sup./225 seconds or shorter wherein T.sub.N is in the nitridation temperature in degree centigrade, or conducted so as to have a nitrogen concentration of about 8 atomic % or less, at least in the vicinity of the interface between the oxynitride film and the substrate. Also disclosed is a method for the production of the semiconductor device.

Abstract: A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.

Abstract: A fabrication process includes at least a step of low pressure CVD for depositing an upper silicon oxide layer on a silicon nitride layer which is formed through a lower silicon oxide layer on a silicon substrate, a next step of forming a gate electrode on the second oxide layer, and a further step of selectively removing the second oxide layer and instead forming a similar silicon oxide layer anew. This process can meet the demand for device miniaturization, improve the C-V characteristic of a MOS capacitor and provide uniform insulating layers.

Abstract: In a method of forming an insulating film, a silicon dioxide film is formed on a silicon substrate by performing heat treatment in an oxidizing gas atmosphere which does not contain nitrogen, and then the silicon dioxide film is oxynitrided by performing heat treatment in an nitrous oxide atmosphere. Prior to the formation of the silicon dioxide film, the silicon substrate is cleaned by heating it in a reducing gas atmosphere, and then heating it in a reactive gas atmosphere.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase region is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. Ammonia formed during the field oxidation process reacts with the silicon substrate to form a thin silicon nitride layer in the beak region. A thin tunnel oxide is then grown without the use of a sacrificial-oxide growth and removal method. During tunnel oxide formation lateral growth of the field oxide is inhibited by the thin nitride layer previously formed. However, the tunnel oxide thinning (due to the existence of the thin nitride layer) induced low breakdown voltage is overcome by the enhanced oxide growth in the beak due to the buried source/drain dopants. The tunnel oxide in the erase regon is therefore uniform and thin. The thin, uniform oxide in the tunnel region leads to improved erase characteristics.

Abstract: An insulative film, such as SiO.sub.2, Si.sub.3 N.sub.4 and PSG films, for example, is commonly used the passivation film or gate electrode of MISFETs. Stability of the insulative films during the production or operation of the semiconductor devices is enhanced by providing an insulative film which is formed by nitridation, for example, in an NH.sub.3 gas, of an SiO.sub.2 film, preferably a directly thermally oxidized film of silicon. The insulative film according to the present invention is used for a gate insulation film in MISFETs, a capacitor or passivation film for semiconductor devices, and as a mask for selectively forming circuit elements of semiconductor devices. The process for forming the insulative film may comprise successive nitridation, oxidation and nitridation steps.

Abstract: A process by which thin films of silicon nitride are deposited on silicon substrates by plasma enhanced chemical vapor deposition techniques is stabilized by post-deposition rapid thermal annealing at temperatures ranging from about 600.degree. C. to about 700.degree. C. and at times ranging from about 3 seconds to about 30 seconds.

Abstract: Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Abstract: In a low-pressure reactor, the addition of nitrogen trifluoride to a gaseous organosilicon compound such as tetraethoxysilane (TEOS) or tetramethylcyclotetroxysilane (TMCTS) results in surprisingly enhanced silicon dioxide deposition rates. The oxide deposited using this process also has the capability of filling features having aspects ratios up to at least 1.0, and may exhibit low mobile ion concentrations. The process is also applicable for depositing other silicon-containing films such as polysilicon and silicon nitride.

Abstract: For enhancement of device stability, there is disclosed a semiconductor device fabricated on a semiconductor substrate comprising (a) source and drain regions formed in a surface portion of the semiconductor substrate and spaced from each other by a channel region, (b) a gate insulating film formed on the channel region, (c) a gate electrode structure formed on the gate insulating film, and (d) a passivation film of an insulating material covering the gate electrode structure and containing hydrogen-bonded-silicons equal in number to or less than 5.times.10.sup.21 per cm.sup.3, and the unstable hydrogen-bonded-silicons are decreased in number so that the semiconductor device only have a decreased trap density which results in stable operation.

Abstract: A process for forming a thin sealing layer of silicon nitride directly upon a silicon substrate to minimize bird's beak encroachment. The process employs in situ fabrication whereby the native oxide is removed from the silicon substrate by etching the hydrogen or hydrogen chloride and followed in direct succession, and in the absence of exposure to an oxidizing environment, with the deposition of a silicon nitride layer by LPCVD. Bird's beak encroachment is incrementally reduced by the absence of the native oxide layer as a path for oxygen species movement during the field oxide growth.

Abstract: A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.

Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.

Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.A subsequent annealing process involving controlled temperatures and cycle times provides for determining desired resistive values from an equivalent deposition process. Further, a barrier metal layer may be formed between the vertical resistor and the second conductive region.

Abstract: An annealing process carried out at 800.degree. C. in a wet O.sub.2 ambient permits the manufacture of a reliable storage capacitor wherein the dielectric layer is comprised of silicon oxynitride formed by low pressure chemical vapor deposition (LPCVD). The manufacturing process includes first depositing the silicon oxynitride film by LPCVD, second annealing in wet O.sub.2 at 800.degree. C. or N.sub.2 at 1000.degree. C., third forming an N-type region in the silicon substrate by As.sup.+ ion implantation through the silicon oxynitride film, fourth annealing in wet O.sub.2 at 800.degree. C., and fifth depositing an electrode.

Abstract: A method of producing a semiconductor memory device comprises the steps of forming a first mask on a substrate and forming an opening in the first mask, implanting impurity ions into the substrate from the opening in the first mask so as to form an impurity region, forming a side wall layer of oxidation-resistant material having a predetermined width on a side surface of the opening in the first mask, forming a tunnel region having a width determined by the predetermined width by using the oxidation-resistant side wall layer as a second mask and forming a gate part on the tunnel region.

Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.

Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.

Abstract: A method of forming a silicon nitride coating in situ on a silicon surface by ion milling. The ion milling and silicon nitride formation process are uniquely integrated in semiconductor manufacturing methods to provide several benefits, including contact areas being substantially registered with and self-aligned with functional regions.