Abstract: The present invention proposes a method for fabricating field oxide regions for isolation by an improved poly-buffered local oxidation of silicon (PBLOCOS) process. A polysilicon layer is utilized to reduce the bird's beak, and a thin thermal oxide film is formed on the buffered polysilicon film to prevent pitting formation. Forming a thin pad oxide and a silicon layer, a thermal oxidation is carried out to grow another pad oxide on the silicon layer and crystallize the silicon into polysilicon. The buffered layer of stacked oxide-polysilicon-oxide layer is thus formed. The silicon nitride layer is then deposited on the stacked buffered layer and the active areas are defined. A thermal oxidation is now performed, and thick field oxide regions are grown. After the masking nitride layer and the stacked buffered layer are stripped, the MOS devices are fabricated, and thus complete the present invention.

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

Abstract: The process comprises the steps of growing a first oxide layer on the upper surface of a substrate; depositing a silicon nitride layer on top of the first oxide layer; patterning the silicon nitride layer with a photoresist mask to define field oxide areas; stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer; removing the remnants of the silicon nitride layer; stripping the pad oxide layer and growing a sacrificial oxide layer; masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed; stripping the sacrificial oxide not protected by the photoresist; stripping the photoresist; and growing a gate oxide layer which is thinner than the sacrificial oxide layer. Thereafter, fabrication of the memory device may be completed using any known prior art techniques.

Abstract: A method of forming a native oxide from an aluminum-bearing Group III-V semiconductor material is provided. The method entails exposing the aluminum-bearing Group III-V semiconductor material to a water-containing environment and a temperature of at least about 375 C to convert at least a portion of said aluminum-bearing material to a native oxide characterized in that the thickness of said native oxide is substantially the same as or less than the thickness of that portion of said aluminum-bearing Group III-V semiconductor material thus converted. The native oxide thus formed has particular utility in electrical and optoelectrical devices, such as lasers.

Abstract: A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.

Abstract: An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.

Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.

Abstract: A method of fabricating a memory device for improving the reliability of the cell area and the driving capability of the peripheral area is disclosed, wherein the method comprises the steps of forming a cell area and a peripheral area by forming a field oxidation layer over a first conductive semiconductor substrate, forming gate oxidation layers of the different thickness from each other over a surface of the substrate which corresponds to the cell area and the peripheral area through once oxidation process, forming a gate over the gate oxidation layer, and implanting a second conductive impurity ion into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell and peripheral area, thereby forming respective MOS transistors on each of the cell area and the peripheral area.

Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.

Abstract: Electron emitters and a method of fabricating emitters which have a concentration gradient of impurities, such that the highest concentration of impurities is at the apex of the emitters, and decreases toward the base of the emitters. The method comprises the steps of doping, patterning, etching, and oxidizing the substrate, thereby forming the emitters having impurity gradients.

Abstract: A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate.

Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.

Abstract: A device and method of manufacturing the device comprising a self-aligned, split-gate EPROM/Flash EPROM array device. Ions are implanted into locations in a doped well in a substrate to form buried bit lines, a forming a thick dielectric over the implanted ions, implanting a first threshold voltage V.sub.

Abstract: Dual field oxide isolation (34 & 42) is formed by oxidizing through a portion (44) of a silicon nitride layer (30), through an exposed portion (43) of a remaining portion (18) of a masking layer (16), and through an exposed portion (42) of a buffer layer (28), all of which overlie isolation regions (22) of the silicon substrate (12). The different portions vary the diffusion rate of oxygen so that different field oxide thicknesses are created in a single field oxidation cycle. Therefore, integrated circuits having both low voltage densely packed devices and high voltage devices can be fabricated on the same circuit.

Abstract: A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.

Abstract: A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.

Abstract: A method of producing a semiconductor substrate, which comprises forming a monocrystalline silicon layer on a porous silicon substrate by epitaxial growth and applying an oxidation treatment to the porous silicon substrate and the monocrystalline silicon layer at least near the interface between the porous silicon substrate and the monocrystalline silicon layer.

Abstract: A substantially planar semiconductor surface is formed for fabricating submicron BiCMOS integrated circuits. A lightly doped epitaxial layer is formed on a semiconductor substrate having buried layers formed therein. The substantially planar semiconductor surface is formed by forming a p-type well in the lightly doped epitaxial layer before the step of forming an n-type well in the lightly doped epitaxial layer.

Abstract: A dielectric buried layer is formed inside substrates which are directly bonded together. Firstly, a groove or a recess, or both are formed on the principal bonding plane of one of at least two kinds of semiconductor substrates to be bonded together. Once the semiconductor substrates are bonded together, the groove and recess form a space, which is filled with dielectric. Before forming the dielectric buried layer, the invention carries out a process of removing potential damage from corners of the groove and/or recess.

Abstract: The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.

Abstract: A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.

Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

Abstract: A self-aligned salicide process produces small dimensioned semiconductor devices, for example metal oxide semiconductor (MOS) devices. An electrode is formed on the face of a semiconductor substrate, the electrode having a top and a sidewall and an insulating coating on the sidewall. Then a silicon layer and a refractory metal layer are formed on the face, top and sidewall, with one of the layers being continuous, and the other layer having a break on the sidewall. In a preferred embodiment the silicon layer is directionally applied, to form thick portions on the face and top and thin portion on the sidewall. The thin portion on the sidewall is removed and a metal layer is uniformly deposited. The substrate is heated to convert at least part of the silicon and metal layers to silicide. The silicide layer on the face is planar and does not consume the substrate at the face, allowing shallow source and drain regions to be formed.

Abstract: To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is then filled with a suitable insulating material to isolate the active island from the substrate.

Abstract: A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.

Abstract: A method of forming single crystal islands (30) by epitaxial growth from a monocrystalline substrate (10). A <100> or other suitable low index surface is preferentially etched to void an inverted pyramid section (16) with <111> or other suitable low index sidewalls (18). The <100> bottom (17) of the pyramid section is covered with insulation (20) and island refill material (24) is grown epitaxially from the sidewalls (18). The islands (30) are laterally isolated (25, 28) from the sidewalls (13) and the structure is finished to provide a substrate on which to form various IC devices.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: The disclosure relates to a bipolar transistor having reduced base-collector capacitance and a method of making the transistor by forming a sidewall base contact with polycrystalline silicon-on-insulator. The structure is achieved by using differential oxidation to grow thicker oxide over heavily doped N+ regions in a sacrificial polycrystalline silicon layer with the sidewall base region being protected from doping by a sidewall oxide and limited anneal of the N+ dopant. Both NPN and PNP bipolar transistors with minimum collector-base capacitance can be fabricated using this technique.