Power Fets Patents (Class 148/DIG126)
  • Patent number: 6162665
    Abstract: A high voltage transistor or thyristor having a base layer which is a thinned neutron transmuted wafer 102, 152 instead of a diffused or epitaxially grown base layer. The neutron transmuted wafer has high resistivity and a desired thickness while the layer formed overlying the surface of the neutron transmuted wafer has a desired thickness and doping level. Adjusting the thicknesses and doping levels within these two structures produce a device having the desire high voltage characteristics. The various embodiments provides for a high voltage MOSFET 100, IGBT 170, and thyristor.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: December 19, 2000
    Assignee: Ixys Corporation
    Inventor: Nathan Zommer
  • Patent number: 6080614
    Abstract: A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: June 27, 2000
    Inventors: John Manning Sauidge Neilson, Linda Susan Brush, Frank Stensney, John Lawrence Benjamin, Anup Bhalla, Christopher Lawrence Rexer, Richard Douglas Stokes, Christopher Boguslow Kocon, Louise E. Skurkey, Christopher Michael Scarba
  • Patent number: 6017797
    Abstract: There is provided a method of fabricating a semiconductor device including, a first conductivity type MOSFET, a second conductivity type MOSFET, and a power MOSFET having a high breakdown voltage, and having a drain offset region formed in the substrate between the drain region and a channel region located below the gate electrode, and containing first conductivity type impurities therein at such a concentration that carriers are depleted in an operation of the semiconductor device, the method including the steps, in sequence, of (a) forming gate electrodes on the substrate in first, second and third regions where the first conductivity type MOSFET, the second conductivity type MOSFET, and the power MOSFET are to be fabricated, respectively, (b) introducing first conductivity type impurities into the substrate at such a concentration that carriers are depleted in an operation of the semiconductor device, (c) introducing first conductivity type impurities into the substrate with both the second region and a re
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: January 25, 2000
    Assignee: NEC Corporation
    Inventor: Akio Furukawa
  • Patent number: 5994188
    Abstract: A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: November 30, 1999
    Assignee: Delco Electronics Corporation
    Inventor: Donald Ray Disney
  • Patent number: 5904575
    Abstract: A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: May 18, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Emi Ishida, Xiao-Yu Li, Sunil D. Mehta
  • Patent number: 5904525
    Abstract: A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: May 18, 1999
    Assignee: Siliconix incorporated
    Inventors: Fwu-Iuan Hshieh, Yueh-Se Ho, Bosco Lan, Jowei Dun
  • Patent number: 5885878
    Abstract: To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: March 23, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoto Fujishima, Akio Kitamura
  • Patent number: 5879994
    Abstract: An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: March 9, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Sze-Hon Kwan, Izak Bencuya, Steven P. Sapp
  • Patent number: 5821144
    Abstract: An IGFET device (lateral DMOS transistor) with reduced cell dimensions which is especially suitable for RF and microwave applications, includes a semiconductor substrate having an epitaxial layer with a device formed in a surface of the epitaxial layer. A sinker contact is provided from the surface to the epitaxial layer to the substrate for use in grounding the source region to the grounded substrate. The sinker contact is aligned with the source region and spaced from the width of the channel region whereby lateral diffusion in forming the sinker contact does not adversely affect the pitch of the cell structure. The reduced pitch increases output power and reduces parasitic capacitance whereby the device is well-suited for low side switches and as an RF/microwave power transistor.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: October 13, 1998
    Assignee: Spectrian, Inc.
    Inventors: Pablo E. D'Anna, Francois Hebert
  • Patent number: 5817546
    Abstract: A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: October 6, 1998
    Assignees: STMicroelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Giuseppe Ferla, Ferruccio Frisina
  • Patent number: 5766966
    Abstract: A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5.times.10.sup.12 atoms per centimeter squared and is driven for about 10 hours at 1175.degree. C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage, drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: June 16, 1998
    Assignee: International Rectifier Corporation
    Inventor: Chiu Ng
  • Patent number: 5750429
    Abstract: In a semiconductor device of the insulated gate type, a side wall silicon oxide layer of a desired width is formed on each side wall of a gate electrode and a silicon oxide layer to reduce a distance between the contact end of a source electrode with an N.sup.+ -type source region and the internal end of the gate electrode thereby to decrease the on-resistance even if the impurity concentration of the N.sup.+ -type is determined to be low. Since the impurity concentration of the N.sup.+ -type source region is lower than that of a P.sup.+ -type body region and higher than the surface impurity concentration of a P-type body region, the base width of a parasitic bipolar transistor related to the P-type body region is maintained in a proper value without increasing the depth of the N.sup.+ -type source region in excess.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: May 12, 1998
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tomoyoshi Kushida
  • Patent number: 5750416
    Abstract: A power field effect transistor has a laterally extending channel region which is not formed by double diffusion. The channel region may be formed in epitaxial silicon which is not doped after being grown. The drain electrode of the transistor is disposed on a bottom surface of the substrate upon which the transistor structure is formed. When the transistor is turned on, the channel region inverts thereby forming a conductive path from a source region, laterally through the inverted channel region, substantially vertically through a sinker region to the underlying substrate, through the substrate, and to the drain electrode.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 12, 1998
    Assignee: Siliconix Incorporated
    Inventors: Fwu-Iuan Hshieh, Mike F. Chang, Jan Van der Linde, Yueh-Se Ho
  • Patent number: 5721148
    Abstract: In a method for manufacturing a MOS type semiconductor device, a first conductivity type layer is formed in a surface layer of a second conductivity type base region on a first conductivity type drain layer, a gate trench is formed in the base region, and a gate electrode is then formed in the gate trench through a gate insulation film. An exposed surface of the obtained structure is covered with an inter-layer insulation film, and a source contact trench that reaches inside the second conductivity type base region is formed through the inter-layer insulation film and first conductivity type layer while a gate contact trench that reaches inside the gate electrode is formed through the inter-layer insulation film. A portion of the inter-layer insulation film and the source contact trench are covered with a first metal film that forms a source electrode, and another portion of the inter-layer insulation film and the gate contact trench are covered with a second metal film that forms a gate metal electrode.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: February 24, 1998
    Assignee: Fuji Electric Co.
    Inventor: Takeyoshi Nishimura
  • Patent number: 5714396
    Abstract: A semiconductor structure having an edge termination feature wherein a first doped region and a second doped region are selectively formed in a semiconductor layer. The second doped region is coupled with the first doped region and has an impurity concentration less than that of the first doped region. An insulating layer is disposed over the semiconductor layer and over at least a portion of the second doped region. A conductive layer, having a coil-shaped configuration, is disposed over the insulating layer and is coupled to the semiconductor layer.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: February 3, 1998
    Assignee: Motorola, Inc.
    Inventors: Stephen Robb, Paul Groenig
  • Patent number: 5702961
    Abstract: Forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells includes forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to define a plurality of vertical IGBT cells.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: December 30, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hong Park
  • Patent number: 5696010
    Abstract: A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: December 9, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder Malhi
  • Patent number: 5693547
    Abstract: An integrated circuit transistor vertically oriented along a side wall of a shallow trench formed in a semiconductor substrate. The transistor includes a semiconductor substrate, preferably comprised of silicon, into which a shallow transistor trench has been formed. A trench floor of the transistor trench is vertically displaced below the upper surface of the semiconductor substrate by a trench depth. The transistor further includes a drain impurity distribution having a peak concentration that is vertically displaced a drain depth below the semiconductor substrate upper surface. The drain depth is less than the trench depth. The transistor further includes a channel impurity distribution having a peak concentration vertically displaced a channel depth below the substrate upper surface. The channel depth is greater than the drain depth, but less than the trench depth. The drain impurity distribution and the channel impurity distribution extend laterally to a first side wall of the transistor trench.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: December 2, 1997
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Michael Duane
  • Patent number: 5670392
    Abstract: A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the in
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: September 23, 1997
    Assignees: SGS-Thomson Microelectronics S.r.l., Consorzio per la Ricerca Sulla Microettronica nel Mezzogiorno
    Inventors: Giuseppe Ferla, Ferruccio Frisina
  • Patent number: 5654208
    Abstract: The present invention relates to a method for producing a semiconductor device having a semiconductor layer of SiC. The method comprises the steps of a) applying a mask on at least a portion of the SiC layer to coat a first portion of the SiC layer leaving a second portion thereof uncoated, b) applying a heat treatment to the SiC layer, and c) supplying dopants to the SiC layer during the heat treatment for diffusion of the dopants into the SiC layer at the second portion thereof for doping the SiC layer. The mask is made of crystalline AIN as the only component or AIN as a major component of a crystalline alloy constituting the material.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: August 5, 1997
    Assignee: ABB Research Ltd.
    Inventors: Christopher Harris, Andrei Konstantinov, Erik Janzen
  • Patent number: 5602046
    Abstract: In one embodiment, modifications to the polysilicon gate, body, source, and contact masks of a DMOS process add a source-body monocrystalline gate protection diode under the gate pad by implanting an anode region beneath the gate. The anode is connected to the gate through the gate metal in the pad. In addition to the gate-source diode, there is a connection from the drain to the gate through the anode formed by the body region beneath the gate. This embodiment includes a junction terminating field plate. The field plate creates a protection device similar to a zener diode, but exhibits a current/voltage characteristic similar to a thyristor. A significant feature of this embodiment is that the zener breakdown voltage is easily adjusted by a simple modification to the fabrication process. The field plate creates two opposing junctions with the spacing determined by the field plate length.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: February 11, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Daniel Calafut, Izak Bencuya, Steven Sapp
  • Patent number: 5595921
    Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: January 21, 1997
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Flavio Villa, Enrico M. A. Ravanelli
  • Patent number: 5591655
    Abstract: A vertical switched-emitter device structure in which the body of vertical-current-flow MOS device is formed in a P-type surface epi region, and dielectric isolation laterally separates the body from the surface contact to the buried P-type base region.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: January 7, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 5589405
    Abstract: The breakdown voltage of a VDMOS transistor is markedly increased without depressing other electrical characteristics of the device by tying the potential of a field-isolation diffusion, formed under the edge portion of a strip of field oxide separating a matrix of source cells from a drain diffusion, to the source potential of the transistor. This may be achieved by extending a body region of a peripheral source cell every given number of peripheral cells facing the strip of field-isolation structure until it intersects said field-isolation diffusion. By so connecting one peripheral source cell every given number of cells, the actual decrement of the overall channel width of the integrated transistor is negligible, thus leaving unaltered the electrical characteristics of the power transistor.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: December 31, 1996
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Claudio Contiero, Paola Galbiati, Lucia Zullino
  • Patent number: 5585287
    Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: December 17, 1996
    Assignee: Consorzio per la Ricerca sulla Microelecttronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5583060
    Abstract: The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: December 10, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Helmut Hertrich, Helmut Strack, Jenoe Tihanyi
  • Patent number: 5559044
    Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: September 24, 1996
    Assignee: Siliconix incorporated
    Inventors: Richard K. Williams, Hamza Yilmaz, Michael E. Cornell, Jun W. Chen
  • Patent number: 5556792
    Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 17, 1996
    Assignee: Consorzio per la Ricerca sulla Microelecttronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5554546
    Abstract: A high voltage transistor includes a semiconductor-on-insulator (SOI) region in which a source and a channel are formed. A drain drift region is further formed partly in the SOI region and partly in the bulk silicon region beyond SOI and a gate is coupled to said SOI channel.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Inc.
    Inventor: Satwinder Malhi
  • Patent number: 5547886
    Abstract: In an SOI substrate including a single-crystal Si substrate (1b), an oxide film (20) and a single-crystal Si substrate (1a), there is formed an stepped wall surface (8) by selective removal of the single-crystal Si substrate (1a) to provide a thick oxide film (5) on the stepped wall surface (8). When a VDMOS (100) is formed in an active region of the single-crystal Si substrate (1b) above which the single-crystal Si substrate (1a) is absent and an MOS (101) having a thin oxide film (22) is formed in the single-crystal Si substrate (1a), the oxide film (5) is not damaged because it is thick. The thickness of the single-crystal Si substrate (1a) enables to be designed in accordance with the required thickness of the MOS (101).
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: August 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masana Harada
  • Patent number: 5541122
    Abstract: A method of fabricating a fast-switching, low-R(on) insulated-gate bipolar transistor including providing an N-type semiconductor wafer with a planar surface, forming a thin heavily-doped layer, having a concentration in the range of 3.times.10.sup.17 /cm.sup.3 to 1.times.10.sup.19 /cm.sup.3, in the wafer adjacent the planar surface, providing a P-type semiconductor wafer, and bonding a surface of the P-type wafer to the planar surface of the N-type wafer. An emitter and a gate are then formed in the N-type wafer in the usual manner and a collector is formed on the P-type wafer.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: July 30, 1996
    Assignee: Motorola Inc.
    Inventors: Shang-Hui L. Tu, Gordon Tam, Pak Tam
  • Patent number: 5514608
    Abstract: An LDD lateral DMOS transistor is provided in a lightly-doped epitaxial layer of a first conductivity above a substrate of the same conductivity. A highly-doped buried layer of the first conductivity is provided under the LDD lateral DMOS transistor to relieve crowding of electrical equipotential distribution beneath the silicon surface. In one embodiment, a gate plate is provided above the gate and the gate-edge of the drift region. An optional N-well provides further flexibility to shape electric fields beneath the silicon surface. The buried layer can also reduce the electric field in a LDD lateral diode and improves cathode-to-anode reversed-recovery characteristics.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: May 7, 1996
    Assignee: Siliconix Incorporated
    Inventors: Richard K. Williams, Michael E. Cornell
  • Patent number: 5512495
    Abstract: A high voltage PMOS transistor 7 has improved on resistance by adjusting impurity concentration in a lightly doped drift region rim 48 to compensate for impurity segregation which occurs during the growth phase of a thick field oxide 43. During fabrication of high voltage PMOS device 7, a shallow vertical junction 230 formed by impurity segregation into field oxide 43. Implanting an HV drift region p-tank rim adjustment 220 and annealing it forms a lateral junction 250 and isolates the shallow junction 230 under field oxide 43. Thereby, the on-resistance of high voltage PMOS transistor 7 is minimized.
    Type: Grant
    Filed: February 16, 1995
    Date of Patent: April 30, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Chia-Cu P. Mei, Satwinder Malhi
  • Patent number: 5508217
    Abstract: A vertical type field effect transistor includes N-type base regions formed on the surface of a P-type semiconductor substrate, a P-type source region formed in each of the N-type base regions, a gate insulating film formed between the P-type source regions, and a gate electrode formed of polysilicon on the gate insulating film. The transistor has the P-type source regions, the N-type base regions and a lower portion of the P-type semiconductor substrate as three terminals. A method for manufacturing the transistor comprises the steps of: forming the gate insulating film; growing a polysilicon layer; performing ion injection of an N-type impurity for the grown polysilicon layer; and performing heat treatment after the ion injection.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: April 16, 1996
    Assignee: NEC Corporation
    Inventor: Masami Sawada
  • Patent number: 5506153
    Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: April 9, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Heinrich Brunner, York C. Gerstenmaier
  • Patent number: 5500377
    Abstract: A semiconductor device is fabricated which has reduced power dissipation when the device is turned on and runs cooler in surge suppressor applications. This result is achieved by fabricating a device where the breakdown action takes place preferentially under cathode region. The lower power dissipated during the turn-on action enables the device to operate in environmental conditions from -20.degree. C. to 65.degree. C.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: March 19, 1996
    Assignee: Motorola, Inc.
    Inventors: Emmanuel S. Flores, Juan L. D. V. Padilla
  • Patent number: 5498553
    Abstract: A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided.
    Type: Grant
    Filed: November 1, 1993
    Date of Patent: March 12, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Sheng-Hsing Yang
  • Patent number: 5482888
    Abstract: A metal oxide semiconductor field effect transistor power device with a lightly doped silicon substrate includes a source region and a drain region. At least one field implanted island region is formed along the surface of the oppositely substrate between the source and drain regions with a field oxide region formed above the field implanted region, a dielectric layer and a gate electrode of matching configurations formed over the substrate, and self-aligned source drain regions implanted into the device with external electrodes connected thereto.
    Type: Grant
    Filed: August 12, 1994
    Date of Patent: January 9, 1996
    Assignee: United Microelectronics Corporation
    Inventors: Ching-Hsiang Hsu, Ta-chi Kuo, Nai J. Yeh, Su Lu
  • Patent number: 5474944
    Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.
    Type: Grant
    Filed: December 7, 1992
    Date of Patent: December 12, 1995
    Assignees: SGS-Thomson Microelectronics, S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Raffaele Zambrano
  • Patent number: 5474946
    Abstract: A process for forming a MOS gated device in which an oxide layer is patterned to have adjacent thick and thin oxide layers atop a silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the base regions previously formed. A contact opening mask which is critically aligned to the polysilicon mask forms openings for making contact to the silicon. The device is completed using non-critical alignment masking steps.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: December 12, 1995
    Assignee: International Rectifier Corporation
    Inventors: Janardhanan S. Ajit, Daniel M. Kinzer
  • Patent number: 5472908
    Abstract: The destruction-free rapid dismantling of current of power semiconductor components can be substantially enhanced when the inhibiting pn-junction is produced with a polished surface of the semiconductor body. The pn-junction thus becomes so uniform that local overloads are avoided. As a result, the speed of the dismantling of the current of the power semiconductor can be increased.
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: December 5, 1995
    Assignee: Eupec Europaeische Gesellsch. F. Leitsungshalbleiter mbH & Co. KG
    Inventors: Wolfgang Pikorz, Alois Sonntag
  • Patent number: 5470770
    Abstract: A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well.
    Type: Grant
    Filed: March 30, 1995
    Date of Patent: November 28, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigeki Takahashi, Mitsuhiro Kataoka, Tsuyoshi Yamamoto
  • Patent number: 5468668
    Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: November 21, 1995
    Assignee: Harris Corporation
    Inventors: John M. S. Neilson, Carl F. Wheatley, Jr., Frederick P. Jones, Victor A. K. Temple
  • Patent number: 5460985
    Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: October 24, 1995
    Assignee: Ipics Corporation
    Inventors: Norihito Tokura, Shigeki Takahashi
  • Patent number: 5453390
    Abstract: A power semiconductor device having current detecting function comprising a detection pert that includes the elements of a better reach-through withstand voltage capability than those of a principal current part. The power semiconductor device comprises such elements as DMOS, IGBT or BPT cells. One area of the device acts as the detection part and another as the principal current part. The detection part and the principal current part share as their common electrode a high density substrate having a low density layer of a first conductivity type. The surface of the low density layer carries a principal and a subordinate well region of a second conductivity type each. The surface of the principal well region bears a surface electrode region of the first conductivity type acting as the other electrode of the principal current part; the surface of the subordinate well region carries a surface electrode region of the first conductivity type acting as the other electrode of the detection part.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: September 26, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Toshiaki Nishizawa, Akira Kuroyanagi, Tsuyoshi Yamamoto, Norihito Tokura
  • Patent number: 5451533
    Abstract: A bidirectional current blocking lateral power MOSFET including a source and a drain which are not shorted to a substrate, and voltages that are applied to the source and drain are both higher than the voltage at which the body is maintained (for an N-channel MOSFET) or lower than the voltage at which the body is maintained (for a P-channel MOSFET). The on-resistance of the MOSFET is improved by decreasing the conductance of the epi region and disposing a thin threshold adjust layer on the surface of the substrate between the source and drain regions. An optional second punchthrough preventing implant is disposed on the substrate surface.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: September 19, 1995
    Assignee: Siliconix incorporated
    Inventors: Richard K. Williams, Kevin Jew, Jun W. Chen
  • Patent number: 5443999
    Abstract: A semiconductor device is formed from a thyristor and a MOSFET cascade-connected in which the thyristor includes a bipolar transistor cascade-connected with the MOSFET, the base (p semiconductor region) of which is adapted to be punched through by the application of a working voltage. Thus, the thyristor can easily be latched and unlatched in response to the turn-on and turn-off of the MOSFET. Thus the semiconductor device can be securely on/off controlled by only the single gate (G) of the MOSFET. By using such semiconductor device as a switching element in a flash control device, a high performance flash control device with high flashing efficiency is provided.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: August 22, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Hiroshi Yamaguchi, Yasuaki Fukumochi
  • Patent number: 5434095
    Abstract: A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: July 18, 1995
    Assignee: Sundstrand Corporation
    Inventor: Theodore G. Hollinger
  • Patent number: 5424231
    Abstract: A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor's implanted regions, while simultaneously increasing the respective thicknesses of the gate oxide layers corresponding to the implanted regions along the current flow path.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: June 13, 1995
    Assignee: United Microelectronics Corp.
    Inventor: Sheng-Hsing Yang
  • Patent number: 5405794
    Abstract: A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: April 11, 1995
    Assignee: Philips Electronics North America Corporation
    Inventor: Manjin J. Kim