Purification Patents (Class 148/DIG130)
  • Patent number: 5252512
    Abstract: GaAs films compensated with TEOV to reduce free electron concentration are grown having superior morphology by heating the TEOV above the temperature used in the prior art, filtering the other constituents but not the TEOV, and reducing the arsenic ambient during the preliminary heating phase.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: October 12, 1993
    Assignee: United Technologies Corporation
    Inventors: Alexander J. Shuskus, Melvyn E. Cowher
  • Patent number: 5143867
    Abstract: A method for filling VLSI high aspect ratio vias and lines in VLSI interconnection structures, with a low resistivity metal at temperatures below 400.degree. C. A low melting point alloy of a desired low resistivity metal is deposited into the high aspect ratio vias or lines. The alloy is then purified in place by bringing the alloying element to the surface of the deposited alloy and removing the element from said surface thereby leaving the low resistivity metal in the interconnection structure. In one embodiment, the alloy is purified by using a low temperature oxidation process to allow the alloying element to diffuse to the surface of the deposited alloy where a surface oxide is formed. The surface oxide is then removed by chemical etching or by chemical mechanical polishing. In a second embodiment, a continuous exposure to a plasma etching or reactive ion etching will steadily remove the alloying element from the surface of the deposited alloy.
    Type: Grant
    Filed: February 13, 1991
    Date of Patent: September 1, 1992
    Assignee: International Business Machines Corporation
    Inventors: Francois M. d'Heurle, James M. E. Harper
  • Patent number: 4835114
    Abstract: This invention concerns a production method and a processing apparatus for semiconductor devices, as well as an evacuating apparatus used for the processing apparatus. According to this invention, since the evacuation system of pressure-reduction processing apparatus for conducting various wafer processings during production steps of semi-conductor devices is constituted only with oil-free vacuum pump, deleterious oil contaminations or carbonation products of oils produced from oils upon heating are not present in the pressure-reducing processing chamber as compared with conventional pressure-reducing processing apparatus using a vacuum oil pump as an evacuation pump and the production method of semiconductor devices using such apparatus.
    Type: Grant
    Filed: February 19, 1987
    Date of Patent: May 30, 1989
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Akihiko Satou, Tadao Kusaka, Shigeo Tomiyama, Kouzi Aoki, Ichiro Gyobu, Kimio Muramatsu, Hiroaki Sakamoto, Shinjiroo Ueda, Masahiro Mase, Takashi Nagaoka
  • Patent number: 4559217
    Abstract: A method for producing highly pure indium for subsequent utilization as a reaction component in the synthesis of polycrystalline, indium phosphide which includes the step of heating raw indium under vacuum in an open ended quartz ampoule to a temperature in excess of 850.degree. C. followed by the step of sealing the ampoule while simultaneously maintaining said vacuum within the interior of the ampoule.
    Type: Grant
    Filed: November 1, 1983
    Date of Patent: December 17, 1985
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Joseph A. Adamski