Abstract: In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.

Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

Abstract: In accordance with the present invention, a method for forming solder bumps begins with a wafer that has been patterned with bond pad areas. A plurality of distinct metal layers are then deposited over the wafer. Subsequently, solder is deposited by way of plating through a mask over the metal layers in the bond pad areas. After the removal of the mask, the metal layers outside of the soldered areas are etched using a dilute phosphoric acid solution, which includes phosphoric acid, acetic acid, hydrogen peroxide, and deionized water. By the use of this solution, the metal layers are removed without attacking the soldered areas. Thus, a pattern of solder bumps are formed. The metal layers include distinct layers of aluminum, nickel-vanadium, and copper. Alternatively, the aluminum layer is eliminated.

Abstract: A semiconductor layer undergoes isolation etching and gate recess etching, using a side wall insulating layer having the shape of a forward taper as a mask, by means of the anisotropic etching technique. The shape of the side wall of the semiconductor layer corresponds to that of the forward taper of the mask. The shape of the forward taper is always constant, irrespective of face orientation of crystal of the semiconductor layer. Since the taper angle of the side wall insulating layer can freely be set within a predetermined range in accordance with conditions, the taper angle of the semiconductor layer can be controlled. The design margin of an electrode wiring pattern is greatly improved. Since the side wall of a gate recess is stably formed in the shape of a forward taper, the side wall insulating layer can be formed on the surface of the forward taper and thus a gate electrode layer can be formed so as to have a T-shaped cross section. Therefore, the gate resistance can be greatly reduced.

Abstract: An electric interconnection method includes: a) providing two conductive layers separated by including material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: Disclosed are methods for reducing the degree of underetching and particulate contamination occurring during dry non-isotropic etching of a polycide layer on the surface of a silicon wafer maintained in a wafer holder wherein the backside of the holder is cooled with a stream of helium gas. Specifically, in the disclosed methods, dry non-isotropic etching of the polycide layer is conducted either in the absence of backside cooling or the helium gas flow utilized in backside cooling is maintained at a pressure of no more than 3 torr.

Abstract: According to the method of preventing the corrosion of metallic wirings of the present invention, aluminium alloy wirings are formed on the surface of a substrate with the use of photoresists, and the photoresists are then removed. Thereafter, HMDS (hexamethyl disilazine) serving as a surface-active agent or its derivative is supplied to the aluminium alloy wirings to form hydrophobic molecular layers on the lateral walls of the aluminium alloy wirings.

Abstract: A semiconductor device provided with an external connection terminal composed of a metal bump electrode. A first metal film is formed on the entire surface of the semiconductor device, a second metal film on the first metal film, and a third metal film on the second metal film. A resist film is selectively formed on the third metal film. A metal bump electrode is formed on the third metal film, at a portion at which the resist film is not present by electrolytic plating while using the third metal film as a conductive plating electrode and the resist film as a mask. The resist film is removed and the metal films are etched while using the metal bump electrode as a mask.

Abstract: A method of making a two-phase charge coupled device (CCD) includes forming a layer of a conductive material over and insulated from the surface of a body of a semiconductor material of one conductivity type having a channel region of the opposite conductivity type in the body and extending to the surface. Sections of a first masking layer are formed on the conductive material layer spaced along the channel region. A conductivity modifying dopant is implanted into the channel region through the spaces between the sections of the first masking layer. A layer of a second masking layer is formed over the sections of the first masking layer and on the surface of the conductive material layer in the spaces between the sections of the first masking layer. A layer of indium-tin oxide (ITO) is formed over the portions of the second masking layer which extend across the ends of the sections of the first masking layer, and a layer of carbon is formed on the second masking layer between the ITO layers.

Abstract: A method for cleaving semiconductor devices along planes accurately positioned. Resist is applied to a major surface of the semiconductor device and a mask is projected upon the resist covered major surface. The mask is opaque in those regions in which no cleave is desired. Following the exposure of the resist, the removal of the mask and the development of the resist, an ion beam is positioned incident upon the semiconductor surface such that ion beam etching occurs in the areas in which no resist covers the semiconductor structure. Once a sufficient depth is etched in the areas not covered with resist such that the strength of the semiconductor structure in those areas is significantly less than in those areas covered by resist, the ion beam etching process is ended and the resist is stripped from the semiconductor structure. Subsequently, force is applied within the area in which the ion beam etching occurred to cleave the semiconductor structure within that region.

Abstract: The present invention provides a method of forming fuse ribbons between conductive layers on a semiconductor device. The formation of these fuse ribbons may be at different levels of multiple level integrated circuits. The fuse ribbons are formed in a more precise manner than can be obtained conventionally. Resistance control can be easily achieved and significant decreases in dimensions and the use of less fuse material can be achieved.

Abstract: A method for interconnecting layers in a semiconductor device is disclosed. The device includes a lower conductive layer formed by capping a second conductive layer on a first conductive layer, a contact window formed in an inter-insulating layer on the lower conductive layer, and an upper conductive layer connected to the lower conductive layer through the contact window. The contact window is formed by removing a portion of the inter-insulating layer where the contact will be formed using a first etching gas, and removing a portion of the second conductive layer where the contact will be formed using a second etching gas. The contact resistance becomes uniform by preventing the formation of a non-volatile mixture in the contact window, and the reliability of the device is improved by planarizing the surface of the lower conductive layer.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: An anisotropic reactive ion etching of an aluminum metal film of a semiconductor device. The device is placed in a reactive ion etcher using a CF.sub.4, Cl.sub.2 and BCl.sub.3 gas mixture to anisotropically etch the aluminum metal film layer wherein the gas mixture has a ratio of CF.sub.4 :Cl.sub.2 such that the aluminum etch rate increases as the amount of CF.sub.4 relative to Cl.sub.2 increases.

Abstract: A process of forming an interconnection layer of polysilicon in a contact hole formed in an interlayer insulating film comprises opening the contact hole, depositing doped and nondoped polysilicon films in sequence, and etching back the polysilicon films by the reactive ion etching technique with at least one carbon fluoride gas to obtain the interconnection layer buried in the contact hole.

Abstract: A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.

Abstract: A method of producing patterned epitaxial silicon films and devices fabricated thereby is described. The method forms a first layer of a refractory material on a substrate and pattern delineates the first layer. Silicon is then deposited at a temperature within the range between 400 degrees C. and 700 degrees C. and the polycrystalline material that forms is removed.

Abstract: Improvements to graphoepitaxy include use of irradiation by electrons, ions or electromagnetic or acoustic radiation to induce or enhance the influence of artificial defects on crystallographic orientation; use of single defects; and use of a relief structure that includes facets at 70.5 and/or 109.5 degrees.

Abstract: A bump electrode structure of a semiconductor device comprises an electrode pad formed of an aluminum alloy, an insulating oxide layer covering only the peripheral edge portion of the electrode pad, an under-bump layer formed of an alloy of titanium and tungsten, and a bump electrode formed of gold. The titanium-tungsten alloy functions both as a barrier metal and as a bonding metal. The bump electrode rises substantially straight from the bonding surface of the under-bump layer, and its top portion has an area only substantially equal to that of the electrode pad. Fine V-shaped grooves are formed on the top surface of the bump electrode by anisotropic etching. Thus, the semiconductor device with fine electrode pad pitches is provided with a high-reliability bump electrode structure which ensures sufficient bonding strength between internal and external electrodes.

Abstract: A method of manufacturing a semiconductor device in which a portion of a monocrystalline silicon layer protruded from a surface of an insulating member is polished up to the surface by a chemical-mechanical polishing is disclosed. A polycrystalline silicon layer and a leveling material are formed in sequence on the protruded portion of the monocrystalline silicon layer and on an exposed part of the surface of the insulating member, and a reactive ion etching and the chemical-mechanical polishing are carried out.

Abstract: A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.

Abstract: The radiation hardened NFET and process of the subject Methods and Structures for Improving Radiation Tolerance of Silicon Gate CMOS/Silicon on Sapphire Devices utilizes boron edge doping of a silicon epi island on sapphire at the island opposed edges in the region which will be the P-doped region of the finished transistor. Multiple boron ion implants are made into the silicon adjacent to the active region and driven-in to provide a uniform edge doping. Alternatively, a furnace containing a source of boron vapor and the sapphire wafer is used to dope the island edges at high temperatures.

Abstract: Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces.

Abstract: The present invention is a contact etch method which simultaneously smoothes a reflowed oxide profile so that separate phanarization photoresist coat and etch steps are unnecessary. This method is characterized in that it is fast, uses only one photoresist mask layer, etches contacts to poly and to substrate simultaneously, is done entirely with plasma etch technology in a single reactor, and builds up less polymer in the plasma reactor. The novel method eliminates a coat and an etch step, improving yield and reducing fabrication time. Lower polymer buildup means higher yields due to a cleaner process, and less downtime for reactor chamber cleaning.

Abstract: An oxide sidewall spacer is formed on the sidewalls of a gate prior to forming the body region of a DMOS transistor. An ion implantation or diffusion process is then conducted to form the body region, where the gate and the oxide sidewall spacer together act as a mask for self-alignment of the body region. After a drive-in step to diffuse the impurities, the body region will extend only a relatively short distance under the gate due to its initial spacing from the edge of the gate. After the body region is formed, the oxide sidewall spacer is removed, and impurities to form the source region are implanted or diffused into the body region and driven in. Since the extension of the body region under the gate is limited by the oxide sidewall spacer, the channel region between the edge of the source region and the body region under the gate may be made shorter resulting in the channel on-resistance of the transistor being reduced.

Abstract: A method of manufacturing semiconductor devices comprising at least a reactive ion etching step of a so-called substrate formed by semiconductor compounds having the general formulae Ga.sub.1-x As.sub.x In.sub.1-y P.sub.y, in which formulae x and y are the concentrations and lie between 0 and 1, this method comprising for carrying out this etching step a masking system of the said substrate cooperating with a flow of reacting gases, characterized in that the masking system is formed by a first metallic layer of titanium (Ti) of small thickness, on which a second metallic layer of nickel (Ni) is disposed having a thickness of about ten times larger, and in that the flow of reacting gases is formed by the mixture of the gases Cl.sub.2 /CH.sub.4 /H.sub.2 /Ar, in which mixture Cl.sub.2 is present in a quantity of about a quarter of the quantities of CH.sub.4 and Ar, as far as the partial pressures in the etching chamber are concerned.Application: Manufacture of optoelectronic devices of III-V materials.

Abstract: On a semiconductor substrate (38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated with the remaining portions of the contact structure being masked by selective oxidation.

Abstract: A method for separating laser diodes. The diodes are monolithically produced from a semiconductor substrate wafer which through an epitaxy process has been provided with a layer sequence suitable for laser operation. First, the semiconductor substrate wafer is covered with a first mask which defines the interspaces between the mirrors of adjacent laser diodes. Then the mirror surfaces are etched out of the semiconductor substrate wafer. Thereafter, the wafer is covered with a second mask for defining separation trench areas between the mirror surfaces of adjacent laser diodes and for protecting the remaining wafer parts. Then, separation are etched into the trench area. Finally, the laser diodes are separated by breaking the wafer along the trenches. In a preferred embodiment, the wafer thickness is at most twice the distance between the mirror surfaces of adjacent laser diodes and the trench depth is at least one fourth of the wafer thickness.

Abstract: A method for reducing birdbeaks formed during a planox process is disclosed. On a silicon substrate (1), oxide (2) and nitride (3) are formed. The oxide and nitride are then selectively etched using a single plasma having high selectivity with respect to silicon and a photoresist mask (4). The high selectivity toward silicon is achieved by use of a CHF.sub.3 +CO.sub.2 plasma under conditions of 30:1 oxide/silicon selectivity. Field oxide regions (5) with reduced birdbeaks can then be formed.

Abstract: A method for forming a multilayer integrated circuit is described wherein the resultant top surface thereof is substantially planar. The method involves first forming a layer of connecting metallization on integrated circuit components formed in a conventional manner. Then a first layer of dielectric is formed on the metallization layer. Next a second dielectric layer is formed on the first dielectric layer. Via areas are then formed by etching the first and second dielectric layers in order to expose selected areas of the first metallization layer, and filled with metal to form vias. A layer of photoresist is deposited on all surfaces. Lastly, the surface is etched using an etchant that etches dielectric, metal and photoresist at substantially the same rate such that said vias are exposed and a planar top surface produced.

Abstract: A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

Abstract: A process for forming electrodes for semiconductor devices having a semiconductor substrate and an electrically conductive portion covered and protected by an electrically insulating coating. The process including the steps of forming an electrically conductive film on the electrically insulating coating, forming an electrode to be connected to an external circuit on the electrically conductive film at a position overlying the electrically conductive portion by exposing portions of the electrically insulating coating and the first electrically conductive film to a converged ion beam, electrically connecting the electrode to the exposed portions of the electrically conductive film, and removing the portions of the electrically conductive film not covered by the electrode. As a result, the likelihood of breakdown of the internal circuit of the semiconductor device connected to the electrically conductive portion while the electrode is being formed in greatly reduced.

Abstract: Disclosed is a method of producing a compound semiconductor device comprising an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.

Abstract: A process for manufacturing GaAs FET's having refractory metal gates provides for reducing the size of the gate relative to a mask by an etch sequence which results in precisely controlled and repeatable self-limited undercutting of the mask. A reactive ion etch of the refractory metal in a CF.sub.4 O.sub.2 plasma containing an inert gas provides the self-limiting undercut at a pressure in the range of 175-250 mTorr when the power is less than 0.15 W/cm.sup.2. Preceeding the undercut, an anisotropic RIE in a CF.sub.4 plasma can be employed to clear unmasked areas of the refractory metal and an initial sputter cleaning in argon improves the quality of the initial etch.

Abstract: The provision of an intermediately doped transition region between respective n+ implanted source and drain regions in a GaAs FET and the lightly doped channel region under the gate permits device optimizaiton for low source and drain resistance in EFET's while employing the same n+ implant for source and drain optimization in DFET's while also maintaining the same n+ to gate contact spacing in both device types. Additionally, in high frequency operation of an asymmetrically implanted FET, the tapered doping profile offered by the transition region on the drain side of the gate provides high transconductance without sacrificing high output resistance. The transition region can be provided in a self-aligned implant employing dielectric sidewall spacers and the n+ implant can be self-aligned with an etch mask employed in gate definition.

Abstract: A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.

Abstract: An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penet

Abstract: The invention pertains to a method for the selective etching of a surface layer which is automatically stopped at a subjacent layer.According to the invention, a first layer of a material containing gallium is selectively etched with respect to a second layer containing aluminium by reactive ion etching in the presence of a pure freon plasma C Cl.sub.2 F.sub.2. At low pressures (0.5 to 2.5 pascals), the etching is anisotropic and makes it possible to etch the gate recess of a field effect transistor. At a higher pressure (6 to 10 pascals), the etching is isotropic and makes it possible to sub-etch the first layer.Application to the manufacture of field effect transistors made of group III-V materials, with low access resistances.

Abstract: The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination.

Abstract: A current source MOSFET is fabricated by forming a trench (36) in an n++ drain (source) region (32) and extending below the trench (36). A gate oxide layer (40) is disposed on the sidewalls of the trench (36) and a conductive region (38) formed in the bottom of the trench (36). A gate-to-source (gate-to-drain) contact (49) is then formed in the trench (36) and then a drain (source) contact (58) formed. The vertical gate structure defines a vertical channel region on all sides of the trench (36) to allow a wider devive to be fabricated in a smaller overall silicon area.

Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.

Abstract: A multiple meltback procedure is described for removing gross contaminants and thermal degradation from InP-containing surfaces. Prior to LPE growth on an InP substrate, the substrate surface is brought into contact briefly (.ltorsim.1 sec) with an essentially pure In melt and is then brought into contact with a slightly undersaturated In/P melt. A similar triple meltback procedure is described for use prior to LPE growth over a mesa (e.g., in the fabrication of buried heterostructures).

Abstract: Edge conduction in a silicon-on-sapphire transistor is minimized by a process which permits precise doping of the edge channel regions of the transistor. The silicon island (19) containing the transistor (24) is precisely doped around its edges by ion implanting an epitaxial silicon layer (13) on a sapphire substrate (11), with an oxide mask (29) covering, with the exception of a narrow peripheral edge (37), the portion of the silicon which is eventually to form the island (19') on which the transistor is to be constructed. The mask (29) is then expanded by the addition of a sleeve (43) to cover the additional peripheral edge region (37) in the silicon. When the silicon is subsequently etched using the expanded oxide pattern 45 as a mask, the periphery of the remaining silicon will be doped to a predetermined depth (37) corresponding to the width of the sleeve (43).

Abstract: The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.

Abstract: A semiconductor device in which a film of an insulator a conductor is closely deposited in a groove formed in a semiconductor substrate or an insulating or conductor layer thereon to planarize the surface thereof.A semiconductor device manufacturing process in which a specimen is selectively etched away through using a resist pattern as a mask, a pattern forming film is deposited by a plasma deposition technique on the specimen, and the resist film is removed, whereby the pattern forming film closed fills up a groove formed by etching to provide a planarized surface.

Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels.

Abstract: A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer.