Removal Of Substrate Patents (Class 148/DIG135)
  • Patent number: 6060373
    Abstract: A plurality of pad electrodes are formed on a first surface of an IC wafer, and a solder layer is formed on each of the pad electrodes. The first surface of the IC wafer including solder layers is coated with a flux layer, and solder layers are reflowed to round each of the solder layers, thereby forming each solder layer into a solder bump. An adhesive tape is adhered on the flux layer, and a second surface opposite to the first surface of the IC wafer is ground to form a flip chip semiconductor device.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: May 9, 2000
    Assignee: Citizen Watch Co., Ltd.
    Inventor: Masaru Saitoh
  • Patent number: 6025060
    Abstract: A method and apparatus for creating unique gemstones is provided. The method comprises the steps of optically contacting the gemstones of interest followed by a heat treatment of the composite gemstone. The heat treatment step increases the bond strength and therefore the resistance of the bond to reversal. In one aspect of the invention, a composite gem is fabricated by bonding a naturally occurring gem to an artificial gem to form a single composite gemstone of large size that outwardly appears to be a single natural gem. The composite gem may be fabricated at a fraction of the cost of a natural stone of the same size. In another aspect of the invention, an intensely colored natural stone is bonded to a colorless or lightly colored artificial stone. This composite retains the intense color associated with the natural stone while enjoying the brilliance, depth, and size resulting from the combination of stones.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: February 15, 2000
    Assignee: Onyx Optics, Inc.
    Inventor: Helmuth E. Meissner
  • Patent number: 6004860
    Abstract: An SOI substrate and a method for fabricating the same are provided to sharpen the departing angle at the circumference of the active substrate, and provide the active substrate with a uniform thickness. An attached wafer of the present invention is formed by processing the upper side of the base substrate so that its thickness increases from the center to the circumference, and attaching the active substrate to the processed side of the base substrate. The unattached portion of the attached wafer is removed. Then mirror processing is performed to provide the active substrate with a substantially uniform thickness along the processed side of the base substrate.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: December 21, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
  • Patent number: 5932048
    Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100.degree. C.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: August 3, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroshi Furukawa, Hirotaka Kato, Hiroaki Yamamoto, Kazuaki Fujimoto
  • Patent number: 5897333
    Abstract: In an improved method for manufacturing an integrated composite semiconductor device according to the present invention, a semiconductor-based stop-etch layer having holes therein at selected sites is disposed over the epoxy or other flowable hardener used in flip-chip bonding. The hardener underneath the openings in the stop-etch layer is subtantially removed via a dry etch applied therethrough, exposing desired structure, such as bonding pads, formerly covered by the hardener. The epoxy underneath the stop-etch layer is substantially preserved.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: April 27, 1999
    Assignee: Lucent Technologies, Inc.
    Inventors: Keith Wayne Goossen, James A. Walker
  • Patent number: 5869354
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: February 9, 1999
    Assignee: Elm Technology Corporation
    Inventor: Glenn Joseph Leedy
  • Patent number: 5866436
    Abstract: A method of improving the yield and achievable tolerances of integrated circuits by obtaining surface measurements of non-reflective soft mounting films used in integrated circuit manufacture. The non-reflective surface of a mounting film is first rendered reflective by applying a reflective wafer atop the film surface. This reflective test wafer, which is highly plano-parallel and preferably has a thickness less than that of the ultimate product wafer, is applied to the mounting film to be measured via direct pressure whereby the reflective test wafer conforms to and takes on the surface characteristics and contours of the film. The formerly non-reflective surface of the mounting film is thereby rendered effectively reflective and thus susceptible to optical profiling and graphical and numerical recordation by a computerized interferometer in accordance with well-known techniques.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: February 2, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Anton Johann Miller
  • Patent number: 5846638
    Abstract: A method of forming defect-free permanent bonds without the use of adhesives as well as devices formed by this method is disclosed. In general, the disclosed process allows similar or dissimilar crystalline, vitreous or dense polycrystalline ceramic, metallic or organic polymeric components to be first joined by optical contacting and then heat treated to stabilize the bond. The heat treatment can be performed at a low enough temperature to prevent interdiffusion between species, thus insuring that the bond is not subjected to excessive mechanical stresses and that the materials do not undergo phase changes.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: December 8, 1998
    Assignee: Onyx Optics, Inc.
    Inventor: Helmuth E. Meissner
  • Patent number: 5846844
    Abstract: A nitrogen-group III compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0, and a method for producing the same comprising the steps of forming a zinc oxide (ZnO) intermediate layer on a sapphire substrate, forming a nitrogen-group III semiconductor layer satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0 on the intermediate ZnO layer, and separating the intermediate ZnO layer by wet etching with an etching liquid only for the ZnO layer.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: December 8, 1998
    Assignees: Toyoda Gosei Co., Ltd., Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu
    Inventors: Isamu Akasaki, Hiroshi Amano, Kazumasa Hiramatsu, Theeradetch Detchprohm
  • Patent number: 5776789
    Abstract: A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions, a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region, and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated. The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: July 7, 1998
    Assignee: Fujitsu Limited
    Inventor: Shunji Nakamura
  • Patent number: 5769991
    Abstract: A method of wafer bonding with less elongation and contraction of wafers at the time of and after the bonding of the wafers is disclosed. In the method of wafer bonding, wafers are bonded together with sticking force of their surfaces to form a bonded wafer. The bonding is done by selecting the pressure of the gas between the wafers to be lower than the atmospheric pressure, for instance, and also selecting the kind of gas between the wafers to H.sub.2, for instance.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: June 23, 1998
    Assignee: Sony Corporation
    Inventors: Yoshihiro Miyazawa, Yasunori Ohkubo
  • Patent number: 5755914
    Abstract: A semiconductor substrate comprises a plurality of substrates to be bonded, wherein a bond promotion layer into which silicon atoms are implanted is provided in an interface between the substrates to be bonded, and the substrates are bonded to each other with the interposition of the bond promotion layer.
    Type: Grant
    Filed: July 5, 1996
    Date of Patent: May 26, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 5753529
    Abstract: An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: May 19, 1998
    Assignee: Siliconix incorporated
    Inventors: Mike F. Chang, King Owyang, Fwu-Iuan Hshieh, Yueh-Se Ho, Jowei Dun
  • Patent number: 5747353
    Abstract: A method of making a surface micro-machined accelerometer using a silicon-on-insulator (SOI) wafer structure. Both the acceleration (or deceleration) sensor and associated signal conditioning circuitry are monolithically fabricated on the same substrate. The top silicon layer of the SOI wafer is used as the sensing member, corresponding to the movable, common electrode of a differential capacitor pair. The components of the signal conditioning circuitry are fabricated in the SOI layer using standard SOI processing techniques. Because the top silicon layer is single crystal silicon, it does not suffer from the stress related warping common with polysilicon members. In addition, because the method described is compatible with bipolar, BiCMOS, or CMOS process flows, it may be used to fabricate faster and lower noise level signal conditioning circuitry than can be obtained using current techniques for making monolithic accelerometers.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: May 5, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Rashid Bashir, Abul E. Kabir
  • Patent number: 5728591
    Abstract: A process for manufacturing a light valve device comprises forming a transparent insulating thin film layer on a surface of a semiconductor substrate, and forming a single crystal semiconductor thin film on a surface of the transparent insulating thin film layer. A portion of the single crystal semiconductor thin film is then removed and at least one pixel electrode is formed on the transparent insulating thin film layer at a region where the single crystal semiconductor thin film has been removed. A driving unit is then formed in the single crystal semiconductor thin film. Thereafter, a carrier substrate is laminated using an adhesive on the surface of the semiconductor substrate at a region corresponding to the pixel electrode and the driving unit. The semiconductor substrate is then removed to expose a surface of the transparent insulating thin film layer and through-holes and a metal film are formed on the exposed surface thereof.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 17, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Kunihiro Takahashi, Yoshikazu Kojima, Hiroaki Takasu, Nobuyoshi Matsuyama, Hitoshi Niwa, Tomoyuki Yoshino, Tsuneo Yamazaki
  • Patent number: 5723353
    Abstract: An acceleration sensor is composed of a three-layer system. The acceleration sensor and conductor tracks are patterned out of the third layer. The conductor tracks are electrically isolated from other regions of the third layer by recesses and electrically insulated from a first layer by a second electrically insulating layer. In this manner, a simple electrical contacting is achieved, which is configured out of a three-layer system.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: March 3, 1998
    Assignee: Robert Bosch GmbH
    Inventors: Horst Muenzel, Dietrich Schubert, Alexandra Boehringer, Michael Offenberg, Klaus Heyers, Markus Lutz
  • Patent number: 5719069
    Abstract: A method for concurrently forming a micromachine element and an integrated circuit device on the same substrate, such that fabrication of the micromachine element and the circuit device requires a minimal number of processing steps. The method is adapted for forming sensing devices, such as accelerometers and pressure sensors, which utilize a small micromachine element, such as a bridge, cantilevered beam, suspended mass, membrane or capacitive element that is supported over a cavity formed in the silicon substrate. Piezoresistors used to detect the deflection of the micromachine element are formed simultaneously with elements of the integrated circuit devices, such that a minimal number of processing steps are required.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: February 17, 1998
    Assignee: Delco Electronics Corporation
    Inventor: Douglas Ray Sparks
  • Patent number: 5702963
    Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates Using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: December 30, 1997
    Assignee: Kopin Corporation
    Inventors: Duy-Pach Vu, Brenda Dingle, Ngwe Cheong
  • Patent number: 5698474
    Abstract: Emission microscopy testing of semiconductor integrated circuits is accomplished from the back side of a packaged die or a wafer but selectively milling the back surface using high speed (e.g., 40,000-60,000 rpm) milling tool having a 150 grit 0.125 inch diameter laterally translated at 3 inches per minute and taking cuts up to approximately 0.00025 inch (6 microns). In milling a packaged die, a trench is first milled in the molding material holding the die in the package and surrounding the die so that the tool can momentarily pause to switch directions off the die face. The die or wafer can be thinned to less than 200 microns for the emission microscopy testing.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: December 16, 1997
    Assignee: Hypervision, Inc.
    Inventor: Daniel T. Hurley
  • Patent number: 5698452
    Abstract: A method and apparatus are disclosed for an integrated photonic device. A transparent non-imaging optical director having a top and a bottom surface is integrated, at its bottom surface, with a photonic device. The bottom surface is approximately equal in area to the active area of the photonic device. The top surface of the director is larger than its bottom surface. The top and bottom surface are connected by a waveguiding region. The geometry and refractive index of the non-imaging optical director are controlled so that the light entering the director is preferably totally internally reflected. Substantially all optical energy of an optical signal received at the top surface of the non-imaging optical director will be directed to its bottom surface, and then to the integrated photonic device. Where the photonic device is an optical source, substantially all optical energy emitted that is received by the bottom surface is directed to the top surface.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: December 16, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Keith Wayne Goossen
  • Patent number: 5696034
    Abstract: A method for producing a semiconductor substrate in which no autodoping occurs and slip dislocations in the substrate are reduced. The method involves forming a silicon nitride film on the backside of an n.sup.- -silicon substrate, epitaxially growing an n.sup.+ -buffer layer and a p.sup.+ -layer on the front side of the n.sup.- -silicon substrate, and decreasing the thickness of the n.sup.- -silicon substrate from the backside.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: December 9, 1997
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masatake Katayama, Isao Moroga, Isao Shirai, Youichi Kumaki, Akio Kasahara
  • Patent number: 5674758
    Abstract: Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 7, 1997
    Assignee: Regents of the University of California
    Inventor: Anthony M. McCarthy
  • Patent number: 5668045
    Abstract: A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: September 16, 1997
    Assignee: SiBond, L.L.C.
    Inventors: David I. Golland, Robert A. Craven, Ronald D. Bartram
  • Patent number: 5650353
    Abstract: SOI (silicon-on-insulator) substrates are efficiently produced by a method which comprises superposing and bonding at least three single crystal silicon wafers through the medium of a SiO.sub.2 film formed on the surface of each of the wafers and cutting the bonded wafers along planes perpendicular to the direction of superposition thereof. The cutting can be infallibly attained with high dimensional accuracy without entailing such adverse phenomena as the vibration of the blade of a cutting tool by providing at the portions destined to be cut the grooves for guiding the blade of the cutting tool in advance of the cutting work.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: July 22, 1997
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Katsuo Yoshizawa, Tsutomu Sato, Kiyoshi Mitani, Masatake Katayama
  • Patent number: 5647932
    Abstract: The following steps are performed when processing electronic components such as piezoelectric devices. At Step 1 inter-atom bond is created between a functional member such as a quartz crystal plate and a first substrate, and the functional member and the quartz crystal plate are directly joined together. At Step 2, the functional member and a second substrate are fixed together with an adhesive agent or by a direct bond. At Step 3, the first substrate is removed chemically or mechanically, with said functional member and said second substrate still being joined together. A step of polishing said functional member for the adjustment of thickness thereof may be done between Step 1 and Step 2. For example, a silicon dioxide thin film may be provided between the functional member and the first substrate. Since no adhesive layer exists between the functional member and the first substrate, this improves the degree of plane of the functional member when joined to the first substrate.
    Type: Grant
    Filed: February 14, 1996
    Date of Patent: July 15, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Taguchi, Kazuo Eda, Akihiro Kanaboshi, Tetsuyoshi Ogura, Yoshihiro Tomita
  • Patent number: 5646066
    Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing a common electrode layer 31 over the thermal isolation trenches 22; depositing an optical coating 26 above the common electrode layer 31; mechanically thinning the substrate to expose the trench filler 24; etching to remove the trench filler 24 in the bias contact area; depositing a contact metal 34 on the backside of the substrate 20, wherein the contact metal 34 connects to the common electrode layer 31 at bias contact areas 34 around a periphery of the thermal isolation trenches; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. Bias contact vias 23 may be formed in the bias contact areas and then filled with bias contact metal 49.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: July 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Steven N. Frank, James F. Belcher, Charles E. Stanford, Robert A. Owen, Robert J. S. Kyle
  • Patent number: 5646067
    Abstract: A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: July 8, 1997
    Assignee: Harris Corporation
    Inventor: Stephen Joseph Gaul
  • Patent number: 5643805
    Abstract: A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: July 1, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Ohta, Hideo Miura, Hiroo Masuda, Yoichi Tamaki, Takahide Ikeda, Asao Nishimura, Takashi Hashimoto
  • Patent number: 5643821
    Abstract: A buried silicide layer 111 in a bonded wafer 105 makes ohmic contact to a heavily doped buried layer 125. A dopant rapidly diffuses through the silicide layer and into the adjacent semiconductor to form the buried layer.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: July 1, 1997
    Assignee: Harris Corporation
    Inventor: James Douglas Beasom
  • Patent number: 5633209
    Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 27, 1997
    Assignee: ELM Technology Corporation
    Inventor: Glenn J. Leedy
  • Patent number: 5622586
    Abstract: Method of fabricating a device made of a thin diamond film having a thickness of less than 10 .mu.m which is difficult to handle. The method is initiated by forming a thin diamond film on a silicon substrate to a thickness of about 5 .mu.m by chemical vapor deposition. Then, paraffin is applied. The substrate is removed with hydrofluoric acid. Thus, the diamond film is retained on the paraffin that is made to act as a base. A required circuit is formed on the surface of the diamond film. Finally, the paraffin is removed. In this way, a device using the diamond film is completed. This structure can be used as a device for measuring thermal effect, using a thin diamond film. For example, the structure can be used for fabrication of a flowsensor.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: April 22, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Rimantas Vaitkus, Takashi Inushima, Masaya Kadono
  • Patent number: 5602054
    Abstract: A dielectrically isolated island architecture in which the island is contoured inwardly to form one or more projections that penetrate a well separating two regions in the island to assure that the two regions will be electrically isolated without additional processing steps.
    Type: Grant
    Filed: September 21, 1994
    Date of Patent: February 11, 1997
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 5597766
    Abstract: Method for detaching chips in the silicon layer of a SOI substrate, wherein trenches are etched between the chips down to the insulating layer of the SOI substrate. Spacers for the passivation of SiO.sub.2 layers of the chips are produced. Finally, the chips are detached by etching the insulating layer off.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: January 28, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventor: Franz Neppl
  • Patent number: 5595933
    Abstract: A low-power cathode can be obtained by arranging it on a substrate (1), preferably of silicon, which is entirely or partly removed at the location of the emissive structure (11) by means of, for example, anisotropic etching. Because of its low power, the cathode is particularly suitable for multi-beam applications.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: January 21, 1997
    Assignee: U.S. Philips Corporation
    Inventor: Willem L. C. M. Heijboer
  • Patent number: 5593915
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A silicon oxide film having a predetermined film thickness is formed on a smooth major surface of a first silicon substrate of a first conductivity type having a first region wherein a power transistor is to be formed. The major surface of the first silicon substrate is bonded to a smooth major surface of a second silicon substrate having one of the first conductivity type and a second conductivity type. The other surface of the second silicon substrate bonded to the first silicon substrate is polished to form a silicon layer having a predetermined film thickness and a second region wherein a transistor constituting a control circuit for driving the power transistor is to be formed. The silicon layer and the silicon oxide film are removed from a predetermined portion in the first region.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: January 14, 1997
    Assignee: NEC Corporation
    Inventor: Tsukasa Ohoka
  • Patent number: 5591678
    Abstract: A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58') therein that can be electrically interconnected to the microelectronic circuit element (50).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 7, 1997
    Assignee: HE Holdings, Inc.
    Inventors: Joseph J. Bendik, Gerard T. Malloy, Ronald M. Finnila
  • Patent number: 5585304
    Abstract: A semiconductor wafer is comprised of a transparent layer interposed between a thin silicon layer and a thick silicon layer. Silicon islands are formed from the thin silicon layer on the transparent layer. Device elements are formed in the silicon islands. Thereafter, the thick silicon layer which is a support layer is etched away to form a transparent region on the wafer. The wafer is constructed to avoid elimination or destruction of the transparent layer during the course of formation of the silicon islands and during the course of etching of the rear thick silicon plate. The transparent layer is comprised of a silicon nitride film or a silicon carbide film. Alternatively, the transparent layer is comprised of a silicon oxide film covered by a silicon nitride film or a silicon carbide film on one or both of the upper and lower faces of the silicon oxide film.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: December 17, 1996
    Assignees: Agency Industrial Science, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Kunihiro Takahashi, Hiroaki Takasu, Yoshikazu Kojima, Hitoshi Niwa, Nobuyoshi Matsuyama, Yomoyuki Yoshino, Masaaki Kamiya
  • Patent number: 5580802
    Abstract: A silicon-on-insulator (SOI) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, channel and drain surrounded by a top gate and a buried bottom gate, the latter of which also has application for other buried structures and is formed on a bottom gate dielectric which was formed on source, channel and drain semiconductor layer of an SOI wafer. After forming a planar bottom insulator layer on the bottom gate and bottom gate dielectric, the SOI wafer is flip-bonded onto an oxide layer of a bulk silicon wafer, thereby encapsulating the buried bottom gate electrode in insulating oxide, after which the SOI substrate and the etch-stop SOI oxide layer are removed to expose the SOI semiconductor layer which is processed to form the source, drain and channel in a mesa structure on which is deposited a top gate dielectric, a top gate, and top gate insulator as well as four conductors for connecting to the source, drain, top gate and bottom gate.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: December 3, 1996
    Inventors: Donald C. Mayer, Kenneth P. MacWilliams
  • Patent number: 5563084
    Abstract: A method of making a three dimensionally integrated circuit by connecting first and second substrates (1;7) provided with devices in at least one layer in at least one surface in each of said substrates. An auxiliary substrate is connected to the one surface of one of said substrates which is then reduced in thickness from its opposite surface. The auxiliary layer with the devices thereon is then separated into individual chips which after having been found to be functioning are aligned and mounted in a side-by-side arrangement on said one surface of said first substrate. Electrical connection are formed between the devices of the mounted chips and the devices in the first substrate.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: October 8, 1996
    Assignee: Fraunhofer-Gesellschaft zur F orderung der angewandten Forschung e.V.
    Inventors: Peter Ramm, Reinhold Buchner
  • Patent number: 5547886
    Abstract: In an SOI substrate including a single-crystal Si substrate (1b), an oxide film (20) and a single-crystal Si substrate (1a), there is formed an stepped wall surface (8) by selective removal of the single-crystal Si substrate (1a) to provide a thick oxide film (5) on the stepped wall surface (8). When a VDMOS (100) is formed in an active region of the single-crystal Si substrate (1b) above which the single-crystal Si substrate (1a) is absent and an MOS (101) having a thin oxide film (22) is formed in the single-crystal Si substrate (1a), the oxide film (5) is not damaged because it is thick. The thickness of the single-crystal Si substrate (1a) enables to be designed in accordance with the required thickness of the MOS (101).
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: August 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masana Harada
  • Patent number: 5540785
    Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Bernard S. Meyerson, Robert Rosenberg
  • Patent number: 5532173
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: July 2, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, William Waters, Joseph P. Lorenzo, Stephen Spaziani
  • Patent number: 5514235
    Abstract: A method is disclosed for obtaining bonded wafers of SOI type, where impurity redistribution in the bulk of the wafers is suppressed and the bonding strength between the wafers is substantially higher compared with that in the prior art. This is accomplished by forming a thermally grown oxide layer on the surface of the thinner one(bond wafer) of two monocrystalline silicon wafers having thicknesses different from each other by more than 50 .mu.m; then superposing the thinner wafer onto the other thicker wafer(base wafer); and finally conducting at least two heat treatments of the wafers at temperatures selected in the range of under 900.degree. C. for a period of time selected in the range of from 0.5 min. to 120 min.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: May 7, 1996
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kiyoshi Mitani, Masatake Katayama
  • Patent number: 5510276
    Abstract: A process for producing a pressure transducer or sensor using the silicon-on-insulator method is provided. The process includes the following steps: (a) producing a monocrystalline silicon film (44) on a silicon substrate (6) at least locally separated from the latter by an insulating layer (42), (b) producing an opening (24) in the silicon film down to the insulating layer, (c) partially eliminating the insulating layer via the opening in order to form the diaphragm in the silicon film, and (d) resealing the opening (26).
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: April 23, 1996
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Diem, Marie-Therese Delaye
  • Patent number: 5496764
    Abstract: An insulating layer is formed over a first substrate. Trenches are formed within a second substrate, and those trenches are filled with an insulating layer. The two substrate are bonded at their insulating layers. The portion of the second substrate away from the trenches is removed to form semiconductor regions over the insulating layer of the first substrate. Embodiments of the present invention allow better thickness control for SOI regions and lower leakage current compared to SOI layers that use LOCOS-type field isolation.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: March 5, 1996
    Assignee: Motorola, Inc.
    Inventor: Shih-Wei Sun
  • Patent number: 5496743
    Abstract: A Novel method of making a semiconductor device (e.g., a HBT) is disclosed. A semiconductor body that comprises bulk semiconductor material and epitaxial semiconductor material on the bulk material is processed by carrying out a first sequence of processing steps on the epitaxial material. The sequence comprises forming at least first and second contact means on the epitaxial material. The resulting intermediate body is mounted, epitaxial material down, on a carrier body (e.g., a Si wafer with integrated circuitry thereon), such that the first and second contact means are electrically connected to, respectively, third and fourth contact means on the carrier body. Mounting is accomplished, exemplarily, by means of anisotropically conductive adhesive means. Subsequent to mounting of the intermediate body on the carrier body, a second sequence of processing steps is carried out on the intermediate body.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: March 5, 1996
    Assignee: AT&T Corp.
    Inventor: Serge Luryi
  • Patent number: 5494849
    Abstract: A single-etch stop process for the manufacture of silicon-on-insulator substrates. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1.times.10.sup.18 boron atoms/cm.sup.3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: February 27, 1996
    Assignee: Si Bond L.L.C.
    Inventors: Subramanian S. Iyer, Emil Baran, Mark L. Mastroianni, Robert A. Craven
  • Patent number: 5494833
    Abstract: An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: February 27, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Eric A. Martin, Kenneth Vaccaro, Joseph P. Lorenzo
  • Patent number: 5480832
    Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: January 2, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shoji Miura, Takayuki Sugisaka, Atsushi Komura, Toshio Sakakibara
  • Patent number: RE36890
    Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: October 3, 2000
    Assignee: Motorola, Inc.
    Inventors: Raymond C. Wells, Frank T. Secco d'Aragona