Abstract: An integrated circuit inverted thin film resistor structure and method of manufacture having interconnect defining resistor contacts and leads resident within and coplanar with a supporting layer, resistive material uniformly overlaying the supporting layer and contacts, the resistive material diffused into the resistor/interconnect contact region.

Abstract: A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer.

Abstract: An epitaxial pinched resistor includes a semiconductor substrate of a first conductivity type having a surface on which an epitaxial layer of a second conductivity type grown. An up isolation region of the first conductivity type is diffused from the surface of the semiconductor substrate up into the epitaxial layer. A first down isolation region of the first conductivity type is diffused down into the epitaxial layer and overlapping with the up isolation region. The first down isolation region and the up isolation region isolate a portion of the epitaxial layer to be used to conduct a current. A second down isolation region of the first conductivity type is diffused down into the epitaxial layer between first and second contact surface areas of the epitaxial layer and into the portion of the epitaxial layer used to conduct the current.

Abstract: A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: A method forms a thin film resistor with a thick film resistor on one hybrid IC substrate, and provides a high efficiency hybrid IC utilizing advantages of both resistors.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: A shield structure is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The shield structure may be a metal such as aluminum, titanium or tungsten and serves to protect the undoped or lightly doped resistor within a polysilicon load device from charge-induced damage during ion implantation or plasma processing steps performed on the SRAM after formation of the polysilicon load device. The polysilicon load device is defined by depositing a layer of photoresist, exposing the photoresist through a master load mask, etching, and implanting into the exposed polysilicon. After the load device is formed, a dielectric layer is deposited and then a layer of conductive material is deposited. Dummy conductor structures are formed from the layer of conductive material using photolithography and the master load mask.

Abstract: A method of manufacturing a semiconductor device furnished on a silicon substrate with a bipolar element part and a resistance element part formed of an impurity diffusion layer, having (a) a step of forming a first oxide film on said silicon substrate and on the component elements formed on said substrate throughout the entire surface thereof, (b) a step of selectively and sequentially removing the part of said first oxide film corresponding to the base region of said bipolar element part and the surface of said silicon substrate directly underlying said first oxide film and, at the same time, cleaning the freshly exposed surface, (c) a step of forming a second oxide film on said silicon substrate and said component elements formed thereon throughout the entire surface thereof thereby differentiating the thickness of the oxide film formed on said base region and the thickness of the oxide film formed on said resistance element part, and (d) a step of selectively and instantaneously implanting an ion into sai

Abstract: A process for fabricating load resistors for memory cell units of a semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device having a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, wherein the first dielectric layer has an opening via exposing the gate electrode of the gate structure. A polysilicon layer is then deposited and patterned for forming a first connector in the via, at least one dummy structure on the first dielectric layer, and a second connector. A second dielectric layer is then formed to have two further vias respectively exposing the first and second connectors. A polysilicon load resistor is formed and coupled electrically to the first and second connectors and extends over the surface of the at least one dummy structure so as to have an elongated length.

Abstract: A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A semiconductor pressure sensor utilizes single-crystal silicon piezoresistive gage elements dielectrically isolated by silicon oxide from other such elements, and utilizes an etched silicon substrate with an etch stop. P-type implants form p-type piezoresistive gage elements and form p+ interconnections to connect the sensor to external electrical devices. The diaphragm is made from epitaxially-grown single-crystal silicon. Passivation nitride can be used for additional dielectric isolation. One practice of the invention provides over-range cavity protection, and thus increased robustness, by forming an over-range stop for the diaphragm through localized oxygen ion implantation and etching.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: The present invention develops several methods used in a semiconductor fabrication process to form a resistive material having a specific resistive value. A first method uses the steps of: forming a titanium layer over a silicon substrate; and subjecting the titanium layer to a rapid thermal processing cycle. A second method uses the steps of: forming a titanium layer over a silicon substrate; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. A third method uses the steps of: forming an insulating layer over a silicon substrate; forming an undoped polysilicon layer over the insulating layer; forming a titanium layer over the polysilicon layer; subjecting the titanium layer to a rapid thermal processing cycle; and forming a titanium nitride layer over the thermally processed titanium. Additionally, the resistive structure can be capped using a nitride layer.

Abstract: A magnetic sensor for use in a reading head for a magnetic disk is formed by depositing a plurality of planar superimposed layers of metals and semiconductors and using for the active element a planar structure formed orthogonal to the superimposed layers by their edges. Specifically, the edges of the superimposed layer form on the orthogonal planar surface a Corbino-disk structure in which conductive regions form inner and outer electrodes about an annular semiconductive region with high magnetoresistance, such as is provided by cadmium mercury telluride or indium antimonide.

Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor is monolithically manufactured. Polycrystalline silicon film, a dielectric film, and another polycrystalline silicon film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as an etching protection mask for the resistor and a capacitor. A refractory metal silicide for a polycide gate is uniformly deposited over the remaining another polycrystalline silicon films and dielectric films. The refractory metal silicide and polycrystalline silicon are consecutively etched through a patterned resist mask and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a capacitor having small change in capacitance versus applied voltage is manufactured in a MOS IC device having a polycide gate.

Abstract: In a method of etching a thin film resistor material, such as NiCr or CrSi, and of producing a thin film resistor, a non-photoresist hard mask is deposited on an exposed surface of thin film resistor material, a delineated portion of the hard mask is etched with a hydrogen peroxide etchant that does not affect the thin film resistor material to expose the material therebeneath, and the exposed thin film resistor material is etched with a second etchant that does not affect the hard mask. The second etchant may be sulfuric acid heated to greater than 125.degree. C. for NiCr or a mixture of phosphoric acid, nitric acid and hydrofluoric acid for CrSi. The hard mask preferably comprises TiW.

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract: An optically triggered silicon controlled rectifier (SCR) circuit (20) has a number of semiconductor layers diffused into an N- substrate (21). The layers form an SCR (50) having a P+ anode region (25), a P+ gate region (24), and an N+ cathode region (27). An adjustable base-shunt resistance, in the form of a P- channel depletion mode MOSFET (Q3), connects between the SCR gate region and the cathode region. The MOSFET includes a MOSFET gate region (35), a P+ drain region (24), a P-- channel (26), and a P+ source region (23). The substrate also accommodates a PN photodiode (22, D1) which connects to the MOSFET gate region for switching the MOSFET on and off in response to incident optical radiation (L) thereon. The SCR gate region also comprises photosensitive material. When sufficient optical radiation illuminates the photodiode and the SCR gate region, the MOSFET is turned off and the SCR is triggered, permitting anode-to-cathode current to flow.

Abstract: This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain impurities such as carbon, is deposited via chemical vapor deposition by pyrolization of an organometallic precursor compound of the formula Ti(NR.sub.2).sub.4 either alone or in the presence of either a nitrogen source (e.g. ammonia or nitrogen gas) or an activated species (which may include a halogen, NH.sub.3, or hydrogen radicals, or combinations thereof). The TiN film is then oxidized to create a structure that demonstrates highly stable, highly reliable resistive characteristics, with bulk resistivity values in giga ohm range. In a preferred embodiment of the invention, a predominantly amorphous titanium carbonitride film is deposited on an insulative substrate in a chemical vapor deposition chamber.

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Abstract: A polysilicon resistor element and a semiconductor device using the same are disclosed. The polysilicon resistor element has a resistive polysilicon film formed on a predetermined interlayer insulating film of a semiconductor chip. The resistive polysilicon film is covered by an insulating film having holes and high melting point metal films are formed in self-alignment to the holes. The high melting metal film constitutes one of lead portions of the polysilicon resistor element. A diffusion of the high melting point metal film due to heat treatment during fabrication, which causes an effective length of the resistor element, becomes negligible and reproducibility is improved.

Abstract: The method of fabricating a poly-silicon resistor includes a step for providing a dopant gas and a nitrous oxide gas as well as a silane gas to thereby deposit a silicon layer on a substrate by chemical vapor deposition under a deposition temperature not higher than 600 degrees centigrade so that the silicon layer includes the dopant of the dopant gas and oxygen, and a step for annealing the silicon layer under a temperature not lower than 600 degrees centigrade.

Abstract: A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Abstract: A collector region is formed in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate, and a non-monocrystalline silicon layer is deposited thereon. The non-monocrystalline silicon layer is annealed to obtain a polycrystalline silicon layer which is patterned into a polycrystalline silicon resistor. The polycrystalline silicon resistor is covered by an insulating layer. Thereafter, a base region is formed, and an emitter region is formed in the base region.

Abstract: The present method of forming a resistor as part of an integrated circuit includes a first masking step which blocks the resistor area of the integrated circuit from plasma etchant, with such plasma etchant meanwhile being used to define small line widths of, for example, metalization. Subsequent thereto, another layer of photoresist is applied to allow wet etching of the area of metalization above the resistor, meanwhile blocking such wet etchant from areas previously plasma etched.

Abstract: A resistor (45) of semiconductor material is formed on an insulating layer (42), then a silicon nitride film (46) is deposited on the entire surface including the resistor (45), and a silicon dioxide film (47) is sequentially deposited thereon, and thereafter electrodes (49A) and (49B)of the resistor (45) are formed, thereby preventing the fragility of the insulating layer (51) at step portions of the resistor (45), preventing the breakage of the electrodes and interconnections, and improving a withstand voltage between the resistor (45) and the interconnections crossing over it to thereby improve yield of a semiconductor device.

Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.

Abstract: A method for fabricating microwave power transistor elements onto a semiconductor body. An oxidizable barrier material is applied onto the wafer that both acts as a barrier to prevent diffusion between the contact metal of the transistor and the silicon and also acts as a ballast resistor. A contact metal layer is then deposited onto the barrier material at selected locations and the excess barrier material is removed. Barrier material is left between the contact metal and the silicon and at the selected ballast resistor locations. The ballast resistors may then be trimmed, increasing the value of the resistors, by oxidizing a thin surface layer of the exposed barrier material at the ballast resistor locations.

Abstract: An integrated circuit having diffused resistors formed in a low impurity concentration isolation region.

Abstract: A bidirectional nonlinear resistor for use as a nonlinear active element having a highly insulating organic film formed on a first conductor by polymerizing in an electrolytic solution containing a supporting electrolyte and a soluble organic compound, and a second conductor identical or not identical in kind with the first conductor formed on the organic film is provided. An active matrix substrate including a plurality of the bidirectional nonlinear resistor elements may be used to have a liquid crystal display panel. In a preferred embodiment, the electrolytic solution includes an alkali hydroxide as a supporting electrolyte so that dopant need not be removed after formation of the film. The electrolytic solution which is electrolytically polymerized to form the insulating organic film includes a monomer, preferably pyrrole, pyrrole derivatives, phenol or phenol derivatives, dissolved in an electrolytic solution.

Abstract: A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.

Abstract: A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be converted selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for copper/polyimide substrates.

Abstract: A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating material such as boro-phospho silicate glass is deposited on the upper surface of the integrated circuit. Polysilicon vias are formed that extend through the passivating layer and form an electrical ohmic contact with each designated circuit node. The polysilicon vias are subsequently ion implanted with oxygen or nitrogen to increase the resistance thereof to the final desired resistance, which can be greater than 100 megohms, and as much as a gigohm or a terohm. Finally, the vertical resistor is contacted with a metal layer formed on the surface of the passivating layer.

Abstract: A metal film and a polysilicon film are formed in one wiring, in that after a first polysilicon film is formed, an insulating film is formed on a region where a high-resistance portion of the polysilicon film is to be formed and, then, a metal film is deposited thereon. Then, the metal film deposited on the insulating film is removed. Thereafter, the wiring is formed by photolithography.

Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.

Abstract: A method of manufacturing a semiconductor device, includes the steps of: forming a first insulating layer (3), having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate (7); forming a high resistance portion (4) including polycrystalline silicon, on the convex area; and forming a protection layer (2) including SiN on the first insulating layer and the high resistance portion. The method also includes the steps of: removing a portion of the formed protection layer at the concave area such that the removed portion includes an area to form the contact hole and is larger than the area to form the contact hole; and forming a second insulating layer (5) including at least boron as an impurity on the protection layer and the first insulating layer.

Abstract: After doping a conductive layer made of a semiconductive material with impurites, a conductive layer with a deep trap level is formed by low temperature annealing. For forming such a conductive layer with a deep level, lattice defects are introduced into a conventional conductive layer through ion implantation and after that, only stable lattice defects, that can work as deep levels, remain by annealing at low temperature.

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be connected selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for cooper/polyimide substrates.

Abstract: A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

Abstract: A thermal jet ink printing is provided with an improved printhead. The printhead is formed by monolithic integration of MOS logic elements and drivers onto the same silicon substrate containing the resistive elements using a more efficient manufacturing process. In a preferred embodiment, the logic switches, logic drivers and resistive elements are formed from a single layer of polysilicon with the resistive element formed on a thermally grown field oxide layer. The integrated circuit chips are formed by a MOS fabrication technology which uses fewer processing steps than used in existing chips, and the resulting chips are thermally stable and can be operated at higher logic voltages.

Abstract: A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

Abstract: A method of fabricating a double layered polisilicon film with oxygen diffusion for scaled down polysilicon thin film transistor/resistor. The double layered polysilicon film structure includes: a first heavily doped polysilicon layer, produced by Low Pressure Chemical Vapor Deposition (LPCVD) system at about 610 degrees Centigrade, is used as electrodes of resistor or source/drain electrodes of a transistor, and a second layer of polysilicon, deposited by LPCVD at the temperature about 560 degrees Centigrade, is used as a resistor layer or a channel layer of a transistor.Oxygen treatment is applied at low temperature after the first polysilicon layer is defined. The oxygen present at polysilicon grain boundary blocks the dopant diffusing from the first electrode polysilicon to the second polysilicon which is used as resistor region or a channel region of a transistor. Thus, the resistor can maintain high resistivity and the transistor can maintain low threshold voltage even when they are scaled down.

Abstract: A method of interconnecting circuit components in a semiconductor integrated circuit including component elements formed in the substrate and thin-film resistors and capacitors formed on a surface of the substrate, a molybdenum plug is utilized to facilitate stable, uniform low resistance contacts to circuit elements, molybdenum (moly) plugs are utilized as a barrier between interconnect metallization and the circuit components. A CLAD moly/aluminum metallization interconnect can be fabricated in a standard process in which the moly plugs are formed. The accuracy and stability of thin-film resistors is facilitated during wafer processing, laser trimming, temperature cycling, and assembly processing thereby providing repeatable matching by eliminating contact resistance as a process variable.

Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

Abstract: Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.

Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silicon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.