Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

Abstract: Transistor drive current is controlled by controllably varying light exposure across a semiconductor substrate wafer based on an integrated circuit parameter. Integrated circuit parameters upon which the light exposure is varied include gate oxide thickness, rapid temperature annealing (RTA) temperature, polyetch bias and the like.

Abstract: Either a chemical amplification positive electron beam resist film or a chemical amplification negative electron beam resist film is used selectively according to an IC fabricating process when forming a minute IC pattern by using, as a mask, a resist pattern formed by irradiating the chemical amplification electron beam resist film formed on a semiconductor wafer with an electron beam, to form the minute IC pattern quickly in a high accuracy and to carry out an electron beam direct writing at a high throughput. The chemical amplification electron beam resist film is coated with a conductive polymer film before irradiating the same with the electron beam to prevent the charging-up of the chemical amplification electron beam resist film and to stabilize the chemical amplification electron beam resist film during a electron beam writing process.

Abstract: A method is described for checking masks used for the ion implantation steps in the manufacture of semiconductor integrated circuit element wafers before these masks are used for wafer processing. The masks being checked are segmented and the tone, clear or dark, is described by a numerical or logical value assigned to each segment. Mathematical operations on the data representing each mask are carried out and the results are compared with values expected from masks which are error free. Results From the mathematical operations on data representing masks which do not agree with the expected results indicate a high probability of error in those masks. The masks are then checked carefully and errors corrected before using the masks in wafer processing.

Abstract: Disclosed is a semiconductor fabrication process for fabricating MOS transistors in which ions are implanted only beneath the channel and are not overlapped with the source/drain regions so as to significantly reduce the junction capacitance of the source/drain regions for performance enhancement. The process comprises a first step of preparing a silicon substrate on which a field oxide region is formed to define an active region. In the second step, a phase-shift mask is used to define a substantially rectangular removal portion on a photoresist layer. One side of the rectangular removal portion is substantially aligned with the channel of the MOS transistor to be fabricated and the other three sides are placed within the field oxide region.

Abstract: A new method of forming the passivation layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed having a metal line layout in which the metal lines have a fixed spacing throughout their length and larger width around a turn than they have throughout the remainder of their length. Metal islands are formed perpendicular to the metal lines at the terminals of the metal lines. Dummy vias are opened in the insulating layer at the terminals of the metal lines wherein the terminals of the metal lines fill the dummy vias thereby reducing the aspect ratio of the spacing of said metal lines. A passivation layer is deposited over the metal lines wherein tunnels are formed within the passivation layer between the metal lines and at the terminals of the metal lines. The metal layout of the present invention prevents openings from being made within the passivation layer to the tunnels.

Abstract: A method of making high performance MOSFETs uses image reversal lithography to make punchthrough implants.

Abstract: A method for manufacturing a C-MOS thin film transistor device has the steps of implanting the n-type impurity only in the upper layer portion of the source-drain section of the n-channel transistor by controlling implantation energy of the n-type impurity; implanting the p-type impurity in the source-drain section and the gate electrode of the p-channel transistor, and the source-drain section and the gate electrode of the n-channel transistor by controlling implantation energy of the p-type impurity; and activating the implanted n-type and p-type impurities in the source-drain section of the n-channel transistor, and activating the implanted p-type impurity in the source-drain section and the gate electrode of the p-channel transistor and gate electrode of the n-channel transistor. The n-type and the p-type may be respectively changed to the p-type and the n-type in the above construction.

Abstract: A method of making a thin film transistor exhibiting a high channel conductance includes the steps of forming, on an insulating transparent substrate, a gate electrode, an insulating layer, a semiconductor layer, a photoresist, in this order and performing a back substrate exposure at the insulating transparent substrate using the gate electrode as a photo mask, to form a photoresist pattern. The photoresist pattern is then baked to make it flow outward to a desired bottom width. The semiconductor layer is etched using the photoresist pattern as an etch mask to form a semiconductor layer pattern. On the resultant entire exposed surface are formed an ohm contact layer and a metal layer. The metal layer is then subjected to photoing and etching processes, to remove its portion disposed above the semiconductor pattern and its opposite side edge portions, thereby forming a metal layer pattern for source and drain electrodes.

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

Abstract: A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.

Abstract: Formation of an isolation region and an alignment mark different in depth in a semiconductor device is disclosed. Phenol resin positive resist has the property that when selective exposure process is implemented to such a resist to apply heat treatment thereto in an amine gas atmosphere such as ammonium, there results the state where only a photosensitive agent at the portion in which light reaction takes place is escaped or gotten away, so this resin portion is insoluble in an alkali developer. By making use of this property, when exposure process is implemented only to the region portions to be etched different in depth to carry out baking, only the position is established by a single mask. Thereafter, only the alignment mark portion required to be deeper of the regions to be etched is etched exposed to light to etch it thereafter to allow only the isolation region to be exposed to light to etch it. Thus, the alignment mark portion becomes deeper than the isolation region by two etching process steps.

Abstract: An antireflection coating (21) for use in integrated circuit processing consists of a film of tungsten silicide (WSi.sub.0.45) or tungsten silicon nitride (WSiN). These coatings are preferably made by sputtering, with the tungsten silicon nitride coating being made by sputtering in a nitrogen-containing atmosphere.

Abstract: A surface layer (10), for example oxide, is provided on a first major surface (2) of a semiconductor body (1). A masking layer (11) having at least one window (12) is defined on the surface layer (10). The surface layer (10) and the semiconductor body (1) are etched through the window (12) to define an opening (13in the surface layer (10) and a recess (14) within the semiconductor body (1) extending beneath the surface layer (10) so that a rim portion (10a) of the surface layer (10) overhangs the recess (14). The rim portion (10a) of the surface layer (10) is removed by causing a settable flowable material (15) to flow onto the surface layer (10) and into the recess (14) and then causing the flowable material to set and thereby change volume to apply a force for causing the rim portion (10a) to break away from the remainder ( 10b) of the surface layer (10). The set flowable material (150) and thus the rim portion (10a) of the surface layer (10) are then removed.

Abstract: An antireflection coating (21) for use in integrated circuit processing consists of a film of x-silicon-nitride, where x is a metal from the group consisting of titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum and tungsten. These coatings are preferably made by sputtering, with the x silicon nitride coating being made by sputtering in a nitrogen-containing atmosphere.

Abstract: A method for applying photoresist to a top surface of a semiconductor wafer for defining an electronic circuit pattern. The wafer is placed on a horizontal turntable and liquid solvent is dispensed onto the wafer's top surface. Spinning the wafer distributes the solvent to a substantially uniform film thickness over the entire top surface. Liquid photoresist is dispensed onto the top surface over the solvent film, preferably while spinning the wafer, to distribute a photoresist layer over the entire top surface. Photoresist discharge is controlled so that the wafer sirface remains entirely wetted by the solvent film during distribution of the liquid photoresist. The solvent viscosity is lower than the liquid photoresist viscosity and the solvent film thickness is sufficient to enable the photoresist to fully cover any bare silicon, high density or undercut circuit features, generally in a range of 500 to 10,000 Angstroms and preferably 1,000 to 5,000 Angstroms.

Abstract: A method of forming a passivation film for protection of circuits and/or curcuit elements on semiconductor chips, IC chips, LSI chips, VLSI chips or microcomputer, wherein the resist film used in patterning the passivation film is employed as part of the passivation film after being subjected to post-baking, and the upper layer of the passivation film is made of a material selected from the group consisting of a light-sensitive polyimide, silicon resin, epoxy resin and silicon ladder polymer.

Abstract: In humid atmospheres (e.g., 40% relative humidity or above) solutions of 2,2-bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride/2,2-bis[4-(aminophenoxy)phenyl]hexafluoropropane polyimides tend to be unstable in the sense that during spin coating operations undesirable precipitate formation occurs on the rotating surface of the wafer. The result is the formation of unacceptable coatings due to their irregularity and lack of uniformity. Described are solutions of these polyimide polymers in a solvent containing one or more liquid aromatic hydrocarbons having a boiling point of at least about 110.degree. C. and one or more dipolar aprotic solvents having a boiling point of at least about 150.degree. C., such that the solution (a) contains on a weight basis from about 5% to about 50% of the polyimide, and (b) does not undergo precipitate formation during spin coating in an atmosphere of at least up to about 55% relative humidity.

Abstract: A manufacturing method of a semiconductor device of the present invention comprises a first step of exposing a periphery of a first region of a photoresist layer coating an insulating layer formed on a semiconductor substrate and a periphery of a second region for positioning, and a second step of heating said photoresist layer in ammonia atmosphere and forming an alkali insoluble portion in the periphery of the first region and that of the second region, a third step of exposing a third region, which is smaller than the first region, and the second region and developing these regions, a fourth step of etching the third region and the second region to a predetermined depth, and a fifth step of repeating the third and fourth steps once or more in a region, which is smaller than the third region, and the second region.

Abstract: Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount.

Abstract: A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 .mu.m and a second hole of 3 .mu.m in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 .mu.m and a second hole defining area of 2.4 .mu.m, and etching the insulation film with the resist pattern used as a mask.

Abstract: A method for patterning a photo resist film including the steps of coating a photo resist onto a semiconductor substrate exposing the photo resist coated and thereafter developing it, to thereby form a pattern on the photo resist film, wherein after exposure the semiconductor substrate on which the photo resist is coated is left in an atmosphere of a higher relative humidity than that at which the patterning exposure has been conducted for a time period until development.

Abstract: Process and apparatus employing flame ashing for stripping photoresist from a substrate in the manufacture of a semiconductor device. The substrate is exposed to the flame with the photoresist to be removed being contacted directly by the flame to oxidize, or ash, the photoresist. The flame is produced by burning oxygen and a gaseous fuel, and the rate of ashing is increased by preheating the substrate. Nitrogen, a nitrogen-containing gas or an inert gas is added to the fuel to provide a cooler flame and an improved ashing rate. In one disclosed embodiment, the oxygen and the gaseous fuel are discharged through a plurality of spaced apart openings in a burner and the substrate is moved relative to the frames to successively ash different portions of the photoresist.

Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions.First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.

Abstract: An improved patterning process, useful for the metallization of highly efficient photovoltaic cells, the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices, is disclosed. The improved patterning process includes the steps of providing a substrate with a photoactive layer, patterning the photoactive layer with an inclined profile, depositing on both the substrate and the patterned photoactive layer a layer of disjointed metal such that the thickness of the metal layer exceeds that of the patterned photoactive layer and that the metal layer deposited on the substrate is formed with walls normal to the surface of the substrate. Preferably, the deposition of the disjointed metal layer is effected by evaporative metallization in a direction normal to the surface of the substrate. The deposited metal layer on the substrate is characterized by a high aspect ratio, with a rectangular cross section.

Abstract: A process for making a self-aligned thin film transistor, said process comprising the steps of: (1) providing a gate which comprises a glass substrate, a transparent electrode on top thereof, and a metal electrode on top of said transparent electrode, (2) forming a stack by depositing over said gate a triple layer structure consisting of gate dielectric material, active material and a top passivating dielectric, (3) coating the top of said triple layer with a dual-tone photoresist, (4) exposing said photoresist from the top through a mask having transparent areas, opaque areas and areas transparent to selective wavelengths, using broad band UV light, (5) developing the photoresist by treatment with a solvent, (6) etching the stack with a liquid etchant through to the glass substrate, (7) exposing the photoresist from the bottom through the glass substrate using near UV light, (8) developing the photoresist with a solvent, and (9) etching off the top passivating layer of the stack.

Abstract: As a process for fabricating uniform patterns fine enough to produce a quantum size effect, the use of electron halography is proposed. Disclosed examples employing a process are methods of manufacturing a semiconductors laser whose threshold current is approximately 1 mA, and a permeable transistor and bistable device whose response rates are 100 GHz.