Abstract: A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber. A doped rough silicon layer is formed in situ superjacent the silicon dioxide layer. This is accomplished by depositing the silicon layer superjacent the silicon dioxide layer and exposing the silicon layer to a source gas, a dopant gas, and energy, preferably in situ to thereby form uniformly doped silicon layer and roughened polysilicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition.Alternatively, a uniformly doped roughened polysilicon layer is formed superjacent the silicon dioxide layer in situ. This formation is achieved by depositing an amorphous silicon layer superjacent the silicon dioxide layer and roughening the amorphous silicon layer in situ.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a polysilicon layer over a substrate, the polysilicon layer having an outer surface of a first degree of roughness; b) providing a layer of a refractory metal silicide over the outer surface of the polysilicon layer, the refractory metal silicide preferably being WSi.sub.x where "x" is initially from 1.0 to 2.5, the WSi.sub.x layer and the polysilicon layer outer surface defining a first interface therebetween; c) annealing the substrate at a temperature and for a time period which are effective to transform the WSi.sub.x into a tetragonal crystalline structure and to transform the first interface into a different second interface, the WSi.sub.x layer not being in a tetragonal crystalline state prior to the anneal, the WSi.sub.x at the second interface having an increased value of "x" from the initial value of "x"; and d) etching the WSi.sub.

Abstract: A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.

Abstract: A polysilicon film having a rough surface is formed by a reduced pressure CVD method at a temperature of 575.degree. C. and a deposition pressure of 0.2 Torr. Silicon ions are implanted into the polysilicon film having a rough surface. Thus, the tips of concaves and convexes at the rough surface of the polysilicon film are rounded. Then, this polysilicon film having a rough surface is patterned to form a storage node. A cell plate is formed to cover the storage node with a capacitor insulating layer therebetween. Consequently, a semiconductor device capable of suppressing leak current between capacitor electrodes can be manufactured.

Abstract: A capacitor structure of a semiconductor device which includes a semiconductor substrate, a first metal layer formed on the substrate, and a second metal layer formed on the first metal layer. The first metal layer has a nitridation-treated film along its outer surface. A tungsten film having a rugged surface is formed on the entire outer surfaces of the first and second metal layers. Because of the nitridation-treated film along the first layer, the tungsten film will be uniformly distributed along the first and second metals. A thin dielectric film is then formed on the surface of the tungsten, followed by a third metal layer formed on the dielectric film.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming anti-oxidizing regions from dot silicon for use as an oxidation mask to oxidize a polysilicon layer. Further, a silicon oxide layer is used as an etching mask to form a bottom storage node of a capacitor. An etching process is performed to etch a portion of the first polysilicon layer. Next, the silicon oxide layer is removed to define the bottom storage node. Utilizing the bottom storage node structure, the present invention can be used to increase the surface area of the capacitor.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.

Abstract: A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 2

Abstract: Boundary layers of silicon nitride not greater than 1 nanometer thick are inserted between adjacent two phosphorous-doped polysilicon layers forming parts of an accumulating electrode of a capacitor so as to decrease the grain size of the polysilicon and, accordingly, increase the grain boundaries exposed to the surfaces of the phosphorous-doped polysilicon layers, and hot phosphoric acid selectively etches the grain boundaries, thereby increasing the surface area of the phosphorous-doped polysilicon layers.

Abstract: An integrated circuit based on submicron technology is disclosed herein along with the way in which it is formed. The integrated circuit is comprised of an arrangement of different substances which are combined to form its body structure and which define within the body structure an array of electronic components including a diamond thin film coated trench arrangement. In one embodiment disclosed herein, the array of electronic component includes two such components which are in close proximity to and must be electrically isolated from one another and the diamond thin film coated trench arrangement serves to electrically isolate these two components from each other. In a second embodiment, the diamond thin film coated trench is specifically designed to serve as a capacitor forming part of, for example, a DRAM, a mixed signal circuit or a neuro-fuzzy circuit.

Abstract: First, a metal layer is deposited on a silicon film surface to form a silicide layer in an interface between the silicon film and the metal layer. Subsequently, the metal layer is all removed by etching such that silicide islands are left on the surface of the silicon film, and then the exposed silicon film surface is dry-etched by using the silicide islands as a selective mask.

Abstract: A method of forming a non-volatile semiconductor memory device includes the steps of forming a generally periodical undulation on a surface of a silicon substrate with a pitch of 1-20 nm, by cleaning the surface of the substrate by a cleaning solution to form a native silicon oxide film that covers the surface of the silicon substrate with a thickness that changes generally periodically, followed by a selective etching process applied to the native silicon oxide film thus formed to expose the surface of the silicon substrate, and forming a tunneling oxide film on the undulated surface of the substrate by applying a thermal oxidation such that the tunneling oxide film has a thickness that changes generally periodically with a pitch of 1-20 nm.

Abstract: A wafer which allows manufacture of a device to proceed at an exalted yield by preventing the resolution of exposure at the step of photolithography during the manufacture of the device from being impaired is obtained by a method which comprises a slicing step for slicing a single crystal ingot thereby obtaining wafers of the shape of a thin disc, a chamfering step for chamfering the wafer obtained by the slicing step, a lapping step for imparting a flat surface to the chamfered wafer, an etching step for removing mechanical strain remaining in the lapped wafer, an obverse surface-polishing step for polishing one side of the etched wafer, and a cleaning step for cleaning the polished wafer, which method is characterized by interposing between the etching step and the obverse surface-polishing step a reverse surface-preparing step for preparing the shape of the reverse side of the wafer.

Abstract: In accordance with the invention a rough overlayer, e.g., a tungsten film, is used to define a plurality of pillars in a polysilicon electrode layer. This increases the surface area of the polysilicon electrode and thus increases capacitance of a capacitor incorporating the electrode layer in a DRAM cell.

Abstract: A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.

Abstract: A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

Abstract: A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.

Abstract: The present invention develops a container capacitor by forming a conductively doped polysilicon plug between a pair of neighboring parallel conductive word lines; forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over the parallel conductive word lines and the plug; forming a planarized borophosphosilicate glass (BPSG) insulating layer over the planarized tetra-ethyl-ortho-silicate (TEOS) insulative layer; forming an opening into both insulating layers to expose an upper surface of the plug, the opening thereby forming a container shape; forming first, second and third layers of conductively doped amorphous silicon into the container shape while simultaneously bleeding oxygen into the amorphous silicon; forming individual container structures having inner and outer surfaces and thereby exposing the BPSG insulating layer; removing the BPSG insulating layer thereby exposing the outer surface of the container structures; converting the exposed inner and outer surfaces of amorphous silicon

Abstract: A silicon layer having semispherical protrusions of about 100 nm is formed as a lower electrode of a capacitor by low pressure vapor deposition method. A silicon oxide film is formed by oxidizing the surface of this silicon layer. The intervals between the rough portions of the silicon layer are increased by removing this silicon oxide film. Thereafter, a dielectric layer and an upper electrode are formed. In other methods, after the formation of the silicon layer having the roughness, thermal treatment is continuously carried out in oxygen-free atmosphere to increase radius of curvature of the roughness of the silicon layer. Thereafter, the dielectric layer and the upper electrode are formed.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: Disclosed is a method of producing a chip-type solid-electrolyte capacitor, in which the surface of a sheathing resin layer formed on an anode body is roughened by forming an irregularity thereon, and plated metal layers are formed on the surface thus roughened for an anode and cathode use. The metal layers are strongly adhered on the roughened surface. The surface-irregularity of the sheathing resin layer is produced by blasting hard particle material made of, for example, alumina or glass using a sandblast machine, or by irradiating a laser beam such as the YAG laser beam or the like.

Abstract: In the present invention, a stable and uniform texturized surface of a conductive structure is developed by annealing, oxidizing and etching a layer of metal silicide that has been deposited over a semiconductive material. Using this process during fabrication of memory cell in a DRAM will increase storage node capacitance by creating texturized capacitor cell plates that will retain their textured surfaces throughout implementation of conventional DRAM fabrication processes.

Abstract: A process for layering a low reflectivity metal layer on a semiconductor wafer for decreasing the optical reflectivity and increasing the optical absorptivity of the metal layer for laser processing. The process includes: depositing a metal layer, such as aluminum, over a substrate, roughening the surface of the metal layer by chemical mechanical planarization (CMP) while injecting a silicon oxide slurry over the surface and then laser processing the metal. The roughened metal surface has an increased surface area and irregular surface features that help absorb incident laser radiation with less reflectance.

Abstract: A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

Abstract: The method for producing the surface reflectance of the metal layer during semiconductor processing includes the step of roughening the surface of a metal layer prior to forming the photoresist thereon. The roughened surface reduces reflections that can cause metal notching effects. The step of roughening the surface includes depositing a layer (34) of aluminum which is substantially thinner than the thickness of the primary metal layer by a sputtering process.

Abstract: A semiconductor device is manufactured by forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type, and a first nonmonocrystalline silicon film is formed on the first insulating film. A second insulating film is deposited on the first nonmonocrystalline silicon film by CVD, sputtering or molecular beam method. An impurity is then ion-implanted in the first nonmonocrystalline silicon film through the second insulating film. The second insulating film is then removed to expose the surface of the first nonmonocrystalline silicon film doped with the impurity, and a thermal oxide film is formed on the exposed portion of the first nonmonocrystalline silicon film. Subsequently, a second nonmonocrystalline silicon film is formed on the thermal oxide film, and a third insulating film is formed on the second nonmonocrystalline silicon film.