Abstract: Methods of forming field effect transistors.

Abstract: An electro-optic device featuring an semiconductor device formed by providing an insulator over a gate electrode, and anodic oxidizing only the sides of the gate electrode.

Abstract: A self-aligned method of forming contacts to a transistor gate, source and drain reduces the required spacing between the nominal center of the gate and electrode at little cost in process complexity by the provision of a sidewall positioned above the LDD-defining sidewall and extending above the top Of the gate by a buffer amount sufficient to protect the gate during the process of opening a source or drain contact.

Abstract: A process for producing self-aligned titanium silicide. A silicon substrate is provided, silicon electrode and oxide insulator regions are formed on the substrate, and a titanium layer overlying the electrode and insulator regions is formed. The device is heated in an oxygen rich environment to form titanium silicide overlying the electrode regions and to form titanium oxide overlying the insulator regions and metal silicide.

Abstract: A method is described for forming metal silicide contacts to polycrystalline silicon regions and nonmetal silicide contacts to monocrystalline silicon regions of an integrated circuit device. Polycrystalline silicon regions are formed and pattered. A dielectric masking layer is formed over the polycrystalline and monocrystalline silicon regions. The surfaces of the masking layer are covered and the irregularities of the surfaces filled with an organic material to thereby planarize the surfaces. The organic material is blanket etched until the masking layer which covers the polycrystalline silicon regions is exposed and allowing the masking layer which covers the monocrystalline silicon regions to remain covered with organic material. The exposed masking layer is removed from the polycrystalline regions. The remaining organic material is removed. A layer of metal film is blanket deposited over the wafer. The metal silicide contacts to polycrystalline regions are formed.

Abstract: A method for electrically connecting a bit line to a source electrode of the MOSFETs in a semiconductor device is disclosed and which comprises arranging a gate electrode mask to form gate electrodes which are spaced apart and formed on respective gate oxide layers such that a contact mask which when positioned within the space between the gate electrodes provides a gap, for mask misalignment and critical dimension loss during the contact mask patterning process, of less than about 0.3 micrometer, separating each gate electrode from the respective proximate side of the contact mask. A contact hole having a side wall is formed to expose the source electrode by utilizing the contact mask and etching a portion of the etch stop layer and a portion of the insulating layer above the source electrode by the contact mask patterning process. A second insulating layer is deposited over the entire surface of the device.

Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

Abstract: A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. In a preferred embodiment, the configuration is also planarized.A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

Abstract: A method of producing a semiconductor device of high integration density and high reliability with high yield, using self-alignment techniques, including forming a gate electrode on a semiconductor substrate of a first conductivity type with an insulating film arranged above and below it, forming a pair of first impurity regions of a second conductivity type mutually separated and self-aligned with the gate electrode in the substrate, and forming a wall consisting of insulator on at least one side face of the gate electrode and the upper and lower insulating films, forming a second highly doped impurity region of second conductivity type at greater depth in the substrate than the first impurity region in a self-aligned manner with respect to the wall, forming an electrode layer connected to the second impurity region, with at least a portion of the electrode extending over the upper insulating film of the gate electrode, and selectively forming a wiring layer on the electrode layer.

Abstract: A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower.A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

Abstract: A high speed GaAs FET is provided by forming a sandwiched GaAs channel between AlGaAs layers and employing an Si implant to provide channel doping for the GaAs channel. The poor activation efficiency of Si in AlGaAs relative to its activation efficiency in GaAs provides a channel having a higher active dopant concentration than exists in the adjacent sandwiching layers. This tends to enhance conductivity in the channel relative to the sandwiching layers.

Abstract: A method is disclosed for fabricating submicron silicon gate metal-oxide-semiconductor field effect transistors (MOSFETs) which have threshold and punchthrough implants that are self-aligned to the gate electrode and source and drain regions. A layer of dielectric material (12) is either deposited or grown on the surface of a substrate, and a trench (15), which defines the region of the MOSFET gate electrode, is formed in the dielectric layer. A gate oxide (16) is formed at the exposed substrate at the bottom of the trench, and an implant is performed into the silicon substrate wherever there is gate oxide, but not into the portion of the substrate covered by the original dielectric layer. A layer of polysilicon (20), preferably doped, or another metallic film is then deposited onto the surface. The polysilicon is etched back to the top surface of the dielectric layer, thereby leaving polysilicon in the trench to form the gate electrode (24).

Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;(c) forming a self-aligned insulating layer on the side walls of the gate electrode;(d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and(e) forming electrodes which are connected to the source region, drain region and gate electrode.

Abstract: In the production of an MOS transistor or a one-MOS transistor one-capacitor memory cell, a gate electrode is made of aluminum, doped regions are formed by an ion-implantation method using the gate electrode as a mask, and the doped regions are annealed by a laser beam.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a self-aligned insulating film at least on a side wall of said gate electrode;(c) forming a self-aligned metal or metal silicide film on a region on which an insulating film is not formed, said region including a source region, a drain region and a diffusion interconnection region which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and(d) forming said source region, said drain region and said diffusion interconnected region which is the extended part of at least one of said source region and said drain region, by doping at least one time said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after st

Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Abstract: A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer.