Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.

Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.

Abstract: In a Schottky field effect MESFET transistor including a semiconductor substrate and source, gate and drain electrodes, the electrical resistance of the gate is reduced to substantially zero by implementing the gate electrode as a sheet of metallization which bypasses a portion of the source electrode and which is spaced from the source electrode by a layer of air or the like. The MESFET transistor may be fabricated by providing drain and source electrodes on a semiconductor substrate with the electrodes situated side-by-side. Photoresist is applied over at least the source electrode while leaving exposed (a) a first portion of the substrate surface between the source and drain electrodes and (b) a second portion of the substrate surface situated on an opposite side of the source electrode and which is used as a bonding pad location. Gate metallization is then formed over the photoresist and in contact with the first and second areas of the substrate surface.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

Abstract: A process for fabricating a semiconductor-metal-semiconductor electronic device and the device formed thereby from a semiconductor substrate is described. The substrate forms a first active region of the device. A porous layer of conductive material is deposited on the substrate preferably by molecular beam epitaxy forming a control region. A layer of a semiconductor material epitaxially matched to the substrate is then grown on the layer of conductive material so that the layer of semiconductor material forms a second active region of an electronic device.

Abstract: A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.