Abstract: There is disclosed a method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer, the method comprising the steps: sequentially forming first and second compound semiconductor epitaxial layers on a compound semiconductor wafer; forming a first silicon oxide layer on the second compound semiconductor epitaxial layer at a predetermined low temperature and depositing a poly-crystal silicon layer on the first silicon oxide layer; removing portions of the larminated layers by using a etching technique to form grooves on the compound semiconductor wafer; depositing a second silicon oxide layer overlying thereon at a predetermined low temperature; etching back horizontal portions of the second silicon oxide layer to form side walls in each of the grooves and polishing the polysilicon layer to form a planar surface thereon; bonding the planar surface and the single-crystal silicon wafer by using a thermal process technique; removing the compound semicondu

Abstract: A method for forming a transistor which may be suitable for high temperature application is provided. A single crystal silicon substrate has an overlaying layer of epitaxially grown cubic boron nitride in crystallographic registry with the silicon substrate. The cubic boron nitride is epitaxially grown using laser ablation techniques and provides an electrically resistive and thermally conductive barrier. An active layer of epitaxial silicon is then grown from the layer of cubic boron nitride, such that the overlaying layer of epitaxial silicon is in crystallographic registry with the layer of boron nitride which is in crystallographic registry with the underlying silicon substrate. Appropriately doped source and drain regions and a gate electrode are provided to form the transistor.

Abstract: Unpinned epitaxial metal-oxide-compound semiconductor structures are disclosed and a method of fabricating such structures is described. Epitaxial layers of compound semiconductor are grown by MBE which result in the formation of a smooth surface having a stabilized reconstruction. An elemental semiconductor layer is deposited epitaxially in-situ with the compound semiconductor layer which unpins the surface Fermi level. A layer of insulator material is then deposited on the elemental semiconductor layer by PECVD. In one embodiment, the compound semiconductor is GaAs and the elemental semiconductor is Si. The insulator material is a layer of high quality SiO.sub.2. A metal gate is deposited on the SiO.sub.2 layer to form an MOS device. The epitaxial GaAs layer has a density of states which permits the interface Fermi level to be moved through the entire forbidden energy gap. In another embodiment, the SiO.sub.

Abstract: Intermediate buffer films having a low plastic deformation threshold are provided for absorbing defects due to lattice mismatch and/or thermal coefficient of expansion mismatch between a substrate or layer support and an overlayer while concurrently providing a good template for subsequent crystalline growth at the overlayer. This is accomplished for diamond cubic structure substrates, such as Si or Ge or Si on sapphire or crystalline Si on glass, upon which are to be deposited lattice mismatch overlayers, such as, GaAs or ZnSe. Also, zinc blend type substrates, such as GaAs or InP may be employed with such intermediate buffer films. A characteristic of these intermediate buffer films is a substantially lower plastic deformation threshold compared to either the substrate support or the overlayer to be grown heteroepitaxially thereon.

Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.

Abstract: A GaAs layer having a high crystallinity can be grown over an Si substrate without warping, by process for growing a GaAs layer on an Si substrate, said process comprising: forming a first GaAs layer in the amorphous state on the Si substrate at a first temperature, the first GaAs layer being formed with a thickness allowing formation of a single crystalline layer having a thickness of one to three monomolecular layers; heating the first GaAs layer to change the amorphous state of the first GaAs layer to a single crystalline state; forming an Si layer on the first GaAs layer at a second temperature higher than the first temperature, the Si layer being formed with a thickness having one to six monoatomic layers; forming a second GaAs layer in the amorphous state on the Si layer at the first temperature, the second GaAs layer being formed with a thickness substantially the same as the thickness of the first GaAs layer; heating the second GaAs layer the change the amorphous state of the second GaAs layer to a si

Abstract: When high-vacuum methods are used in the manufacture of miniaturized devices such as, e.g., semiconductor integrated-circuit devices, device layers on a substrate are preferably patterned without breaking of the vacuum. Preferred patterning involves deposition of a semiconductor mask layer, generation of the pattern in the mask layer by ion deflected-beam writing, and transfer of the pattern by dry etching. When the mask layer is an epitaxial layer, further epitaxial layer deposition after patterning may proceed without removal of remaining mask layer material.

Abstract: A method for reducing the defect and dislocation density in III-V material layers deposited on dissimilar substrates is disclosed. The method involves ion implantation of dopant materials to create amorphous regions within the layers followed by an annealing step during which the amorphous regions are recrystallized to form substantially monocrystalline regions. The wafers produced by the process are particularly well suited for optoelectronic devices.

Abstract: A GaAs growth crystal comprises a Si substrate, an intermediate layer formed on the substrate and a GaAs layer grown on the intermediate layer. The intermediate layer includes constituent GaP/GaAsP and GaAsP/GaAs superlattice layers and additionally AlP and AlGaP thin films.

Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication.