Abstract: In a conventional method for forming a capacity element for DRAM, a tantalum oxide film is formed on the surface of polycrystal silicon film constituting a capacity lower electrode, and a high temperature treatment is then carried out in an oxygen atmosphere to improve leakage current properties, thereby converting this tantalum oxide film. In the capacity element having the thus formed capacity insulating film, an obtainable capacity value is small. In the present invention, a densification treatment is carried out at a relatively low temperature in place of the high temperature treatment step of the tantalum oxide film, whereby the capacity element having the large capacity value can be formed without deteriorating the leakage current properties.

Abstract: A method for fabricating a DRAM capacitor, including the steps of forming a double contact hole structure by utilizing an insulating spacer two times, filling only the lower portion of the contact hole, forming a pattern having an undercut portion from two insulating films exhibiting a superior wet etch rate difference, coating a conduction layer over the pattern to form an insulating spacer from a portion of the conduction layer disposed on the stepped pattern portion, and etching the resulting structure at its full surface using the insulating spacer as a mask to isolate a capacitor to be finally formed, whereby a capacitor electrode having a double rectangular frame shape is formed. With such a structure, the inner area of the contact hole can be used as a part of the capacitor, thereby enabling the surface area of capacitor to be increased. Since no separate mask is used for the etching step, it is possible to simplify the fabrication of DRAM capacitor.

Abstract: The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess. The process is then continued with a formation of an oxidation resistant conductive layer and the patterning thereof to complete the formation of the storage node electrode. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.

Abstract: A method for fabricating a capacitor of a semiconductor device, including the steps of: sequentially forming a planarized insulating oxide film, a barrier layer, and a first electrode layer over a semiconductor substrate; forming a first contact hole; forming electrode material spacers respectively on side walls of the first contact hole; forming a second contact hole for exposing an impurity diffusion region of the semiconductor substrate; forming a second electrode layer such that it is in contact with the impurity diffusion region; selectively removing an upper portion of the second electrode layer disposed around a region where the first contact hole is defined, thereby forming a second-electrode layer pattern; forming oxide film spacers on side walls of the second-electrode layer pattern; etching the second-electrode layer pattern, the second electrode layer and the first electrode layer until an upper surface of the barrier layer is exposed, thereby forming a first-electrode layer pattern and outer and

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.

Abstract: A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.

Abstract: An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.

Abstract: In accordance with the invention a rough overlayer, e.g., a tungsten film, is used to define a plurality of pillars in a polysilicon electrode layer. This increases the surface area of the polysilicon electrode and thus increases capacitance of a capacitor incorporating the electrode layer in a DRAM cell.

Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.

Abstract: A storage capacitor having high dielectric constant materials and a method for forming same are described. The method solves the problems associated with fabrication of planar capacitors for DRAM chips constructed from inorganic oxides with perovskite structure. These materials are not readily etched by conventional ion etching techniques. These materials also react with silicon and silicon dioxide and the disclosed process avoids these interactions.

Abstract: A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.

Abstract: A thermal oxidation method for producing a semiconductor device having a capacitor insulating film structure capable of making a thin film having a small leakage current and small temperature dependence of the leakage current. In the insulating film, a silicon nitride film with a small electron mobility and a silicon oxide film with a small hole mobility are alternately laminated in order of the nitride film/oxide film/nitride film/oxide film from a lower electrode side. A current component such as electrons flowing in this insulating film structure is limited by the layer with the smaller mobility to reduce the leakage current. An oxide film thickness of approximately several .ANG. can thus be strictly controlled. By forming the silicon nitride film between the high dielectric oxide film and the electrode, the reaction of the silicon electrode and the high dielectric oxide film can be prevented.

Abstract: This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick.

Abstract: An electronic circuit apparatus which is constructed by laminating a plurality of thin films onto an insulative substrate. On the substrate, an electronic circuit element having two conductive layer which are laminated through an insulative layer is formed. The insulative layer is formed so as to cover the whole surface of the insulative substrate.

Abstract: An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate.

Abstract: The invention relates to a process for increasing the surface area of a silicon layer for a charge storage electrode by forming a silicon layer having a highly granulated surface and which comprises depositing an alloy layer comprising an A-material 2X and a B-material 2Y on a first insulating layer 1 which is deposited on a substrate. The depositing of the alloy layer takes place at a predetermined temperature to form a plurality of B-material 2Y precipitations on the insulating layer 1 and an A-material 2X layer on the plurality of B-material 2Y precipitations and on a plurality of first insulating layer surfaces not covered by the plurality of B-material 2Y precipitations. The resulting structure is then cooled, preferably to room temperature. The solubility of the B-material 2Y, which may be considered as the solute, is extremely limited in the A-material 2X, which may be considered as the solvent.

Abstract: A silicon layer having semispherical protrusions of about 100 nm is formed as a lower electrode of a capacitor by low pressure vapor deposition method. A silicon oxide film is formed by oxidizing the surface of this silicon layer. The intervals between the rough portions of the silicon layer are increased by removing this silicon oxide film. Thereafter, a dielectric layer and an upper electrode are formed. In other methods, after the formation of the silicon layer having the roughness, thermal treatment is continuously carried out in oxygen-free atmosphere to increase radius of curvature of the roughness of the silicon layer. Thereafter, the dielectric layer and the upper electrode are formed.

Abstract: A semiconductor memory device having an excellent data holding characteristics because of a small leak current from a trench and a process for producing the same are disclosed. An SiO.sub.2 film 12 having an appropriate pattern is formed on a P type silicon substrate 11. Trenches 14 are relatively formed on the SiO.sub.2 film 12 by selectively growing a P type epitaxial layer 13 on the silicon substrate 11 using the SiO.sub.2 film 12 as a mask. An N type layer 23 acting as an electrode of a capacitor 27 is formed on the inner wall of the trench 14 by the oblique ion implantation of impurities 22 thereto. A polycrystalline silicon film 25 acting as an opposite electrode of the capacitor 27 is formed on an ONO film 24 so that the ONO film 24 is disposed between the polysilicon film 25 and the SiO.sub.2 film. The semiconductor memory device which is produced by this method without etching to form the trenches 14 has a fewer crystal defects in the epitaxial layer 13 around the trenches 14.

Abstract: The present invention relates to a semiconductor device and a method of fabrication of the same, said semiconductor device including a capacitive structure comprising of a lower layer electrode consisting of a silicon material, a capacitive insulating film consisting of a tantalum oxide film and an upper layer electrode, said upper layer electrode comprising at least a titanium nitride film for covering said capacitive insulating film. Said method of fabrication comprises the steps of: forming the lower layer electrode; forming the capacitive insulating film for covering said lower layer electrode; and forming the titanium nitride film for covering said capacitive insulating film.

Abstract: The method includes only two masking levels. During the second masking, capacitative lines (LC) (dedicated or merged with the addressing lines) are defined which overlap the pixels so as to form the storage capacitors (Cs).Application for display on flat liquid crystal screens.

Abstract: According to this invention, there is disclosed a method of manufacturing a silicon nitride film on a semiconductor substrate using a low-pressure CVD apparatus, including the steps of setting a plurality of semiconductor wafers in a boat in a reaction furnace, increasing a temperature in the reaction tube to a predetermined temperature and decreasing a pressure in the reaction tube to a predetermined pressure, and supplying Si(N(CH.sub.3).sub.2).sub.4 gas from a first gas source to the reaction tube and supplying NH.sub.3 gas from a second gas source to the reaction tube.

Abstract: The invention relates to a process for increasing the surface area of a silicon layer for a charge storage electrode by forming a silicon layer having a highly granulated surface and which comprises depositing an alloy layer comprising an A-material 2X and a B-material 2Y on a first insulating layer 1 which is deposited on a substrate. The depositing of the alloy layer takes place at a predetermined temperature to form a plurality of B-material 2Y precipitations on the insulating layer 1 and an A-material 2X layer on the plurality of B-material 2Y precipitations and on a plurality of first insulating layer surfaces not covered by the plurality of B-material 2Y precipitations. The resulting structure is then cooled, preferably to room temperature. The solubility of the B-material 2Y, which may be considered as the solute, is extremely limited in the A-material 2X, which may be considered as the solvent.

Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.

Abstract: A method for manufacturing a semiconductor device includes forming contact holes in insulating layers to expose an impurity doped region of a semiconductor substrate. An epitaxial layer is then grown in the contact hole. A polycrystalline silicon layer is formed over the top to provide the lower electrode of a capacitor. Accordingly, the polycrystalline layer is separated from the impurity doped region thereby preventing current leakage.

Abstract: In fabricating a semiconductor device, when impurities are diffused from a silicon oxide layer containing the impurities to a semiconductor layer, a diffusion atmosphere is controlled so as to oxidize or reduce a specified impurity to thereby control the diffusion coefficient of the impurities in the silicon oxide layer. Thus, it is possible to form a diffusion layer having a desired impurity profile under a good control.

Abstract: A structure and method of fabricating a active matrix display with halftone grayscale and wide viewing angle, having an active matrix array and a control capacitor array fabricated on separate substrates.

Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.

Abstract: A process for fabricating integrated resistors in high density interconnect substrates for multi-chip modules. In addition, the resistor material can be connected selectively into an insulator for optionally allowing for the simultaneous fabrication of integrated resistors and capacitors in relatively few steps. The process is well suited for cooper/polyimide substrates.

Abstract: A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulatin

Abstract: A method of manufacturing a semiconductor memory includes the steps of, on a semiconductor substrate having underlayer wiring which is composed of a plurality of gate portions provided with side walls and a diffused region between the gate regions, i) forming a layer insulating film which is smaller in thickness in the diffused region than the side walls of each of the gate regions and which is made of a material etched more easily than the material of the semiconductor substrate; ii) depositing a conductive layer of a material etched more easily than the layer insulating film, over the entire surface of the layer insulating film; iii) removing the conductive layer simply except a portion where a contact hole is to be formed in the diffused region, by etching with a pattern film for forming the contact hole; iv) depositing an insulating film and a pattern film for forming the contact hole over the entire surface again; and v) removing the insulating film, the remaining conductive layer and the layer insulatin

Abstract: A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.

Abstract: The present invention provides a process which is particularly suited for mass-producing solid electrolytic capacitors. The process utilizes a combination of a mold and a presser member. The mold has a series of molding recesses, and a lead receiving groove extending along and through the series of molding recesses. The presser member has a corresponding series of pressing projections. A portion of a continuous lead wire is placed in the groove, and powdered electrode material is loaded in the molding recesses. The presser member is then moved toward the mold, so that the powdered material is compacted within the molding recesses by the pressing projections. The resulting compacts are removed from the mold together with the wire. The same process steps are repeated with respect to other portions of the wire.

Abstract: A method of manufacturing integrated circuits includes steps: forming a first layer of polycrystalline silicon on areas of a semiconductor substrate previously covered with a dielectric material; forming a first insulating layer and a second thin layer of polycrystalline silicon acting as a shield; removing the second layer of polycrystalline silicon and the first insulating layer except from predetermined areas for containing a first type of electronic component; doping the exposed portion of the first layer of polycrystalline silicon; forming, by deposition, masking and removal, of a second insulating layer on the first layer of polycrystalline silicon in an area for containing a second type of electronic component; forming of a third layer of polycrystalline silicon; masking predetermined zones of this latter layer lying at least partially above the areas intended for the two types of electronic components, and removing the polycrystalline silicon external to these predetermined zones.

Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.

Abstract: A microelectronic device (10a) provides an improved capacitor (12a) having two plate members (22a, 26a) capacitively coupled via a dielectric layer (24). In accordance with the invention, contact portions (32a, 42a) have substantially twice the thickness of functional portions (28, 38) prior to etching oxide (16) to form contacts (18, 20). In this fashion, the total thickness of capacitor (12a) is minimized yet the thickness of contact portions (32a, 42a) is maximized. Hence, maximum thickness for etching purposes [to construct metal contact 18, 20)] is achieved. Thus the topographical profile of microelectronic device (10a) is essentially reduced to half that of the prior art while the necessary pre-etch thickness of contact portions (32a) and (42a) is maintained. Other pre-etch thickness proporations may be utilized between conductive layer subportions (34) and (36) and conductive layer subportions (44) and (46).

Abstract: A semiconductor device comprising a buried phosphor glass layer (5) consisting of a subjacent thick electrically insulating layer (4), a phosphor glass layer (6) and an overlying thin covering layer (7). According to the invention, the thicker electrically insulating layer (4) is locally removed and the combination of phosphor glass layer 6 and covering layer 7 is used as a dielectric for a capacitor. The invention also relates to a method of manufacturing a capacitor with indicated dielectric.

Abstract: An image photodetector includes a photosensor unit, a charge storage unit, and a switch unit, all of them are formed on a single-crystal semiconductor film grown from a single nucleus such that crystal formation is performed on a substrate having a free surface including a non-nucleus formation surface and a nucleus formation surface adjacent thereto. The non-nucleus formation surface has a low nucleation density. The nucleus formation surface has a sufficiently small area to allow growth of only the single nucleus and has a higher nucleation density that that of the non-nucleus formation surface.

Abstract: A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

Abstract: Thin-film capacitors are produced with laser chemical vapor deposition technology on a substrate, which is preferably the substrate of an integrated circuit, by forming alternating layers of electrodes and dielectric.

Abstract: During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps.

Abstract: A semiconductor memory device such as a MOS dynamic RAM comprises transistor portions (2, 3 and 5) for writing and reading a signal and capacitor portions (1, 2, 6 and 9) by pn junction for storing a signal. The capacitor portions have preferably as large a capacitance as possible. For this purpose, a capacitor hole (7) is formed in a p type semiconductor substrate (6) and an n type semiconductor region (9) is provided along the capacitor hole (7) so that the pn junction area therebetween is increased and the capacitance is made large.

Abstract: A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.

Abstract: An annealing process carried out at 800.degree. C. in a wet O.sub.2 ambient permits the manufacture of a reliable storage capacitor wherein the dielectric layer is comprised of silicon oxynitride formed by low pressure chemical vapor deposition (LPCVD). The manufacturing process includes first depositing the silicon oxynitride film by LPCVD, second annealing in wet O.sub.2 at 800.degree. C. or N.sub.2 at 1000.degree. C., third forming an N-type region in the silicon substrate by As.sup.+ ion implantation through the silicon oxynitride film, fourth annealing in wet O.sub.2 at 800.degree. C., and fifth depositing an electrode.

Abstract: A semiconductor device comprising a capacitor of a laminated structure and a method of manufacturing thereof, in which first conductive layer and second conductive layer of different materials or different compositions are stacked alternately with dielectric films interposed therebetween and the first conductive layers and the second conductive layers are interconnected respectively at a time by suitably combining a selective etching method and an anisotropic etching method.

Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).

Abstract: A method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and is etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the memory capacitor forming region.

Abstract: A method of manufacturing a semiconductor device is disclosed wherein a matched capacitor having a relatively high capacitance is formed in the structure of a linear MOS device. The method utilizes the standard procedure for manufacturing MOS devices which includes two separate mask steps for forming contact openings to a field effect transistor. During the first mask step, the opening for the upper plate contact of the capacitor is fully etched while the opening for the lower plate contact is only partially etched. During the second mask step, the opening for the lower plate contact of the capacitor is fully etched to the lower plate. In this manner the existing standard procedure may be used without the addition of nonstandard mask and diffusion steps.

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.