Silicon On Sapphire Sos Patents (Class 148/DIG150)
  • Patent number: 6124185
    Abstract: A process for producing a metal oxide semiconductor (MOS) transistor is provided. At least two trenches are formed at a surface of a first substrate. Oxide is deposited onto the at least two trenches. The at least two trenches each have a surface spaced apart from the surface of the first substrate. A second substrate is placed onto the surface of the first substrate. A layer is delaminated from the first substrate. The layer includes the at least two oxide-filled trenches and a portion of the first substrate. The layer is then bonded to a second substrate. First and second active regions are then formed, in the portion of the first substrate, overlaying the surfaces of the at least two trenches.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: September 26, 2000
    Assignee: Intel Corporation
    Inventor: Brian S. Doyle
  • Patent number: 5906708
    Abstract: Silicon-germanium-based compositions comprising silicon, germanium, and carbon (i.e., Si--Ge--C), methods for growing Si--Ge--C epitaxial layer(s) on a substrate, etchants especially suitable for Si--Ge--C etch-stops, and novel methods of use for Si--Ge--C compositions are provided. In particular, the invention relates to Si--Ge--C compositions, especially for use as etch-stops and related processes and etchants useful for microelectronic and nanotechnology fabrication.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: May 25, 1999
    Assignee: Lawrence Semiconductor Research Laboratory, Inc.
    Inventors: McDonald Robinson, Richard C. Westhoff, Charles E. Hunt, Li Ling
  • Patent number: 5897328
    Abstract: An organic EL display device has a substrate, a plurality of organic EL elements formed on the substrate and a plurality of thin film transistors formed on the substrate. The transistors are connected to the respective EL elements for controlling current applied to the respective elements.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: April 27, 1999
    Assignee: TDK Corporation
    Inventors: Yukio Yamauchi, Michio Arai
  • Patent number: 5861336
    Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: January 19, 1999
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Ronald E. Reedy, Mark L. Burgener
  • Patent number: 5759878
    Abstract: A method of fabricating a semiconductor device comprises the steps of preparing a transparent support substrate, forming a first gate electrode comprising semiconductor single crystal silicon by epitaxial growth on the transparent support substrate, forming an insulating film over the first gate electrode, forming a through-hole in the insulating film to expose a portion of the first gate electrode, laterally and epitaxially growing a semiconductor single crystal silicon thin film over the transparent substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: June 2, 1998
    Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 5670388
    Abstract: Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: September 23, 1997
    Assignee: International Business Machines Corporation
    Inventors: Brian John Machesney, Jack Allan Mandelman, Edward Joseph Nowak
  • Patent number: 5652158
    Abstract: A method of manufacturing thin film transistors for use in a liquid crystal display which reduces the failures due to excessive leakage current. A silicon layer, first insulating layer, and gate electrode layer are serially formed over a transparent substrate. The gate electrode layer is patterned to form a plurality of gate electrodes and associated pairs of gate line electrodes, and the silicon layer is patterned into thin-film transistor regions. Then, a relatively thick second insulating layer is formed over the substrate, and contact holes are formed in the second insulating layer. Finally, a metal layer is formed and patterned over the second insulating layer and through the contact holes to connect each gate electrode with its associated pair of gate line electrodes; and to form source and drain electrodes.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: July 29, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byung Seong Bae
  • Patent number: 5641691
    Abstract: A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: June 24, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Eric N. Cartagena, Howard W. Walker
  • Patent number: 5614433
    Abstract: An SOI integrated circuit contains Al implanted below the channel areas of NFETs and has a positive substrate bias, the magnitude of the substrate bias and the implant dose being set such that the bias suppresses backside leakage in the PFETs and the implant dose suppresses leakage in the NFEts in spite of the bias.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: March 25, 1997
    Assignee: International Business Machines Corporation
    Inventor: Jack A. Mandelman
  • Patent number: 5604139
    Abstract: In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: February 18, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsufumi Codama, Ichiro Takayama, Michio Arai
  • Patent number: 5597738
    Abstract: A method for fabricating a single crystal silicon on insulator material by forming oxidized layers underneath epi islands without damaging the surface quality of the silicon. In an illustrative embodiment, an epitaxial layer of p-type silicon is grown on a substrate of n-type silicon. A plurality of islands are defined from the epitaxial layer. A semiconductor device is fabricated from one of the p-islands by electrochemically anodizing a region of the substrate beneath that p-island, which p-island can be used to fabricate a selected semiconductor device. If n-type material is required for device fabrication, a device layer of n-type silicon can be grown on the surface of a p-islands and that p-island can be anodized and oxidized to form the insulating layer between the device layer and substrate. In this manner, MOS transistors and other devices may be fabricated for operation at temperatures of up to 500.degree. C.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: January 28, 1997
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Anthony D. Kurtz, Joseph S. Shor, Alexander A. Ned
  • Patent number: 5591678
    Abstract: A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58') therein that can be electrically interconnected to the microelectronic circuit element (50).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 7, 1997
    Assignee: HE Holdings, Inc.
    Inventors: Joseph J. Bendik, Gerard T. Malloy, Ronald M. Finnila
  • Patent number: 5587330
    Abstract: In producing a top gate type insulated gate semiconductor device in which a non-single crystalline semiconductor layer is used to form a channel forming region, after a gate electrode is formed on the non-single crystalline semiconductor layer through a gate insulating film, while ultraviolet light is irradiated to the non-single crystalline semiconductor layer, heating treatment is performed at a temperature of from 300.degree. to 600.degree. C. in an atmosphere containing nitrogen oxide or hydrogen nitride, in order to neutralize a recombination center in the non-single crystalline film or a boundary between the non-single crystalline film and the gate insulating film.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: December 24, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5583059
    Abstract: A SiGe-HBT structure for device integration on thin-SOI substrates is disclosed. The emitter and base regions are vertical while the collector contact is lateral in the otherwise MOS-like device structure. This allows one to integrate a SiGe base, the device capacitances are reduced, and the transistor can be combined with fully-depleted CMOS in a SOI-BiCMOS technology.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: December 10, 1996
    Assignee: International Business Machines Corporation
    Inventor: Joachim N. Burghartz
  • Patent number: 5573960
    Abstract: A method of manufacturing a semiconductor layer includes preparing a first semiconductor substrate; forming an etching stop layer on the surface of the first substrate; forming an active layer on the etching stop layer; forming a crystal defect reducing layer on the active layer; preparing a second semiconductor substrate having a heat conductivity higher than the heat conductivity of the first substrate; bonding the crystal defect reducing layer to the second substrate; selectively etching the first substrate to expose the etching stop layer; selectively etching the etching stop layer to expose the active layer, whereby the active layer is disposed on the second substrate with the crystal defect reducing layer therebetween. The heat dissipation property is significantly improved by the second substrate having a high heat conductivity and by reducing the thicknesses of the active layer and the crystal defect reducing layer.
    Type: Grant
    Filed: July 10, 1995
    Date of Patent: November 12, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigekazu Izumi, Norio Hayafuji
  • Patent number: 5550066
    Abstract: A method of making a 4-terminal active matrix electroluminescent device that utilizes an organic material as the electroluminescent medium is described. In this method, thin film transistors are formed from polycrystalline silicon at a temperature sufficiently low such that a low temperature, silica-based glass can be used as the substrate.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: August 27, 1996
    Assignee: Eastman Kodak Company
    Inventors: Ching W. Tang, Biay C. Hseih
  • Patent number: 5547883
    Abstract: A thin film transistor having increased channel length and self-aligned source and drain regions is fabricated by forming a gate electrode on an insulation film disposed on a substrate. Portions of the insulation film are then etched on opposite sides of the gate electrode, as well as beneath part of the gate electrode. A gate insulation film is then formed on the entire exposed surface of the gate electrode, and a semiconductor layer is then formed on the entire gate insulation film, as well as portions of the insulation film. Doping impurities may then be implanted at an angle other than 90.degree. to the surface of the substrate to achieve a thin film transistor having an extended channel length but occupying a relatively small area on the surface of the substrate.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: August 20, 1996
    Assignee: Lg Semicon Co., Ltd.
    Inventor: In Kim
  • Patent number: 5543338
    Abstract: An insulated semiconductor area (10a) and an insulated semiconductor area (10b) are provided in the substrate, and a gate electrode (16a) and a gate electrode (16b) is formed above the insulated semiconductor areas (10a) and (10b), respectively. After masking the semiconductor area (10a), boron atoms are implanted via such a beam that the boron atoms can be injected selectively into only the semiconductor area under the gate electrode (16b) in order to create a channel region (20b). Furthermore, the arsenic atoms are implanted via such a second beam that the arsenic atoms are injected selectively into only the semiconductor area except the semiconductor area under the gate electrode (16b) in order to create a source (22b) and a drain (22b).
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: August 6, 1996
    Assignee: Rohm Co., Ltd
    Inventor: Noriyuki Shimoji
  • Patent number: 5532175
    Abstract: A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: July 2, 1996
    Assignee: Motorola, Inc.
    Inventors: Marco Racanelli, Bor-Yuan C. Hwang, Juergen Foerstner, Wen-Ling M. Huang
  • Patent number: 5525527
    Abstract: A process for producing an array of solid state radiation detectors includes depositing on a substrate one or more layers of silicon-based materials and then depositing a metal layer overlying silicon-based substance. The metal layer is formed into an array of metal layer regions, and then the metal layer is used as a mask to remove exposed adjacent silicon-based substance layers thereby forming an array of silicon-based substance layers that are aligned with the array of metal layers for forming an array of photosensitive sensing devices. The process of the present invention reduces the number of microlithography steps that are used in forming an array of layered amorphous silicon photosensitive devices.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: June 11, 1996
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: Nang T. Tran
  • Patent number: 5518949
    Abstract: The present invention is related to an isolation method for SOI (Silicon on Insulator) devices on an SOI wafer having a silicon substrate, a buried dielectric layer formed on the silicon substrate and a silicon film layer formed on the buried dielectric layer.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: May 21, 1996
    Assignee: Winbond Electronics Corporation
    Inventor: Hengtien H. Chen
  • Patent number: 5512501
    Abstract: In etching a polysilicon layer above a gate electrode layer, a portion of the gate electrode layer is left thereunder. The etching process of that polysilicon layer and that gate electrode layer is carried out in two steps of etching the polysilicon layer and an interlayer insulating layer, and etching the gate electrode layer and the gate oxide film. Therefore, the amount that is removed from an SOI layer can be suppressed in the manufacturing process thereof.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: April 30, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideto Hidaka, Takahiro Tsuruda, Katsuhiro Suma
  • Patent number: 5504019
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: April 2, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: 5488005
    Abstract: A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: January 30, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Ku Han, Byung-Hyuk Min
  • Patent number: 5488012
    Abstract: A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: January 30, 1996
    Assignee: The Regents of the University of California
    Inventor: Anthony M. McCarthy
  • Patent number: 5480818
    Abstract: A crystal silicon film deposited on an insulating film made of a binary system material or a binary system semiconductor film formed by an atomic layer deposition method has a grain as large as approximately 200 nm. Thus, the mobility of carriers is increased. The crystal silicon thereof is grown within a temperature range of 250.degree. C. to 400.degree. C. Accordingly, when a planar type thin film transistor, an inverted stagger type thin film transistor or a stagger type thin film transistor is formed using crystal silicon formed on these films made of a binary system material, transistor characteristics thereof are improved.
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: January 2, 1996
    Assignee: Fujitsu Limited
    Inventors: Tomotaka Matsumoto, Jun Inoue, Teruhiko Ichimura, Yuji Murata, Junichi Watanabe, Yoshio Nagahiro, Mari Hodate, Kenichi Oki, Masahiro Okabe
  • Patent number: 5476813
    Abstract: In a method of manufacturing a bonded semiconductor substrate, a SiGe mixed crystal layer, a silicon layer containing N-type impurities, a SiGe mixed crystal layer containing N-type impurities of high concentration, and a silicon layer containing N-type impurities of high concentration are formed in this order on a top surface of a silicon substrate by an epitaxial growth process to form a first semiconductor substrate. A silicon oxide film is formed on a surface of a silicon substrate to form a second semiconductor substrate. The first and second semiconductor substrates are bonded to each other by heat treatment, with their top surfaces contacting each other. The first semiconductor substrate is etched from the back surface thereof until the SiGe mixed crystal layer is exposed, and the SiGe mixed crystal layer is etched until the silicon layer containing N-type impurities is exposed. This method prevents the thickness of the element forming layer from varying.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: December 19, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Naruse
  • Patent number: 5468674
    Abstract: A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: November 21, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Howard W. Walker, Graham A. Garcia
  • Patent number: 5466617
    Abstract: Body portions (36) of semiconductor crystalline silicon material of sufficient quality to form high-mobility TFTs (thin-film transistors) and other semiconductor devices of a driver circuit are formed by depositing on a substrate (14) a layer of insulating silicon-based non-stoichiometric compound material (32) and then converting this material (32) into the semiconductive crystalline material (36) by heating with an energy beam (40), for example from an excimer laser. The use of an energy beam (40) permits easy localization of the heating (and consequent conversion) both vertically and laterally. The deposition (e.g. by plasma-enhanced chemical vapour deposition) and the beam annealing can both be carried out without heating the substrate (14) to high temperatures, and so a glass or other low-cost substrate (14) can be used. An unconverted part (32a) underlying the crystalline silicon body portion (36) can form at least part of a gate insulator of the TFT.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: November 14, 1995
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 5462885
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: October 31, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5441591
    Abstract: A method of bonding silicon to sapphire may be performed at room temperature and with no greater pressure than that due to one wafer resting on another. The method comprises the steps of polishing one side of a flat sapphire wafer to a mirror-like surface; polishing one side of a flat silicon wafer to a mirror-like surface; cleaning the wafers and then stacking the wafers so that their corresponding mirror-like surfaces contact. The room temperature bonding that occurs is relatively strong, and the bonded wafers can be handled without danger of their becoming unbonded. If desired, the bonded wafers may be subjected to further processing to further strengthen their bond.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: August 15, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: George P. Imthurn, Howard Walker
  • Patent number: 5439836
    Abstract: Method for producing a silicon technology transistor on a nonconductor. This method consists in particular of forming a thin film of silicon (6) on a nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel (26) of the transistor; of locally oxidizing (14) the unmasked silicon to form an oxidation film; of eliminating the mask; of forming source (18) and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask this implantation; of eliminating the oxidation film; and of forming a thin gate nonconductor between the source and the drain and then forming the gate.
    Type: Grant
    Filed: July 13, 1994
    Date of Patent: August 8, 1995
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Benoit Giffard
  • Patent number: 5438014
    Abstract: A polycrystalline silicon film pattern 3 having a thickness of below 120 nm is formed on a silicon oxide film 2 provided on the principal surface of a silicon substrate 1. The polycrystalline silicon film pattern 3 is covered with a boron silicate glass film 4. By heat treatment, boron is diffused from the boron silicate glass film 4 to the polycrystalline silicon film pattern 3 to form a polycrystalline silicon resistance element 5 containing boron at a density of above 1.times.10.sup.19 atoms/cm.sup.3. As a result, the temperature coefficient of the resistance element 5 comprising the polycrystalline film can be reduced.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: August 1, 1995
    Assignee: NEC Corporation
    Inventor: Takasuke Hashimoto
  • Patent number: 5426064
    Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200.ANG., thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.
    Type: Grant
    Filed: March 8, 1994
    Date of Patent: June 20, 1995
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hognyong Zhang, Hideki Uochi, Toru Takayama, Yasuhiko Takemura
  • Patent number: 5426062
    Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried (p)-layer (16) and a buried (n)-well region (26) are formed in order to position (p)-(n) junctions beneath (n)-channel and (p)-channel devices respectively formed in the outer silicon layer (14) outwardly from the (p)-layer (16) and (n)-well (26).
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: June 20, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Jeong-Mo Hwang
  • Patent number: 5424230
    Abstract: An amorphous silicon hydride thin film is deposited on an insulating body by a plasma CVD method, and is then heated for dehydrogenating the amorphous silicon thin film so that a dehydrogenated amorphous silicon thin film containing hydrogen of 3 atomic % or less is formed. The insulating body may be an insulating substrate (such as a glass substrate) alone, or a combination of an insulating substrate with an intermediate insulating base layer thereon. Impurity ions are injected into the dehydrogenated amorphous silicon hydride thin film to form source and drain regions. Excimer laser beams are applied to the dehydrogenated amorphous silicon thin film, thereby polycrystallizing the amorphous silicon thin film into a polysilicon thin film and activating the injected impurity ions.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: June 13, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventor: Haruo Wakai
  • Patent number: 5420048
    Abstract: An SOI-type thin film transistor having a transparent insulating substrate a first gate electrode, a first gate insulating film, a semiconductor layer, a second gate electrode and a second gate insulating film which are respectively formed on the transparent insulating substrate, wherein the width of the first gate electrode and that of the second gate electrode are different from each other and as well as the thickness of the first gate insulating film and that of the second gate insulating film are different from each other.
    Type: Grant
    Filed: December 31, 1991
    Date of Patent: May 30, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigeki Kondo
  • Patent number: 5413958
    Abstract: An amorphous silicon film is formed on a glass substrate by a CVD method, and then the island regions of the amorphous silicon film is changed to a plurality of polycrystalline silicon regions which are arranged in a line and apart with each other in a predetermined distanced by intermittently irradiating laser pulses each having the same dimensions as those of the island region onto the amorphous silicon film, using a laser beam irradiating section. Switching elements including the island regions as semiconductor regions are formed by etching and film-forming process to constitute a driving circuit section. The section is divided to gate driving circuit sections and source driving circuit sections for driving thin film transistors formed in a pixel region.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: May 9, 1995
    Assignee: Tokyo Electron Limited
    Inventors: Issei Imahashi, Kiichi Hama, Jiro Hata
  • Patent number: 5407845
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: April 18, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5405795
    Abstract: An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.
    Type: Grant
    Filed: June 29, 1994
    Date of Patent: April 11, 1995
    Assignee: International Business Machines Corporation
    Inventors: Klaus D. Beyer, Taqi N. Buti, Chang-Ming Hsieh, Louis L. Hsu
  • Patent number: 5401665
    Abstract: A field-effect transistor in which a metal gate (14) is defined on top of an insulating substrate (12). A free-standing semiconductor thin film (16), obtained by the epitaxial lift-off process, is bonded to both the top of the metal gate and the insulating substrate. Electrodes (20, 22) attached to the top of ends of the semiconductor film complete the transistor.
    Type: Grant
    Filed: January 5, 1994
    Date of Patent: March 28, 1995
    Assignee: Bell Communications Research, Inc.
    Inventor: Winston K. Chan
  • Patent number: 5397718
    Abstract: In a method of manufacturing a thin film transistor, when impurity ions are introduced in a channel region between source and drain regions in a semiconductor layer, an insulator layer is first formed on the semiconductor layer. Then, impurity ions generated on high frequency discharge are introduced through the insulator layer into the semiconductor layer under a specified acceleration voltage. Then, the introduction depth of impurities and the amount of the impurities to be introduced in the channel region can be controlled or the threshold voltage of the thin film transistor can be controlled. This method can be applied to a large substrate.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: March 14, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mamoru Furuta, Tetsuya Kawamura, Tatsuo Yoshioka, Hiroshi Sano, Yutaka Miyata
  • Patent number: 5395481
    Abstract: A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: March 7, 1995
    Assignee: Regents of the University of California
    Inventor: Anthony M. McCarthy
  • Patent number: 5395788
    Abstract: The present invention provides a method of making a semiconductor substrate having an SOI structure by temporarily bonding together two wafers having different thermal expansion coefficients to allow thinning of at least one of the wafers by chemical and/or mechanical treatment(s) to reduce the risk of strain, separation, cracks to the wafers followed by one or more heat treating steps to fully bond the wafers together. The method can produce semiconductor substrate having an SOI structure which can provide a silicon layer thin enough to allow various integrated circuits, or TFL-LCD or the like to be formed.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: March 7, 1995
    Assignee: Shin Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Yasuaki Nakazato, Atsuo Uchiyama
  • Patent number: 5389580
    Abstract: A thin film semiconductor device having a silicon thin film semiconductor layer deposited on an ordinary glass substrate at low temperatures of not over 600.degree. C. The silicon film has at least about a 40% degree of crystallinity and mainly {111} preferred orientation. The thin film can be formed by a low pressure chemical vapor deposition process using monosilane (SiH.sub.4) as a source gas at a total reactor pressure of about 15 mTorr or less or at a silane partial pressure of about 10 mTorr or less at a vapor phase deposition temperature of not more than about 600.degree. C.
    Type: Grant
    Filed: December 27, 1993
    Date of Patent: February 14, 1995
    Assignee: Seiko Epson Corporation
    Inventor: Mitsutoshi Miyasaka
  • Patent number: 5376561
    Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: December 27, 1994
    Assignee: Kopin Corporation
    Inventors: Duv-Pach Vu, Brenda Dingle, Ngwe Cheong
  • Patent number: 5374572
    Abstract: The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: December 20, 1994
    Assignee: Motorola, Inc.
    Inventors: Scott S. Roth, William C. McFadden, Alexander J. Pepe
  • Patent number: 5374567
    Abstract: A method for fabricating low leakage current bipolar junction transistors of silicon-on-sapphire for efficient use in operational amplifiers utilizes all implant technology, improved silicon conditioning processing, and low temperature annealing.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: December 20, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Eric N. Cartagena
  • Patent number: 5372958
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: December 13, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: H1637
    Abstract: The fabrication of bipolar junction transistors in silicon-on-sapphire (SOS) relies upon the laser-assisted dopant activation in SOS. A patterned 100% aluminum mask whose function is to reflect laser light from regions where melting of the silicon is undesirable is provided on an SOS wafer to be processed. The wafer is placed within a wafer carrier that is evacuated and backfilled with an inert atmosphere and that is provided with a window transparent to the wavelength of the laser beam to allow illumination of the masked wafer when the carrier is inserted into a laser processing system. A pulsed laser (typically an excimer laser) beam is appropriately shaped and homogenized and one or more pulses are directed onto the wafer. The laser beam pulse energy and pulse duration are set to obtain the optimal fluence impinging on the wafer in order to achieve the desired melt duration and corresponding junction depth.
    Type: Grant
    Filed: September 18, 1991
    Date of Patent: March 4, 1997
    Inventors: Bruce W. Offord, Stephen D. Russell, Kurt H. Weiner