Single Crystal On Amorphous Substrate Patents (Class 148/DIG152)
-
Patent number: 5773340Abstract: A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.Type: GrantFiled: November 28, 1995Date of Patent: June 30, 1998Assignee: Hitachi, Ltd.Inventors: Takahiro Kumauchi, Takashi Hashimoto, Osamu Kasahara, Satoshi Yamamoto, Yoichi Tamaki, Takeo Shiba, Takashi Uchino
-
Patent number: 5674777Abstract: The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).Type: GrantFiled: December 14, 1995Date of Patent: October 7, 1997Assignee: National Science CouncilInventors: Tung-Po Chen, Tan-Fu Lei, Chun-Yen Chang
-
Patent number: 5610094Abstract: A photoelectric conversion device of the type having a photosensor region and a circuit section for processing at least an output signal from the photosensor region, wherein on a first layer formed with an electronic element constituting the circuit section, a second layer with a deposition surface is formed directly or through an interposed insulation layer, and wherein at least one of the electronic element and the photosensor is formed in a crystal layer which has grown from a single nucleus formed on a nucleus forming region on the deposition surface of the second layer, the single nucleus being sufficiently fine for making only a single crystal grow and having a sufficiently high nucleation density than that of the material of the second layer surface.Type: GrantFiled: June 7, 1995Date of Patent: March 11, 1997Assignee: Canon Kabushiki KaishaInventors: Masaharu Ozaki, Takao Yonehara
-
Patent number: 5597738Abstract: A method for fabricating a single crystal silicon on insulator material by forming oxidized layers underneath epi islands without damaging the surface quality of the silicon. In an illustrative embodiment, an epitaxial layer of p-type silicon is grown on a substrate of n-type silicon. A plurality of islands are defined from the epitaxial layer. A semiconductor device is fabricated from one of the p-islands by electrochemically anodizing a region of the substrate beneath that p-island, which p-island can be used to fabricate a selected semiconductor device. If n-type material is required for device fabrication, a device layer of n-type silicon can be grown on the surface of a p-islands and that p-island can be anodized and oxidized to form the insulating layer between the device layer and substrate. In this manner, MOS transistors and other devices may be fabricated for operation at temperatures of up to 500.degree. C.Type: GrantFiled: March 6, 1995Date of Patent: January 28, 1997Assignee: Kulite Semiconductor Products, Inc.Inventors: Anthony D. Kurtz, Joseph S. Shor, Alexander A. Ned
-
Patent number: 5238879Abstract: A method for producing polycrystalline layers having granular crystalline structure is provided. Pursuant to the method, a thin intermediate layer of amorphous is deposited before the deposition of the polycrystalline layer in order to avoid crystal structure influence proceeding from the substrate. The layer is then recrystallized applying a pattern of crystallization points or the amorphous layer. A detrimental effect of the fine-crystalline structure of the substrate is prevented by the amorphous intermediate layer. Pursuant to the present invention, the thin-film technology can also be utilized for polycrystalline silicon layers, this being especially desirable in the manufacture of solar cells.Type: GrantFiled: September 6, 1991Date of Patent: August 24, 1993Assignee: Siemens AktiengesellschaftInventor: Rolf Plaettner
-
Patent number: 5087296Abstract: A solar battery comprises a substrate, a first semiconductor layer of a first conduction type comprising a single crystal singly grown on a nucleation surface (S.sub.NDL) formed on the surface of said substrate as the base for growing, said nucleation surface (S.sub.NDL) being comprised of a material which is sufficiently greater in nucleation density (ND) than the material constituting the surface of said substrate and having a sufficiently fine area such that only a single nucleus grows, a second semiconductor layer of a second conduction type different than the conduction type of said first semiconductor layer and means for taking out the power.Type: GrantFiled: November 8, 1990Date of Patent: February 11, 1992Assignee: Canon Kabushiki KaishaInventors: Shigeki Kondo, Hidemasa Mizutani
-
Patent number: 5077235Abstract: A method of manufacturing a semiconductor integrated circuit device having a SOI structure includes the following steps. The first step is to form a semiconductor layer on a dielectric substrate. The second step is to form an oxide layer on the formed semiconductor layer. The third step is to form a nitride layer on the formed oxide layer. The fourth step is to remove a part of a plurality of layers composed of the semiconductor layer, the oxide layer, and a nitride layer so as to form a separated region in the layers. The fifth step is to coat a cooling agent on a surface of the nitride layer. The sixth step is to irradiate an energy beam from an outer surface of the cooling agent so as to monocrystallize the semiconductor layer. The seventh step is to remove the cooling agent from the surface of the nitride layer. And the final step is to oxidize a portion of the semiconductor layer located in the separated region by using the nitride layer.Type: GrantFiled: January 16, 1990Date of Patent: December 31, 1991Assignee: Ricoh Comany, Ltd.Inventor: Daisuke Kosaka
-
Patent number: 5066610Abstract: Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in present in cap fracture and enhancing crystal quality but is also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.Type: GrantFiled: September 22, 1989Date of Patent: November 19, 1991Assignee: Massachusetts Institute of TechnologyInventors: Chenson K. Chen, Bor-Yeu Tsaur
-
Patent number: 5049522Abstract: A depression is formed by mesa etching or the like in the surface of an insulative substrate. A first semiconductive layer structure such as a PNP layer structure is formed on the surface including the depression. An electrically insulative isolation layer is formed on the first layer structure, and then a second layer structure such as an NPN layer structure is formed on the isolation layer. The area over the depression is then masked, and the second layer structure and isolation layer are etched away from the first layer structure over areas of the surface external of the depression. Where the thicknesses of the first and second layer structures are equal, and the depth of the depression is equal to the combined thicknesses of the first layer structure and the isolation layer, the second layer structure laterally external of the depression will be coplanar with the first layer structure over the depression.Type: GrantFiled: February 9, 1990Date of Patent: September 17, 1991Assignee: Hughes Aircraft CompanyInventors: William E. Stanchina, Lawrence E. Larson
-
Patent number: 5013670Abstract: A photoelectric conversion device includes a light transmissive substrate having a deposition surface and a bottom surface. The bottom surface receives light and passes it through the substrate. A heterogeneous deposition surface is formed on the substrate deposition surface and has a nucleation density higher than the nucleation density of the substrate deposition surface. The heterogeneous deposition surface also has an area dimensioned to permit growth of a single nucleus of a single crystal material. A photoelectric conversion collector is formed of the single crystal material grown on the heterogeneous deposition surface. The collector receives light passed through the substrate bottom surface. Photoresponsive transistor elements are formed in and on the collector for outputting a signal corresponding to the light received by the collector through the bottom of the light transmissive substrate.Type: GrantFiled: May 15, 1990Date of Patent: May 7, 1991Assignee: Canon Kabushiki KaishaInventors: Shiro Arikawa, Takao Yonehara
-
Patent number: 5010033Abstract: A process for producing a compound semiconductor comprises applying a crystal forming treatment on a substrate having a free surface comprising a nonnucleation surface (S.sub.NDS) with smaller nucleation density and a nucleation surface (S.sub.NDL) arranged adjacent thereto having a sufficiently small area for a crystal to grow only from a single nucleus and a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS), by exposing the substrate to either of the gas phases:(a) gas phase (a) containing a starting material (II) for feeding the group II atoms of the periodic table and a starting material (VI) for feeding the group VI atoms of the periodic table and(b) gas phase (b) containing a starting material (III) for feeding the group III atoms of the periodic table and a starting material (V) for feeding the group V atoms of the periodic table, thereby forming only a single nucleus on said nucleation surface (S.sub.Type: GrantFiled: April 30, 1990Date of Patent: April 23, 1991Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Kenji Yamagata, Takao Yonehara
-
Patent number: 5008206Abstract: A photoelectric conversion apparatus comprising a transistor having a main electrode area of one conductive type semiconductor and a control electrode area of an opposite conductive type semiconductor, and a capacitor for controlling the potential of the control electrode area in floating state in which carriers produced optically are stored in the control electrode area by controlling the potential of the control electrode area via the capacitor. The apparatus comprises a multilayered structure in which switching device for setting the control electrode area to a desired potential is formed on a layer different from that on which the transistor and capacitor are formed.Type: GrantFiled: May 24, 1989Date of Patent: April 16, 1991Assignee: Canon Kabushiki KaishaInventors: Mahito Shinohara, Takao Yonehara
-
Patent number: 5008215Abstract: A process for preparing high sensitivity indium antimonide film magnetoresistance element. A silicon single crystal wafer is treated with oxidative diffusion to form a layer of silicon oxide on the surface of the silicon single crystal, a layer of indium antimonide is grown on the substrate by vapor deposition, and the indium antimonide layer is then subjected to a specific annealing treatment in which the indium antimonide layer is partially oxidized and then re-crystallized. The resultant magnetoresistance element possessing improved sensitivity, stability and suitable for large scale production is obtained.Type: GrantFiled: July 7, 1989Date of Patent: April 16, 1991Assignee: Industrial Technology Research InstituteInventors: Duen J. Chen, Guey F. Chi, Ying C. Yeh
-
Patent number: 4999313Abstract: There is provided a semiconductor article together with a process for producing the same which article has a plurality of semiconductor single crystal regions comprising a semiconductor single crystal region of one electroconductive type and a semiconductor single crystal region of the opposite electroconductive type on the same insulator substrate. At least the semiconductor single crystal region of one electroconductive type being provided by forming a different material which is sufficiently greater in nucleation density than the material of the insulator substrate and sufficiently fine to the extent that only one single nucleus of the semiconductor material can grow and then permitting the semiconductor material to grow around the single nucleus formed as the center.Type: GrantFiled: May 29, 1990Date of Patent: March 12, 1991Assignee: Canon Kabushiki KaishaInventors: Shiro Arikawa, Takao Yonehara
-
Patent number: 4990464Abstract: An improved technique for forming silicon-on insulator films for use in integrated circuits. The technique provides an improved encapsulation layer to enable in a reproducible way the zone melt recrystallization of such films. The encapsulation layer consists of a first layer of a doped SiO.sub.2 (silicate glass) on which a further layer of Si.sub.3 N.sub.4 is deposited. The doped SiO.sub.2 forms a fusible glassy material which is rendered semi-liquid and flows at the temperatures used in recrystallization. The softening of the encapsulation material accommodates volume expansion and eliminates the biaxial stresses in the layered structure. The Si.sub.3 N.sub.4 layer adds mechanical strength to the SiO.sub.2 layer and improves the wetting angle.Type: GrantFiled: December 30, 1988Date of Patent: February 5, 1991Assignee: North American Philips Corp.Inventors: Helmut Baumgart, Andre Martinez
-
Patent number: 4977096Abstract: An image photodetector includes a photosensor unit, a charge storage unit, and a switch unit, all of them are formed on a single-crystal semiconductor film grown from a single nucleus such that crystal formation is performed on a substrate having a free surface including a non-nucleus formation surface and a nucleus formation surface adjacent thereto. The non-nucleus formation surface has a low nucleation density. The nucleus formation surface has a sufficiently small area to allow growth of only the single nucleus and has a higher nucleation density that that of the non-nucleus formation surface.Type: GrantFiled: May 25, 1989Date of Patent: December 11, 1990Assignee: Canon Kabushiki KaishaInventors: Tetsuya Shimada, Satoshi Itabashi, Katsunori Hatanaka
-
Patent number: 4910165Abstract: A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate.Type: GrantFiled: November 4, 1988Date of Patent: March 20, 1990Assignee: NCR CorporationInventors: Steven S. Lee, Dim-Lee Kwong
-
Patent number: 4902642Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).Type: GrantFiled: August 24, 1988Date of Patent: February 20, 1990Assignee: Texas Instruments, IncorporatedInventors: Bor-Yen Mao, Richard L. Yeakley
-
Patent number: 4888302Abstract: A defect free monocrystalline layer of silicon on an insulator is produced by forming a thin layer of silicon dioxide on a monocrystalline silicon substrate, forming a thin layer of polycrystalline or amorphous silicon on the silicon dioxide layer and focussing two beams from lamps on the thin silicon layer to form a line image providing a melt zone surrounded by two narrow heated zones having temperatures lower than the melt zone and having a temperature differential of from 2.degree.-10.degree. C./mm decreasing form the melt zone while heating the substrate to a temperature below that of the zones heated by the lamps and scanning the structure.Type: GrantFiled: March 29, 1989Date of Patent: December 19, 1989Assignee: North American Philips CorporationInventor: Subramanian Ramesh
-
Patent number: 4834809Abstract: A semiconductor substrate includes: a first monocrystalline semiconductive layer formed on the surface of a crystalline silicon substrate with the intervension of a first insulation film; a second insulation film set to the upper surface of the first monocrystalline semiconductive layer and provided with a plurality of apertures each having a specific pattern; and a second monocrystalline semiconductive layer which is epitaxially grown by the seed crystallization process and provided with the same crystalline characteristics as that of the first monocrystalline semiconductive layer.Accordingly, the preferred embodiment of the present invention provides an extremely useful semiconductor substrate which easily isolates the elements of semiconductor devices between layers of insulating film described above.Type: GrantFiled: September 9, 1987Date of Patent: May 30, 1989Assignee: Sharp Kabushiki KaishaInventor: Yoshinobu Kakihara
-
Patent number: 4760036Abstract: A process for growing silicon on insulator in which complete isolation of the grown silicon of the substrate silicon by an intermediate oxide layer is obtained. A first epitaxial lateral overgrowth technique is used to grow a continuous layer of silicon through seed holes in a patterned oxide layer overlying the silicon substrate. Then the silicon layer is etched to expose the seed holes which are then oxidized to make the oxide layer aperture-free. This is followed by a second epitaxial lateral overgrowth step to replace the silicon etched in the silicon layer to make the layer substantially planar.Type: GrantFiled: June 15, 1987Date of Patent: July 26, 1988Assignee: Delco Electronics CorporationInventor: Peter J. Schubert
-
Patent number: 4731318Abstract: A novel MOS transistor structure comprises electrodes of metallic silicide and especially tantalum silicide. In the case of the gate electrode, the silicide is directly in contact with an insulating thin-film layer. In the case of the drain and source electrodes, the silicide is directly in contact with the monocrystalline silicon. The method of fabrication is thus simplified while avoiding the use of polycrystalline silicon.Type: GrantFiled: February 24, 1986Date of Patent: March 15, 1988Assignee: Societe pour l'Etude et la Fabrication des Circuits Integres Speciaux - E.F.C.I.S.Inventors: Alain Roche, Joseph Borel
-
Patent number: 4657603Abstract: A method for the manufacture of gallium arsenide thin film solar cells on inexpensive substrate material whereby an intermediate layer of highly doped, amorphous germanium is employed in order to promote the growth of the gallium arsenide layers. A high-energy radiation is directed to specific, prescribed points on the highly doped, amorphous germanium layer thereby generating centers having a defined crystal orientation, so that the epitaxial layer spreads laterally from these centers in a surface-covering fashion during the epitaxial vapor phase deposition. The solar cells produced by designational grain growth can be manufactured with high purity in a simple way and have an efficiency (greater than 20%) comparable to known mono-crystalline solar cells.Type: GrantFiled: September 20, 1985Date of Patent: April 14, 1987Assignee: Siemens AktiengesellschaftInventors: Wolfgang Kruehler, Josef Grabmaier
-
Patent number: 4604159Abstract: Disclosed is a method of forming a large number of monocrystalline silicon regions, of uniform orientation, on the surface of an insulator material. Initially, a large number of island regions of amorphous or polycrystalline silicon, thermally connected to one another in a predetermined direction by connecting regions, are provided. Then such island regions are sequentially melted and regrown in such predetermined direction so as to form the monocrystalline semiconductor regions, with such regions having a uniform orientation. Thereafter, such connecting regions can be removed in order to isolate the island regions. The connecting regions can be formed with gaps, whereby such connecting regions need not be removed. The connecting regions can be formed of materials having a higher heat conductivity than that of the material of the island regions, and/or the connecting regions can have a smaller cross-sectional area at right angles to the predetermined direction than that of the island regions.Type: GrantFiled: June 13, 1984Date of Patent: August 5, 1986Assignee: Hitachi, Ltd.Inventors: Yutaka Kobayashi, Akira Fukami, Takaya Suzuki
-
Patent number: 4565599Abstract: Improvements on the graphoepitaxial process for obtaining epitaxial or preferred orientation films are described wherein a cap of material is formed over the film to be oriented, artificial surface-relief structure may be present in the substrate, the cap, or both, and the film may be heated by irradiation with electromagnetic radiation.Type: GrantFiled: December 10, 1984Date of Patent: January 21, 1986Assignee: Massachusetts Institute of TechnologyInventors: Michael W. Geis, Henry I. Smith, Dimitri A. Antoniadis, Dale C. Flanders