Abstract: In a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.

Abstract: In a horizontal transfer section of a solid state imager, a horizontal transfer efficiency can be improved while other element sections are prevented from being substantially affected. In a solid state imager having a horizontal transfer section comprised of a well-region of a second conductivity type formed on the surface of a semiconductor substrate of a first conductivity type and a signal charge transfer region formed on the surface of the well-region of the second conductivity type, the well-region is formed completely in a depletion state by the implantation of impurities into this well-region. The horizontal transfer efficiency is thus improved.

Abstract: A method for forming a first doped region (24) and a second doped region (26) within a substrate (12). A masking layer (14) overlies the substrate (12). A first region (20) of the masking layer (14) is etched to form a first plurality of openings. A second region (22) of the masking layer (14) is etched to form a single opening or a second plurality of openings different in geometry from the first plurality of openings. A single ion implant step or an equivalent doping step is used to dope exposed portions of the substrate (12). The geometric differences in the masking layer (14) between region (20) and region (22) results in the formation of the first and second doped regions (24 and 26) wherein the first and second doped regions (24 and 26) vary in doping uniformity, doping concentration, and doping junction depth.

Abstract: In a method of manufacturing CMOS transistors, a well that is of a second conductivity type is formed in a semiconductor substrate of a first conductivity type and is surrounded by a high concentration buried layer of the first conductivity type which completely extends around and below the well, and which also constitutes wells of the first conductivity type. The high-concentration buried layer is formed by a self-aligned process, and the potential of the buried layer can be easily fixed from the top of the semiconductor substrate so that a high degree of resistance is obtained to CMOS latch-up.

Abstract: A bipolar transistor has a base region consisting of a graft base region, linking base region and an intrinsic base region, and a diffusion suppressing region of an opposite conductivity type to that of the base region is formed at least at the lower portion of the intrinsic base region. The junction depth of the linking base region is selected to be shallower than that of the intrinsic base region. Since the base to base linking is performed in the linking base region, collision between the intrinsic base region and the graft base region is inhibited, while the diffusion of the base width beyond the diffusion suppressing region is also inhibited. The junction depth of the linking base region is selected to be shallow to prevent the width of the parasitic base from being increased to suppress the side injection effect.

Abstract: A gain waveguide type semiconductor laser oscillating visible light has an N type GaAs substrate of, and a double-heterostructure provided above the substrate to include an InGaP active layer, and first and second cladding layers sandwiching the active layer. The first cladding layer consists of N type InGaAlP, whereas the second cladding layer consists of P type InGaAlP. A P type InGaP layer is formed as an intermediate band-gap layer on the second cladding layer. An N type GaAs current-blocking layer is formed on the intermediate band-gap layer, and has an elongated waveguide opening. A P type GaAs contact layer is formed to cover the current-blocking layer and the opening.

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.

Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble.

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.